L64388 Remote Access Processor (RAPTM) chip generalpurpose, high-perfo
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L64388 Remote Access Processor (RAPTM) Chip
L64388 Remote Access Processor (RAPTM) chip generalpurpose, high-performance communications processor remote access applications, including high-speed Ethernet LAN-to-WAN internetworking. Based Logic's CoreWare® methodology, chip integrates MIPS RISC processor, controller, Ethernet controller, serial wide area network controllers (SWCs) single chip. chip also includes peripheral component interconnect (PCI) interface connecting 33-MHz, 32-bit bus. contains modem interface with integrated voice data ports. Figure illustrates chip general internetworking application. Local data traffic 10/100-Mbit Ethernet server data traffic internetworked with various technologies, including POTS (plain telephone system), ISDN (integrated services digital network), high-speed digital WAN, such ADSL (asymmetric digital subscriber line), DS-1/E-1, DS-3, (hybrid fiber coaxial). Figure Internetworking Application
10/100-Mbit Ethernet
Workstation Ethernet Port
Remote Access Processor
ISDN Basic Rate Interface (BRI) Small Office/ Home Office High Speed Digital (SOHO) ISDN V.34 V.34 Analog Analog High Speed Digital Portable
Workstation
Server
Network Server
Server
1998
Copyright 1995-1998 Logic Corporation. rights reserved.
Features
Full-duplex, 100-Mbit/s 32-bit, 33-MHz interface
Ethernet connection full-duplex data rates Mbit/s (four ports)
HDLC-based connectivity Diagnostic/console port Basic rate ISDN connectivity MiniRISC® CW4011 MIPS
processor (160 MIPS peak, MIPS sustained) interface
Integrated memory controller Scalable connectivity using V.34 modem connectivity Voice connectivity G10®-p 3.3-V, 0.35-µ CMOS
fabrication technology
Real-Time Clock Multichannel controller Multiprotocol hardware support
HDLC, transparent, start/stop communications
272-pin plastic ball grid array
(PBGA) package
Functional Description
Figure shows functional block diagram chip. This section briefly describes major blocks. CW4011 MiniRISC processor based superscalar design, performing native peak MIPS sustained MIPS MHz. connects 16-Kbyte instruction cache 8-Kbyte data cache. caches either direct mapped 2-way associative. CW4011 uses big-endian data formatting. provides boot source option, with source coming either from byte-wide EPROM from bus. multichannel Controller (DMAC) provides seven full-duplex channels. performs burst memory operations programmable lengths words. DMAC supports scatter gather arbitrary byte alignment.
L64388 Remote Access Processor (RAPTM) Chip
Figure Block Diagram
Time Division Multiplexing (TDM) Serial Interface
Port (TSM 1/SWC Port (TSM 2/SWC Port (Codec/SWC Port (GPIO/SWC Ethernet Port (MII)
Port Configuration Multiplexers Time Slot Multiplexers (TSMs) E-110 Ethernet Core GPI/O Voice Codec Interface Line Codec Interface Serial Controller Serial Controller Serial Controller Serial Controller Ethernet Controller
Register
Receive FIFO
Transmit FIFO
Interface Logic
Multichannel Controller
8-Kbyte SRAM
8-Kbyte D-Cache CW4011 MiniRISC Core 16-Kbyte I-Cache
Interface
Memory Register
32-bit Multiply Accumulator Core
Memory Controller
Controller
Interface
Timers
UART
Controller
Local Memory Interface (32-bit SDRAM, 8-bit Flash, 8-bit PHY)
32-bit MHz,
System Clock Reference max) Clock
Console Port (Async)
Boundary Scan
L64388 Remote Access Processor (RAPTM) Chip
Ethernet Interface contains medium independent interface (MII) direct connection external PHY. This interface operates either half full duplex. data transfer rate either Mbits (IEEE 802.3) Mbits (IEEE 802.3u) media access control. automatically retries transmit frames when collision occurs within first bytes. Ethernet interface incorporates Remote Monitoring (RMON) statistics counters support network management. chip contains four multiprotocol serial interfaces. These interfaces support HDLC (high-level data link control), transparent, start/stop protocols. maximum data rate Mbit/s clocked synchronous interfaces. digital (DPLL) nonclocked synchronous interfaces supports data rates Mbits/s. interfaces provide automatic baud rate detection start/stop clock rate measurement externally clocked synchronous lines. Line coding NRZ, NRZI, FM0, programmable option. Figure shows port connectivities. Figure Port Connectivity Options
Ethernet Multiprotocol Ethernet Chip Ethernet Chip ISDN Ethernet ISDN V.34 ISDN
Multifunction Device V.34 Ethernet Chip ISDN
Peripheral Component Interconnect (PCI) interface complies with revision 2.1. bits wide transfers data MHz. compliant with signalling environments. chip configured either host satellite. Additional LAN/WAN ports, multiple chips, server configurations connect interface. host, chip provides internal arbiter glueless connection satellites. either host satellite mode, interface acts either master slave. contains independent master slave read
L64388 Remote Access Processor (RAPTM) Chip
write FIFOs. provides mailbox host messaging, provides hardware support Intelligent (I2O). contains scatter/gather slave bridge local memory interface. Time Division Multiplexing (TDM) Serial Interface contains independent transmit receive paths that operate data rates MHz. This interface supports ISDN IOM-2, IDL, T1/E1, other applications. connects four bidirectional serial peripheral controllers IOM-2 channels. also connects four HDLC channels, which interconnect Serial controllers. Serial Peripheral Interface (SPI) synchronous, bidirectional interface that used ISDN transceiver management. Modem Interface supports serial ports. first serial port interfaces line codec/DAA analog modem applications. transfers data rates Kbits/s. second serial port interfaces voice codec voice applications. modem interface alternately route V.34 line voice traffic ISDN channel. Universal Asynchronous Receiver/Transmitter (UART) supports start/stop traffic line rates Mbits/s. provides hardware support automatic baud rate detection (ABRD). Timers block comprised four general-purpose 16-bit timers 32-bit watchdog timer. Real-Time Clock (RTC) measures hours, minutes, seconds with 0.04-second resolution. Local Memory Interface contains integrated memory controller 32-bit SDRAMs, 8-bit Flash PROMs, peripheral devices. also contains SDRAM refresh controller. supports Mbytes DRAM Mbytes Flash memory. General-Purpose Interrupt/Control Interface (GPIO) provides programmable, bidirectional pins used additional interrupt inputs control outputs. Controller supports boundary scan testing. chip supports full scan/ATPG IDDQ factory testing.
L64388 Remote Access Processor (RAPTM) Chip
System Example
Figure illustrates typical RAP-based system. chip's connects 10/100-Mbit Ethernet PHY. interfaces connect Siemens 2186 ISDN transceivers. modem interface connects 7546 V.34 data codec voice codec (not shown). Figure RAP-Based System Example
32-bit
Server
Modem
Server 7546 V.34 Codec V.34
Magnetics
Ethernet PHY/PMD
Ethernet Port L64388 Chip Port Local Memory Interface
Siemens 2186 ISDN Transceiver
ISDN Front
Siemens 2186 ISDN Transceiver
ISDN Front
Local Memory
SDRAM
Flash
Flash SDRAM local memory provide storage V.34 modem software, internetworking software, data structures. 32-bit, 3.3/5-volt interface chip connects directly both other communications devices. Multiple chips connected bus, which useful server applications.
L64388 Remote Access Processor (RAPTM) Chip
System Development Tools
software environment will meet your total development needs, from basic reference designs turnkey solutions. software environment package comprised low-level component initialization complete operating systems, device drivers, communication protocol stacks, sample demo application. select only tools need. software environment tools available from either Logic Logic's third party partners. Contact your local sales office more details. Supported Platforms
Workstations Workstations Solaris Windows NT/95
System Development Board
Network Interface Card (NIC) form factor evaluation board
chip evaluation System Development Utilities
PMON (PROM Monitor)-LSI Logic's MIPS family PROM monitors
provides fundamental commands loading debugging software applications that MIPS family processors.
Low-Level Hardware Diagnostics-The chip evaluation board
includes low-level diagnostics that exercise many functions. These diagnostics provide level hardware confidence necessary proper software performance system.
Initialization Configuration Code-The chip evaluation
board package includes reference code that illustrates required start-up code board. designer, this code template build systems specific your individual product requirements. Real-Time Operating Systems
Integrated Systems, Inc. (ISI) pSOS Wind River Systems VxWorks
L64388 Remote Access Processor (RAPTM) Chip
Logic provides support packages evaluation board facilitate quick time-to-market with both these industry-standard, realtime multitasking operating systems. addition, other real-time multitasking operating systems under consideration. Please contact your local sales office availability other operating systems. Communications Drivers
Ethernet Driver HDLC Driver UART Driver
Contact Logic availability these drivers your specific operating system. Third Party Drivers Communications Protocol Stacks
ISDN channel drivers Siemens Motorola ISDN
transceivers
TCP/IP Protocol Stacks Routing Software
Software products boards available from select group third party software vendors your product development needs. Logic selected, integrated, tested these products thoroughly before qualifying them. software listed here been chosen function part combined hardware software system solution, providing faster time-to-market your RAP-based product. Contact Logic complete list products vendors. Tool Chains
Green Hills Software Algorithmics Diab Data Tasking
These vendors support MIPS tool chains supported platforms. They provide compilers, assemblers, linkers, debuggers your complete system development needs.
L64388 Remote Access Processor (RAPTM) Chip
Pinout Mechanical Drawing
chip packaged 272-pin plastic ball grid array (PBGA). Figure shows pinout PBGA package. Figure shows mechanical dimensions this package.
L64388 Remote Access Processor (RAPTM) Chip
Figure 272-Pin PBGA Pinout (VG)
pci_ ad29 pci_ idsel
pci_ ad19
pci_ perrn
pci_ irdyn
pci_ ad17
pci_
pci_
pci_ ad15
pci_
pci_ gntn1 vdd5 pci_
pci_ ad12 pci_ pci_ pci_
pci_ rstn pci_ pci_ intn
sys_ boot
pcsn2
pcsn1
pci_ ad11 bs_tm rtc_clk
pci_ pci_ pci_ pci_ ad23 cben1 stopn devseln vdd5 pci_ pci_ reqn0 ad25 pci_ ad28 pci_ ad30 vdd5 pci_ serrn pci_ pci_ trdyn
pci_ pci_ pci_ pci_ reqn1 ad14 cben3 pci_ ad20 pci_ cben2 pci_ ad16 vdd5 pci_ ad10 pci_ ad13 pci_
vdd5 bs_tclk tm_clk casn lb_wen bs_tdo bs_tdi trstn sys_ nmin sys_ clko
pcsn0 dqmn3 dqmn2
pci_ pci_ cben0 ad21 pci_ ad18 pci_ ad31
lb_rasn
vdd5 pci_ ad27
clken dqmn1 dqmn0 lb_a10 lb_a11 lb_a9 lb_a8
pci_ pci_ ad26 gntn0 pci_ ad24 pci_
pci_ vdd5 ad22 pci_ pci_ framen
lb_a12 test_ lb_a7 lb_a5 lb_a4
lb_a6
lb_a3 scan_
pci_ pci_ mii_col pci_ se_clk se_csn host mii_ rxd0 mii_ rxd1 mii_ rxer mii_ txd0 mii_ txd3 mii_ txer txco mii_ mii_ rxd2 mii_ txclk mii_ txd1 mii_ txen rtsn mii_ rxclk mii_ rxd3 mii_ mdio mii_ txd2 dtrn dcdn ctsn mii_ rxdv mii_ txci txco txci dsrn ctsn
lb_a2 lb_a1 lb_a0
lb_d31 lb_d30 lb_d29 lb_d28
lb_d26 lb_d25 lb_d27
lb_d21 lb_d22 lb_d23 lb_d24
lb_d18 lb_d19 lb_d20
lb_d12 lb_d15 lb_d16 lb_d17 lb_d6 off_ hook dcdn txci dsrn rtsn dtrn ring_
lb_d11 lb_d13 lb_d14
lb_d8 lb_d9 lb_d10 lb_d7
s1_rxc brg_clk dsrn pll_ iddqn rtsn
s3_rxc ctsn
gpio0
u_ctsn
lb_d5 lb_d4
s3_txd txco spi_
txci s4_rxc u_dtrn sdout txco dsrn dcdn ctsn
lb_d1 lb_d3
sys_ sys_ clk_pci
s2_rxc dtrn
lcmclk
u_rtsn dcdn u_sdin gpio1
lb_d2
sys_pll dtrn
dcdn s2_txd rtsn
u_dsrn lb_d0
L64388 Remote Access Processor (RAPTM) Chip
Figure 272-pin PBGA Mechanical Drawing (VG)
MD98.VG
Important:
This drawing latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64388 Remote Access Processor (RAPTM) Chip
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