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Programmable Logic Family April 2000, ver. 1.01 Features.


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ACEX
Programmable Logic Family
April 2000, ver. 1.01
Features.
Preliminary Information
Programmable logic devices (PLDs), providing cost system-on-a-programmable-chip integration single device Enhanced embedded array implementing megafunctions such efficient memory specialized logic functions Dual-port capability with 16-bit width embedded array block (EAB) Logic array general logic functions High density 10,000 100,000 typical gates (see Table 49,152 bits (4,096 bits EAB, which used without reducing logic capacity) Cost-efficient programmable architecture high-volume applications size reductions hybrid process cost solution high-performance communications applications System-level features MultiVoltI/O pins drive driven 2.5-V, 3.3-V, 5.0-V devices power consumption Bidirectional performance (setup time [tSU] clock-tooutput delay [tCO]) Fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation
Table ACEX1K Device Features
Feature
Typical gates Maximum system gates Logic elements (LEs) EABs Total bits Maximum user pins
EP1K10
10,000 56,000 12,288
EP1K30
30,000 119,000 1,728 24,576
EP1K50
50,000 199,000 2,880 40,960
EP1K100
100,000 257,000 4,992 49,152
Altera Corporation
A-DS-ACEX-01.01
ACEX Programmable Logic Family
Preliminary Information
.and More Features
speed grade devices compliant with Local Specification, Revision 5.0-V operation Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic. Operate with 2.5-V internal supply voltage In-circuit reconfigurability (ICR) external configuration devices, intelligent controller, JTAG port ClockLockand ClockBoostoptions reduced clock delay, clock skew, clock multiplication Built-in, low-skew clock distribution trees 100% functional testing devices; test vectors scan chains required Pull-up pins before during configuration Flexible interconnect FastTrack® Interconnect continuous routing structure fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used software tools megafunctions) Tri-state emulation that implements internal tri-state buses global clock signals four global clear signals Powerful pins Individual tri-state output enable control each Open-drain option each Programmable output slew-rate control reduce switching noise Clamp VCCIO user-selectable pin-by-pin basis Supports hot-socketing
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Software design support automatic place-and-route provided Altera's MAX+PLUS® development system Windows-based SPARCstation, 9000 Series 700/800, RISC System/6000 workstations Flexible package options available pins, including innovative FineLine BGApackages (see Tables Additional design entry simulation support provided EDIF netlist files, library parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, other interfaces popular tools from manufacturers such Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, Viewlogic
Table ACEX Package Options Count
Device
EP1K10 EP1K30 EP1K50 EP1K100 Notes:
Notes (1), (2),
208-Pin PQFP
100-Pin TQFP
144-Pin TQFP
256-Pin FineLine
484-Pin FineLine
Contact Altera Customer Marketing up-to-date information package availability. ACEX device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), FineLine packages. Devices same package pin-compatible, although some devices have more pins than others. When planning device migration, pins that common devices. Consult Altera Applications count this package. This option supported with 256-pin FineLine package. using SameFramepin migration, FineLine packages pin-compatible. example, board designed support 256-pin 484-pin FineLine packages.
Table ACEX Package Sizes
Device
Pitch (mm) Area (mm2) Length width
100-Pin TQFP
0.50
144-Pin TQFP
0.50
208-Pin PQFP
0.50 30.6 30.6
256-Pin FineLine
484-Pin FineLine
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
General Description
Altera® ACEX devices provide die-efficient, low-cost architecture combining look-up table (LUT) architecture with EABs. LUT-based logic provides optimized performance efficiency data-path, register intensive, mathematical, digital signal processing (DSP) designs, while EABs implement RAM, ROM, dual-port RAM, first-in first-out (FIFO) functions. These elements make ACEX suitable complex logic functions memory functions such digital signal processing, wide data-path manipulation, data transformation microcontrollers, required high-performance communications applications. Based reconfigurable CMOS SRAM elements, ACEX architecture incorporates features necessary implement common gate array megafunctions, along with high count enable effective interface with system components. advanced process voltage requirement 2.5-V core allow ACEX devices meet requirements low-cost, high-volume applications ranging from modems low-cost switches. ability reconfigure ACEX devices enables complete testing prior shipment allows designer focus simulation design verification. ACEX device reconfigurability eliminates inventory management gate array designs test vector generation fault coverage. Table shows ACEX device performance some common designs. performance results were obtained with Synopsys DesignWare functions. Special design techniques required implement applications; designer simply infers instantiates function Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), schematic design file.
Table ACEX Device Performance
Application Resources Used EABs
16-bit loadable counter 16-bit accumulator 16-to-1 multiplexer 16-bit multiplier with 3-stage pipeline(2) read cycle speed write cycle speed Notes:
This application uses combinatorial inputs outputs. This application uses registered inputs outputs.
Performance Speed Grade
Units
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table shows ACEX device performance more complex designs. These designs available Altera MegaCorefunctions.
Table ACEX Device Performance Complex Designs
Application Used
16-bit, 8-tap parallel finite impulse response (FIR) filter 8-bit, 512-point Fast Fourier transform (FFT) function a16450 universal asynchronous receiver/transmitter (UART) 1,854 47.4
Performance Speed Grade
57.8
Units
76.5 MSPS
Each ACEX device contains embedded array logic array. embedded array used implement variety memory functions complex logic functions, such digital signal processing (DSP), wide data-path manipulation, microcontroller applications, datatransformation functions. logic array performs same function sea-of-gates gate array used implement general logic such counters, adders, state machines, multiplexers. combination embedded logic arrays provides high performance high density embedded gate arrays, enabling designers implement entire system single device. ACEX devices configured system power-up with data stored Altera serial configuration device provided system controller. Altera offers EPC1, EPC2, EPC1441 configuration devices, which configure ACEX devices serial data stream. Configuration data also downloaded from system Altera MasterBlasterTM, ByteBlasterMVTM, ByteBlasterTM, BitBlasterdownload cables. (The ByteBlaster cable obsolete replaced ByteBlasterMV cable, which program configure 2.5-V, 3.3-V, 5.0-V devices.) After ACEX device been configured, reconfigured in-circuit resetting device loading data. Because reconfiguration requires less than real-time changes made during system operation. ACEX devices contain interface that permits microprocessors configure ACEX devices serially parallel, synchronously asynchronously. interface also enables microprocessors treat ACEX device memory configure writing virtual memory location, simplifying device reconfiguration.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
more information configuration ACEX devices, following documents:
Configuration Devices APEX FLEX Devices Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable
ACEX devices supported MAX+PLUS development system, which integrated package that offers schematic, text (including AHDL), waveform design entry, compilation logic synthesis, full simulation worst-case timing analysis, device configuration. MAX+PLUS software provides EDIF LPM, VHDL, Verilog HDL, other interfaces additional design entry simulation support from other industry-standard UNIX workstation-based tools. MAX+PLUS software works easily with common gate array tools synthesis simulation. example, MAX+PLUS software generate Verilog files simulation with tools such Cadence Verilog-XL. Additionally, MAX+PLUS software contains libraries that device-specific features such carry chains, which used fast counter arithmetic functions. instance, Synopsys Design Compiler library supplied with MAX+PLUS development system includes DesignWare functions that optimized ACEX device architecture. MAX+PLUS development system runs Windows-based SPARCstation, 9000 Series 700/800, RISC System/6000 workstations.
Functional Description
more information, MAX+PLUS Programmable Logic Development System Software Data Sheet. Each ACEX device contains enhanced embedded array that implements memory specialized logic functions, logic array that implements general logic. embedded array consists series EABs. When implementing memory functions, each provides 4,096 bits, which used create RAM, ROM, dual-port RAM, first-in first-out (FIFO) functions. When implementing logic, each contribute gates towards complex logic functions such multipliers, microcontrollers, state machines, functions. EABs used independently, multiple EABs combined implement larger functions.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
logic array consists logic array blocks (LABs). Each contains eight local interconnect. consists 4-input LUT, programmable flipflop, dedicated signal paths carry cascade functions. eight used create medium-sized blocks logic-such 8-bit counters, address decoders, state machines-or combined across LABs create larger logic blocks. Each represents about usable logic gates. Signal interconnections within ACEX devices well from device pins) provided FastTrack Interconnect routing structure, which series fast, continuous column channels that entire length width device. Each element (IOE) located each column FastTrack Interconnect routing structure. Each contains bidirectional buffer flipflop that used either output input register feed input, output, bidirectional signals. When used with dedicated clock pin, these registers provide exceptional performance. inputs, they provide setup times hold times outputs, these registers provide clock-to-output times IOEs provide variety features, such JTAG support, slew-rate control, tri-state buffers, open-drain outputs. Figure shows block diagram ACEX device architecture. Each group combined into LAB; groups LABs arranged into rows columns. Each also contains single EAB. LABs EABs interconnected FastTrack Interconnect routing structure. IOEs located each column FastTrack Interconnect routing structure.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX Device Block Diagram
Embedded Array Block (EAB) Element (IOE)
Column Interconnect
Logic Array
Logic Array Block (LAB)
Interconnect
Logic Element (LE)
Local Interconnect Logic Array
Embedded Array
ACEX devices provide dedicated inputs that drive flipflops' control inputs ensure efficient distribution high-speed, lowskew (less than control signals. These signals dedicated routing channels that provide shorter delays lower skews than FastTrack Interconnect routing structure. Four dedicated inputs drive four global signals. These four global signals also driven internal logic, providing ideal solution clock divider internally generated asynchronous clear signal that clears many registers device.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Embedded Array Block
flexible block RAM, with registers input output ports, that used implement common gate array megafunctions. Because large flexible, suitable functions such multipliers, vector scalars, error correction circuits. These functions combined applications such digital filters microcontrollers. Logic functions implemented programming with readonly pattern during configuration, thereby creating large LUT. With LUTs, combinatorial functions implemented looking results rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times EABs. large capacity EABs enables designers implement complex functions single logic level without routing delays associated with linked field-programmable gate array (FPGA) blocks. example, single implement function with inputs outputs. Parameterized functions, such functions, take advantage automatically. ACEX provides timing routing advantages over FPGAs. FPGAs implement on-board arrays small, distributed blocks that must connected together make blocks manageable size. blocks connected using multiplexers implemented with more logic blocks. These extra multiplexers cause extra delay, which, turn, slows down blocks. FPGA blocks also prone routing problems because small blocks connected, forming larger blocks. contrast, ACEX EABs used implement large, dedicated blocks that eliminate these timing routing concerns. ACEX enhanced supports dual-port RAM. dual-port structure ideal FIFO buffers with clocks. ACEX also support 16-bit-wide blocks. ACEX dual-port single-port mode. When dual-port mode, separate clocks used read write sections, allowing written read different rates. also separate synchronous clock enable signals read write sections, which allow independent control these sections. also used bidirectional, dual-port memory applications where ports read write simultaneously. implement this type dual-port memory, EABs used support simultaneous reads writes.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Alternatively, clock clock enable used control input registers EAB, while different clock clock enable control output registers (see Figure
Figure ACEX Device Dual-Port Mode
Dedicated Inputs Global Signals Dedicated Clocks
Note
Interconnect
data[
RAM/ROM Data 1,024 2,048
Data
rdaddress[ Local Interconnect wraddress[
Read Address
Write Address
rden wren outclocken
Read Enable
Write Enable
inclocken
inclock outclock
Write Pulse Generator
Multiplexers allow read address read enable registers clocked inclock outclock signals. Column Interconnect
Notes:
registers asynchronously cleared local interconnect signals, global signals, chip-wide reset. EP1K10, EP1K30, EP1K50 devices have local interconnect channels; EP1K100 devices have local interconnect channels.
Altera megafunctions implement dual-port applications where both ports read write, shown Figure ACEX also used single-port mode (see Figure
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Figure ACEX Dual-Port Mode
Port address_a[] data_a[] we_a clkena_a Clock Port address_b[] data_b[] we_b clkena_b Clock
Figure ACEX Device Single-Port Mode
Dedicated Clocks Dedicated Inputs Global Signals Chip-Wide Reset
Interconnect
RAM/ROM Data 1,024 2,048
Data
Local Interconnect
Address
Write Enable
Column Interconnect
Note:
EP1K10, EP1K30, EP1K50 devices have local interconnect channels; EP1K100 devices have local interconnect channels.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
EABs used implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable signal, while ensuring that data address signals meet setup hold time specifications relative write enable signal. contrast, EAB's synchronous generates write enable signal self-timed with respect input write clock. circuit using EAB's self-timed must only meet setup hold time specifications global clock. When used RAM, each configured following sizes: 1,024 2,048 Figure shows ACEX memory configurations.
Figure ACEX Memory Configurations
1,024
2,048
Larger blocks created combining multiple EABs. example, blocks combined form block, blocks combined form block. Figure shows examples multiple combination.
Figure Examples Combining ACEX EABs
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
necessary, EABs device cascaded form single block. EABs cascaded form blocks 2,048 words without impacting timing. MAX+PLUS software automatically combines EABs meet designer's specifications. EABs provide flexible options driving controlling clock signals. Different clocks clock enables used reading writing EAB. Registers independently inserted data input, output, write address, write enable signals, read address, read enable signals. global signals local interconnect drive write-enable, read-enable, clock-enable signals. global signals, dedicated clock pins, local interconnect drive clock signals. Because drive local interconnect, control write-enable, read-enable, clear, clock, clock-enable signals. interconnect drive column interconnects. Each output drive channels column channels; unused channel driven other LEs. This feature increases routing resources available outputs (see Figures column interconnect, which adjacent EAB, twice many channels other columns device.
Logic Array Block
consists eight LEs, their associated carry cascade chains, control signals, local interconnect. provides coarse-grained structure ACEX architecture, facilitating efficient routing with optimum device utilization high performance. Figure shows ACEX LAB.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX
Dedicated Inputs Global Signals
Interconnect
Local Interconnect
Carry-In Cascade-In
Figure details.
Control Signals
Column-to-Row Interconnect
Column Interconnect
Carry-Out Cascade-Out
Notes:
EP1K10, EP1K30, EP1K50 devices have inputs local interconnect channel from row; EP1K100 devices have EP1K10, EP1K30, EP1K50 devices have local interconnect channels; EP1K100 devices have
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Each provides four control signals with programmable inversion that used eight LEs. these signals used clocks, other used clear/preset control. clocks driven dedicated clock input pins, global signals, signals, internal signals local interconnect. preset clear control signals driven global signals, signals, internal signals local interconnect. global control signals typically used global clock, clear, preset signals because they provide asynchronous control with very skew across device. logic required control signal, generated more driven into local interconnect target LAB. addition, global control signals generated from outputs.
Logic Element
smallest unit logic ACEX architecture, compact size that provides efficient logic utilization. Each contains 4-input LUT, which function generator that quickly compute function four variables. addition, each contains programmable flipflop with synchronous clock enable, carry chain, cascade chain. Each drives both local FastTrack Interconnect routing structure. Figure shows ACEX
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX Logic Element
Carry-In Cascade-In
Register Bypass
Programmable Register
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
FastTrack Interconnect
CLRN Local Interconnect
labctrl1 labctrl2
Chip-Wide Reset
Clear/ Preset Logic
Clock Select
labctrl3 labctrl4
Carry-Out Cascade-Out
programmable flipflop configured operation. clock, clear, preset control signals flipflop driven global signals, general-purpose pins, internal logic. combinatorial functions, flipflop bypassed LUT's output drives LE's output. outputs that drive interconnect: drives local interconnect, other drives either column FastTrack Interconnect routing structure. outputs controlled independently. example, drive output while register drives other output. This feature, called register packing, improve utilization because register used unrelated functions. ACEX architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports highspeed counters adders, cascade chain implements wide-input functions with minimum delay. Carry cascade chains connect LABs same row. Intensive carry cascade chains reduce routing flexibility. Therefore, these chains should limited speed-critical portions design.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Carry Chain
carry chain provides very fast carry-forward function between LEs. carry-in signal from lower-order drives forward into higher-order carry chain, feeds into both next portion carry chain. This feature allows ACEX architecture efficiently implement high-speed counters, adders, comparators arbitrary width. Carry chain logic created automatically MAX+PLUS Compilers during design processing, manually designer during design entry. Parameterized functions, such DesignWare functions, automatically take advantage carry chains. Carry chains longer than eight automatically implemented linking LABs together. enhanced fitting, long carry chain skips alternate LABs row. carry chain longer than skips either from even-numbered even-numbered LAB, from oddnumbered odd-numbered LAB. example, last first carries first third row. carry chain does cross middle row. instance, EP1K50 device, carry chain stops eighteenth LAB, carry chain begins nineteenth LAB. Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output register bypassed simple adders used accumulator function. Another portion carry chain logic generates carry-out signal, which routed directly carry-in signal next-higher-order bit. final carry-out signal routed where used general-purpose signal.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX Carry Chain Operation (n-Bit Full Adder)
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Cascade Chain
With cascade chain, ACEX architecture implement functions that have very wide fan-in. Adjacent LUTs used compute portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical (via Morgan's inversion) connect outputs adjacent LEs. With delay each additional provides four more inputs effective width function. Cascade chain logic created automatically MAX+PLUS Compiler during design processing, manually designer during design entry. Cascade chains longer than eight bits implemented automatically linking several LABs together. easier routing, long cascade chain skips every other row. cascade chain longer than skips either from even-numbered even-numbered LAB, from odd-numbered odd-numbered (e.g., last first cascades first third LAB). cascade chain does cross center (e.g., EP1K50 device, cascade chain stops eighteenth LAB, begins nineteenth LAB). This break EAB's placement middle row. Figure shows cascade function connect adjacent form functions with wide fan-in. These examples show functions variables implemented with LEs. delay cascade chain delay With cascade chain, decoding 16-bit address requires
Figure ACEX Cascade Chain Operation
Cascade Chain Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n 1).(4n
d[(4n 1).(4n
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Operating Modes
ACEX operate following four modes:
Normal mode Arithmetic mode Up/down counter mode Clearable counter mode
Each these modes uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. Three inputs provide clock, clear, preset control register. MAX+PLUS software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions that specific operating mode optimal performance. architecture provides synchronous clock enable register four modes. MAX+PLUS software DATA1 enable register synchronously, providing easy implementation fully synchronous designs. Figure shows ACEX operating modes.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Figure ACEX Operating Modes
Normal Mode
Carry-In data1 data2 data3 4-Input LE-Out Local Interconnect Cascade-In LE-Out FastTrack Interconnect
CLRN data4 Cascade-Out
Arithmetic Mode
Carry-In Cascade-In LE-Out data1 data2
3-Input
3-Input Carry-Out Cascade-Out
CLRN
Up/Down Counter Mode
Carry-In Cascade-In
data1 (ena) data2 (u/d) data3 (data)
3-Input
LE-Out
3-Input data4 (nload) Carry-Out Cascade-Out
CLRN
Clearable Counter Mode
Carry-In
data1 (ena) data2 (nclr) data3 (data)
3-Input
LE-Out
3-Input data4 (nload) Carry-Out Cascade-Out
CLRN
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Normal Mode normal mode suitable general logic applications wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs 4-input LUT. MAX+PLUS Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. Either register used drive both local interconnect FastTrack Interconnect routing structure same time. register used independently (register packing). support register packing, outputs; drives local interconnect, other drives FastTrack Interconnect routing structure. DATA4 signal drive register directly, allowing compute function that independent registered signal; 3-input function computed LUT, fourth independent signal registered. Alternatively, 4-input function generated, inputs this function used drive register. register packed still clock enable, clear, preset signals packed register drive FastTrack Interconnect routing structure while drives local interconnect, vice versa. Arithmetic Mode arithmetic mode offers 3-input LUTs that ideal implementing adders, accumulators, comparators. computes 3-input function; other generates carry output. shown Figure first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, adder, this output three signals: carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. Up/Down Counter Mode up/down counter mode offers counter enable, clock enable, synchronous up/down control, data loading options. These control signals generated data inputs from local interconnect, carry-in signal, output feedback from programmable register. 3-input LUTs used; generates counter data, other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading. Data also loaded asynchronously with clear preset register control signals without using resources.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Clearable Counter Mode clearable counter mode similar up/down counter mode, supports synchronous clear instead up/down control. clear function substituted cascade-in signal up/down counter mode. 3-input LUTs used; generates counter data, other generates fast carry bit. Synchronous loading provided 2-to-1 multiplexer. output this multiplexer with synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without limitations physical tri-state bus. physical tri-state bus, tri-state buffers' output enable (OE) signals select which signal drives bus. However, multiple signals active, contending signals driven onto bus. Conversely, signals active, will float. Internal tri-state emulation resolves contending tri-state buffers value floating buses high value, thereby eliminating these problems. MAX+PLUS software automatically implements tri-state functionality with multiplexer.
Clear Preset Logic Control
Logic programmable register's clear preset functions controlled DATA3, LABCTRL1, LABCTRL2 inputs clear preset control structure asynchronously loads signals into register. Either LABCTRL1 LABCTRL2 control asynchronous clear. Alternatively, register that LABCTRL1 implements asynchronous load. data loaded driven DATA3; when LABCTRL1 asserted, DATA3 loaded into register. During compilation, MAX+PLUS Compiler automatically selects best control signal implementation. Because clear preset functions active-low, Compiler automatically assigns logic high unused clear preset. clear preset logic implemented following modes chosen during design entry:
Asynchronous clear Asynchronous preset Asynchronous clear preset Asynchronous load with clear Asynchronous load with preset Asynchronous load without clear preset
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
addition clear preset modes, ACEX devices provide chip-wide reset that reset registers device. this feature during design entry. clear preset modes, chip-wide reset overrides other signals. Registers with asynchronous presets preset when chip-wide reset asserted. Inversion used implement asynchronous preset. Figure shows examples setup preset clear inputs desired functionality.
Figure ACEX Clear Preset Modes
Asynchronous Clear
Chip-Wide Reset labctrl1 labctrl2 labctrl2 Chip-Wide Reset
Asynchronous Preset
Asynchronous Preset Clear
labctrl1
labctrl1 labctrl2 Chip-Wide Reset CLRN
CLRN
CLRN
Asynchronous Load with Clear
labctrl1 (Asynchronous Load) data3 (Data) labctrl2 (Clear) Chip-Wide Reset
Asynchronous Load without Clear Preset
labctrl1 (Asynchronous Load) data3 (Data)
CLRN
CLRN
Asynchronous Load with Preset
labctrl1 (Asynchronous Load) labctrl2 (Preset) data3 (Data) CLRN
Chip-Wide Reset
Chip-Wide Reset
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Asynchronous Clear flipflop cleared either LABCTRL1 LABCTRL2. this mode, preset signal tied deactivate Asynchronous Preset asynchronous preset implemented asynchronous load, with asynchronous clear. DATA3 tied VCC, asserting LABCTRL1 asynchronously loads into register. Alternatively, MAX+PLUS software provide preset control using clear inverting register's input output. Inversion control available inputs both IOEs. Therefore, register preset only LABCTRL signals, DATA3 input needed used operating modes. Asynchronous Preset Clear When implementing asynchronous clear preset, LABCTRL1 controls preset, LABCTRL2 controls clear. DATA3 tied VCC, that asserting LABCTRL1 asynchronously loads into register, effectively presetting register. Asserting LABCTRL2 clears register. Asynchronous Load with Clear When implementing asynchronous load conjunction with clear, LABCTRL1 implements asynchronous load DATA3 controlling register preset clear. LABCTRL2 implements clear controlling register clear; LABCTRL2 does have feed preset circuits. Asynchronous Load with Preset When implementing asynchronous load conjunction with preset, MAX+PLUS software provides preset control using clear inverting input output register. Asserting LABCTRL2 presets register, while asserting LABCTRL1 loads register. MAX+PLUS software inverts signal that drives DATA3 account inversion register's output. Asynchronous Load without Preset Clear When implementing asynchronous load without preset clear, LABCTRL1 implements asynchronous load DATA3 controlling register preset clear.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
FastTrack Interconnect Routing Structure
ACEX architecture, connections between LEs, EABs, device pins provided FastTrack Interconnect routing structure, which series continuous horizontal vertical routing channels that traverse device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance. FastTrack Interconnect routing structure consists column interconnect channels that span entire device. Each LABs served dedicated interconnect. interconnect drive pins feed other LABs row. column interconnect routes signals between rows drive pins. channels drive into local interconnect. signal buffered every reduce effect fan-out delay. channel driven three column channels. These four signals feed dual 4-to-1 multiplexers that connect specific channels. These multiplexers, which connected each allow column channels drive channels even when eight drive interconnect. Each column LABs EABs served dedicated column interconnect. column interconnect that serves EABs twice many channels other column interconnects. column interconnect then drive pins another row's interconnect route signals other LABs EABs device. signal from column interconnect, which either output input from pin, must routed interconnect before enter EAB. Each channel that driven drive specific column channel. Access column channels switched between adjacent pairs LABs. example, drive column channels normally driven particular adjacent same row, vice versa. This flexibility enables routing resources used more efficiently. Figure shows ACEX LAB.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Figure ACEX Connections Column Interconnect
Column Channels
Channels
Other Columns
each intersection, channels drive column channels.
Each drive channels.
From Adjacent Adjacent
Each switch interconnect access with adjacent LAB.
Local Interconnect
Other Rows
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
improved routing, interconnect consists combination full-length half-length channels. full-length channels connect LABs row; half-length channels connect LABs half row. driven half-length channels left half full-length channels. drives fulllength channels. addition providing predictable, row-wide interconnect, this architecture provides increased routing resources. neighboring LABs connected using half-row channel, thereby saving other half channel other half row. Table summarizes FastTrack Interconnect routing structure resources available each ACEX device.
Table ACEX FastTrack Interconnect Resources
Device
EP1K10 EP1K30 EP1K50 EP1K100
Rows
Channels
Columns
Channels Column
addition general-purpose pins, ACEX devices have dedicated input pins that provide low-skew signal distribution across device. These inputs used global clock, clear, preset, peripheral output-enable clock-enable control signals. These signals available control signals LABs IOEs device. dedicated inputs also used general-purpose data inputs because they feed local interconnect each device. Figure shows interconnection adjacent LABs EABs, with row, column, local interconnects, well associated cascade carry chains. Each labeled according location: letter represents number represents column. example, column
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Figure ACEX Interconnect Resources
Figure details. Element (IOE)
Interconnect
Figure details.
Column Interconnect
Cascade Carry Chains
Element
contains bidirectional buffer register that used either input register external data that requires fast setup time output register data that requires fast clock-to-output performance. some cases, using register input register will result faster setup time than using register. IOEs used input, output, bidirectional pins. MAX+PLUS Compiler uses programmable inversion option invert signals from column interconnect automatically where appropriate. Figure shows block diagram.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX Bidirectional Registers
Column Interconnect
Dedicated Clock Inputs
Dedicated Inputs
Peripheral Control
Register
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
Programmable Delay
Output Register
CLK[1.0] CLK[3.2] ENA[5.0] CLRN[1.0] CLRN
Open-Drain Output Slew-Rate Control
Chip-Wide Reset Input Register
CLRN
Chip-Wide Reset
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
ACEX devices, input path from FastTrack Interconnect programmable delay element that used guarantee zero hold time. Depending placement relative what driving, designer choose turn programmable delay ensure zero hold time turn minimize setup time. This feature used reduce setup time complex pin-toregister paths (e.g., designs). Each selects clock, clear, clock enable, output enable controls from network control signals called peripheral control bus. peripheral control uses high-speed drivers minimize signal skew across devices provides peripheral control signals that allocated follows:
eight output enable signals clock enable signals clock signals clear signals
more than clock-enable eight output-enable signals required, each device controlled clock enable output enable signals driven specific LEs. addition clock signals available peripheral control bus, each dedicated clock pins. Each peripheral control signal driven dedicated input pins first each particular row. addition, different drive column interconnect, which causes interconnect drive peripheral control signal. chipwide reset signal resets registers, overriding other control signals. When dedicated clock drives registers, inverted IOEs device. IOEs must same sense clock. example, uses inverted clock, IOEs must inverted clock, non-inverted clock. However, still true complement clock LAB-by-LAB basis. incoming signal inverted dedicated clock will drive IOEs. true complement clock used drive IOEs, drive into both global clock pins. global clock will supply true, other will supply complement. When true complement dedicated input drives clocks, signals peripheral control consumed, each sense clock.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
When dedicated inputs drive non-inverted inverted peripheral clears, clock enables, output enables, signals peripheral control will used. Table lists sources each peripheral control signal shows output enable, clock enable, clock, clear signals share peripheral control signals. Table also shows rows that drive global signals.
Table Peripheral Sources ACEX Devices
Peripheral Control Signal
CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3
EP1K10
EP1K30
EP1K50
EP1K100
Signals peripheral control also drive four global signals, referred GLOBAL0 through GLOBAL3. internally generated signal drive global signal, providing same low-skew, low-delay characteristics signal driven input pin. drives global signal driving line that drives peripheral which then drives global signal. This feature ideal internally generated clear clock signals with high fan-out. However, internally driven global signals offer advantage over general-purpose interconnect routing data signals. chip-wide output enable active-low that used tri-state pins device. This option MAX+PLUS software. built-in pull-up resistors (which active during configuration) active when chip-wide output enable asserted. registers also reset chip-wide reset pin.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Row-to-IOE Connections
When used input signal, drive separate channels. signal accessible within that row. When used output, signal driven multiplexer that selects signal from channels. eight IOEs connect each side each channel (see Figure 16).
Figure ACEX Row-to-IOE Connections
Note
IOE1
FastTrack Interconnect
IOE8
Each driven m-to-1 multiplexer. Each drive channels.
Note:
values shown Table
Table lists ACEX row-to-IOE interconnect resources.
Table ACEX Row-to-IOE Interconnect Resources
Device
EP1K10 EP1K30 EP1K50 EP1K100
Channels
Channels
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Column-to-IOE Connections
When used input, drive separate column channels. When used output, signal driven multiplexer that selects signal from column channels. IOEs connect each side column channels. Each driven column channels multiplexer. column channels different each (see Figure 17).
Figure ACEX Column-to-IOE Connections
Each driven m-to-1 multiplexer
IOE1
Column Interconnect
IOE1
Each drive column channels.
Note:
values shown Table
Table lists ACEX column-to-IOE interconnect resources.
Table ACEX Column-to-IOE Interconnect Resources
Device
EP1K10 EP1K30 EP1K50 EP1K100
Channels Column
Column Channels
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
SameFrame Pin-Outs
ACEX devices support SameFrame pin-out feature FineLine packages. SameFrame pin-out feature arrangement balls FineLine packages such that lower-ballcount packages form subset higher-ball-count packages. SameFrame pin-outs provide flexibility migrate only from device device within same package, also from package another. given printed circuit board (PCB) layout support multiple device density/package combinations. example, single board layout support range devices from EP1K10 device 256-pin FineLine package EP1K100 device 484-pin FineLine package. MAX+PLUS software provides support design PCBs with SameFrame pin-out devices. Devices defined present future use. MAX+PLUS software generates pin-outs describing board that takes advantage this migration. Figure shows example SameFrame pin-out.
Figure SameFrame Pin-Out Example
Printed Circuit Board Designed 484-Pin FineLine Package
256-Pin FineLine
484-Pin FineLine
256-Pin FineLine Package (Reduced Count Logic Requirements)
484-Pin FineLine Package (Increased Count Logic Requirements)
Table shows ACEX device/package combinations that support SameFrame pin-outs ACEX devices. FineLine packages support SameFrame pin-outs, providing flexibility migrate only from device device within same package, also from package another. count will vary from device device.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
more information, search "SameFrame" MAX+PLUS Help.
Table ACEX SameFrame Pin-Out Support
Device 256-Pin FineLine
484-Pin FineLine
EP1K10 EP1K30 EP1K50 EP1K100 Note:
This option supported with 256-pin FineLine package SameFrame migration.
ClockLock ClockBoost Features
support high-speed designs, speed grade ACEX devices offer ClockLock ClockBoost circuitry containing phase-locked loop (PLL) that used increase design speed reduce resource usage. ClockLock circuitry uses synchronizing that reduces clock delay skew within device. This reduction minimizes clock-tooutput setup times while maintaining zero hold times. ClockBoost circuitry, which provides clock multiplier, allows designer enhance device area efficiency sharing resources within device. ClockBoost feature allows designer distribute lowspeed clock multiply that clock on-device. Combined, ClockLock ClockBoost features provide significant improvements system performance bandwidth. ClockLock ClockBoost features ACEX devices enabled through MAX+PLUS software. External devices required these features. output ClockLock ClockBoost circuits available device pins. ClockLock ClockBoost circuitry lock onto rising edge incoming clock. circuit output drive clock inputs registers only; generated clock cannot gated inverted. dedicated clock (GCLK1) supplies clock ClockLock ClockBoost circuitry. When dedicated clock driving ClockLock ClockBoost circuitry, cannot drive elsewhere device.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
designs that require both multiplied non-multiplied clock, clock trace board connected GCLK1 pin. MAX+PLUS software, GCLK1 feed both ClockLock ClockBoost circuitry ACEX device. However, when both circuits used, other clock cannot used.
ClockLock ClockBoost Timing Parameters
ClockLock ClockBoost circuitry function properly, incoming clock must meet certain requirements. these specifications met, circuitry lock onto incoming clock, which generates erroneous clock within device. clock generated ClockLock ClockBoost circuitry must also meet certain specifications. incoming clock meets these requirements during configuration, ClockLock ClockBoost circuitry will lock onto clock during configuration. circuit will ready immediately after configuration. Figure shows incoming generated clock specifications.
Figure Specifications Incoming Generated Clocks
CLK1 INDUTY
Note
CLKDEV
Input Clock
OUTDUTY
INCLKSTB
ClockLock Generated Clock JITTER JITTER
Note:
parameter refers nominal input clock period; parameter refers nominal output clock period.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Tables summarize ClockLock ClockBoost parameters speed-grade devices, respectively.
Table ClockLock ClockBoost Parameters Speed-Grade Devices
Symbol
tINDUTY fCLK1 fCLK2 fCLKDEV
Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input deviation from user specification MAX+PLUS software (ClockBoost clock multiplication factor equals
Parameter
Condition
25,000
Unit
tINCLKSTB Input clock stability (measured between adjacent clocks) tLOCK tJITTER
Time required ClockLock ClockBoost acquire lock Jitter ClockLock ClockBoostgenerated clock
tINCLKSTB <100 tINCLKSTB
tOUTDUTY Duty cycle ClockLock ClockBoostgenerated clock
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table ClockLock ClockBoost Parameters Speed-Grade Devices
Symbol
tINDUTY fCLK1 fCLK2 fCLKDEV
Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input deviation from user specification MAX+PLUS software (ClockBoost clock multiplication factor equals
Parameter
Condition
37.5 25,000
Unit
tINCLKSTB Input clock stability (measured between adjacent clocks) tLOCK tJITTER
Time required ClockLock ClockBoost acquire lock Jitter ClockLock ClockBoostgenerated clock
tINCLKSTB tINCLKSTB
tOUTDUTY Duty cycle ClockLock ClockBoostgenerated clock
Notes tables:
implement ClockLock ClockBoost circuitry with MAX+PLUS software, designers must specify input frequency. MAX+PLUS software tunes ClockLock ClockBoost circuitry this frequency. fCLKDEV parameter specifies much incoming clock differ from specified frequency during device operation. Simulation does reflect this parameter. Twenty-five thousand parts million (PPM) equates 2.5% input clock period. During device configuration, ClockLock ClockBoost circuitry configured before rest device. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration because tLOCK value less than time required configuration. tJITTER specification measured under long-term observation. maximum value tJITTER tINCLKSTB lower than
Configuration
This section discusses pull-up clamping diode option, slew-rate control, open-drain output option, MultiVolt interface ACEX devices. pull-up clamping diode, slew-rate control, open-drain output options controlled pin-by-pin MAX+PLUS logic options. MultiVolt interface controlled connecting VCCIO different voltage than VCCINT. effect simulated MAX+PLUS software Global Project Device Options dialog (Assign menu).
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Pull-Up Clamping Diode Option
ACEX devices have pull-up clamping diode every I/O, dedicated input, dedicated clock pin. clamping diodes clamp signal VCCIO value required 3.3-V compliance. Clamping diodes also used limit overshoot other systems. Clamping diodes controlled pin-by-pin basis. When VCCIO that clamping diode option turned driven 2.5-V 3.3-V signal, 5.0-V signal. When VCCIO that clamping diode option turned driven 2.5-V signal, 3.3-V 5.0-V signal. Additionally, clamping diode activated subset pins, which allows device bridge between 3.3-V 5.0-V device.
Slew-Rate Control
output buffer each adjustable output slew rate that configured low-noise high-speed performance. slower slew rate reduces system noise adds maximum delay fast slew rate should used speed-critical outputs systems that adequately protected against noise. Designers specify slew rate pin-by-pin assign default slew rate pins device-wide basis. slow slew rate setting affects only falling edge output.
Open-Drain Output Option
ACEX devices provide optional open-drain output (electrically equivalent open-collector output) each pin. This open-drain output enables device provide system-level control signals (e.g., interrupt write enable signals) that asserted several devices. also provide additional wired-OR plane.
MultiVolt Interface
ACEX device architecture supports MultiVolt interface feature, which allows ACEX devices packages interface with systems differing supply voltages. These devices have pins internal operation input buffers (VCCINT), another output drivers (VCCIO).
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
VCCINT pins must always connected 2.5-V power supply. With 2.5-V VCCINT level, input voltages compatible with 2.5-V, 3.3-V, 5.0-V inputs. VCCIO pins connected either 2.5-V 3.3-V power supply, depending output requirements. When VCCIO pins connected 2.5-V power supply, output levels compatible with 2.5-V systems. When VCCIO pins connected 3.3-V power supply, output high therefore compatible with 3.3-V 5.0-V systems. Devices operating with VCCIO levels higher than achieve faster timing delay tOD2 instead tOD1. Table summarizes ACEX MultiVolt support.
Table ACEX MultiVolt Support
VCCIO
Notes:
clamping diode must disabled drive input with voltages higher than VCCIO has. When VCCIO ACEX device drive 2.5-V device that 3.3-V tolerant inputs.
Input Signal
Output Signal
Open-drain output pins ACEX devices (with pull-up resistor 5.0-V supply) drive 5.0-V CMOS input pins that require When open-drain active, will drive low. When inactive, resistor will pull trace open-drain will only drive tri-state; will never drive high. rise time dependent value pull-up resistor load impedance. current specification should considered when selecting pull-up resistor.
Power Sequencing Hot-Socketing
Because ACEX devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. VCCIO VCCINT power planes powered order. Signals driven into ACEX devices before during power without damaging device. Additionally, ACEX devices drive during power Once operating conditions reached, ACEX devices operate specified user.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
ACEX devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. ACEX devices also configured using JTAG pins through ByteBlasterMV BitBlaster download cable, hardware that uses JamStandard Test Programming Language (STAPL), JEDEC standard JESD-71. JTAG boundary-scan testing performed before after configuration, during configuration. ACEX devices support JTAG instructions shown Table
Table ACEX JTAG Instructions
JTAG Instruction
SAMPLE/PRELOAD
Description
Allows snapshot signals device pins captured examined during normal device operation permits initial data pattern output device pins. Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, allowing data pass synchronously through selected device adjacent devices during normal operation. Selects user electronic signature (USERCODE) register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. These instructions used when configuring ACEX device JTAG ports using ByteBlasterMV BitBlaster download cable, File (.jam) Byte-Code File (.jbc) embedded processor.
EXTEST BYPASS
USERCODE IDCODE Instructions
instruction register length ACEX devices bits. USERCODE register length ACEX devices bits; bits determined user, bits pre-determined. Tables show boundary-scan register length device IDCODE information ACEX devices.
Table ACEX Boundary-Scan Register Length
Device
EP1K10 EP1K30 EP1K50 EP1K100
Boundary-Scan Register Length
1,050
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Preliminary Information
ACEX Programmable Logic Family
Table 32-Bit IDCODE ACEX Devices
Device Version Bits)
EP1K10 EP1K30 EP1K50 EP1K100 Notes tables:
Note
IDCODE Bits)
Part Number Bits)
0001 0000 0011 0000 0001 0000 0101 0000 0000 0001 0000 0000
Manufacturer's Identity Bits)
00001101110 00001101110 00001101110
Bit)
0001 0001 0010
Contact Altera Applications. most significant (MSB) left. least significant (LSB) JTAG IDCODEs
ACEX devices include weak pull-up resistors JTAG pins.
more information, following documents:
Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet Programming Test Language Specification
Figure shows timing requirements JTAG signals.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows timing parameters values ACEX devices.
Table ACEX JTAG Timing Parameters Values
Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
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Preliminary Information
ACEX Programmable Logic Family
Generic Testing
Each ACEX device functionally tested. Complete testing each configurable static random access memory (SRAM) logic functionality ensures 100% yield. test measurements ACEX devices made under conditions equivalent those shown Figure Multiple test patterns used configure devices during stages production flow.
Figure ACEX Test Conditions
Power supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast-groundcurrent transients normally occur device outputs discharge load capacitances. When these transients flow through parasitic inductance between device ground test system ground, significant reductions observable noise immunity result. Numbers brackets 2.5-V devices outputs. Numbers without brackets 3.3-V devices outputs.
VCCIO [481 Device Output Test System
8.06 [481 Device input rise fall times
(includes capacitance)
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 2.5-V ACEX devices.
Table ACEX Device Absolute Maximum Ratings
Symbol
VCCINT VCCIO IOUT TSTG TAMB input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias
Note
-0.5 -0.5 -2.0
Parameter
Supply voltage
Conditions
With respect ground
5.75
Unit
PQFP, TQFP, packages, under bias
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table ACEX Device Recommended Operating Conditions
Symbol
VCCINT VCCIO
Parameter
Supply voltage internal logic input buffers
Conditions
(3),
2.375 (2.375) 3.00 (3.00) 2.375 (2.375) -0.5
2.625 (2.625) 3.60 (3.60) 2.625 (2.625) 5.75 VCCIO
Unit
Supply voltage output buffers, (3), 3.3-V operation Supply voltage output buffers, (3), 2.5-V operation
Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time
(2),
commercial industrial commercial industrial
Table ACEX Device Operating Conditions (Part
Symbol
Notes (6),
5.75 0.8, VCCIO
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level output voltage
Conditions
Unit
1.7, VCCIO -0.5 VCCIO 3.00 VCCIO VCCIO
3.3-V high-level CMOS output -0.1 VCCIO 3.00 voltage 3.3-V high-level output -0.5 VCCIO 3.00 3.60 voltage 2.5-V high-level output voltage -0.1 VCCIO 2.375 VCCIO 2.375 VCCIO 2.375
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table ACEX Device Operating Conditions (Part
Symbol
Notes (6),
0.45 VCCIO
Parameter
3.3-V low-level output voltage 3.3-V low-level CMOS output voltage 3.3-V low-level output voltage
Conditions
VCCIO 3.00 (10) VCCIO 3.00 (10) VCCIO 3.00 3.60 (10)
Unit
2.5-V low-level output voltage VCCIO 2.375 (10) VCCIO 2.375 (10) VCCIO 2.375 (10) ICC0 Input leakage current Tri-stated leakage current supply current (standby) -0.3 -0.3 ground, load, toggling inputs ground, load, toggling inputs (11) RCONF Value pull-up resistor before during configuration VCCIO (12) VCCIO 2.375 (12)
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table ACEX Device Capacitance
Symbol
CINCLK COUT
Note (13)
Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
Notes tables:
Operating Requirements Altera Devices Data Sheet. Minimum input voltage -0.5 During transitions, inputs undershoot -2.0 input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values VCCINT VCCIO These values specified under ACEX Recommended Operating Conditions shown Table page ACEX input buffers compatible with 2.5-V, 3.3-V (LVTTL LVCMOS), 5.0-V CMOS signals. Additionally, input buffers 3.3-V compliant when VCCIO VCCINT meet relationship shown Figure parameter refers high-level TTL, PCI, CMOS output current. parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. This parameter applies speed grade commercial temperature devices speed grade industrial temperature devices. pull-up resistance values will lower driven higher than VCCIO external source. Capacitance sample-tested only.
(10) (11) (12) (13)
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Figure shows required relationship between VCCIO VCCINT satisfy 3.3-V compliance.
Figure Relationship between VCCIO VCCINT 3.3-V Compliance
CCINT
PCI-Compliant Region
VCCIO
Figure shows typical output drive characteristics ACEX devices with 3.3-V 2.5-V VCCIO. output driver compliant 3.3-V Local Specification, Revision (when VCCIO pins connected ACEX devices with speed grade also comply with drive strength requirements Local Specification, Revision (when VCCINT pins powered with minimum supply 2.375 VCCIO pins connected Therefore, these devices used open 5.0-V systems.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure Output Drive Characteristics ACEX Devices
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Output Voltage
Output Voltage
Timing Model
continuous, high-performance FastTrack Interconnect routing resources ensure accurate simulation timing analysis well predictable performance. This predictable performance contrasts with that FPGAs, which segmented connection scheme and, therefore, have unpredictable performance. Device performance estimated following signal path from source, through interconnect, destination. example, registered performance between same calculated adding following parameters:
register clock-to-output delay (tCO) Interconnect delay (tSAMEROW) look-up table delay (tLUT) register setup time (tSU)
routing delay depends placement source destination LEs. more complex registered path involve multiple combinatorial between source destination LEs. Timing simulation delay prediction available with MAX+PLUS Simulator Timing Analyzer, with industrystandard tools. Simulator offers both pre-synthesis functional simulation evaluate logic design accuracy post-synthesis timing simulation with 0.1-ns resolution. Timing Analyzer provides pointto-point timing delay information, setup hold time analysis, device-wide performance analysis.
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Preliminary Information
ACEX Programmable Logic Family
Figure shows overall timing model, which maps possible paths from various elements ACEX device.
Figure ACEX Device Timing Model
Dedicated Clock/Input Interconnect Element
Logic Element
Embedded Array Block
Figures through show delays that correspond various paths functions within IOE, EAB, bidirectional timing models.
Figure ACEX Device Timing Model
Carry-In Cascade-In
Delay Data-In
Register Delays
tLUT tRLUT tCLUT
Packed Register Delay tPACKED Register Control Delay
tCOMB tPRE tCLR
Data-Out
Control-In
Carry Chain Delay tCGENR
tCGEN tCICO tLABCARRY
tCASC
tLABCASC
Carry-Out
Cascade-Out
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX Device Timing Model
Output Data Delay Data-In Register Delays Output Delays
tIOD
Element Contol Delay Clock Enable Clear Clock Output Enable
tIOCO tIOCOMB tIOSU tIOH tIOCLR
tIOC tINREG
Input Register Delay Register Feedback Delay
tOD1 tOD2 tOD3 tZX1 tZX2 tZX3
Data Feedback into FastTrack Interconnect
tIOFD
Input Delay
tINCOMB
Figure ACEX Device Timing Model
Data Input Delays Data-In Address Input Register Delays RAM/ROM Block Delays Output Register Delays Output Delay
tEABDATA1 tEABDATA2
Write Enable Input Delays
tEABWE1 tEABWE2
Clock Delay
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
Input Register Clock Output Register Clock
tWDSU tWDH tWASU tWAH tRASU tRAH
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
tEABOUT
Data-Out
tEABCLK
Read Enable Input Delays
tEABRE1 tEABRE2
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Preliminary Information
ACEX Programmable Logic Family
Figure Synchronous Bidirectional External Timing Model
Register
Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
CLRN Output Register Bidirectional
CLRN
tINSUBIDIR tINHBIDIR
Input Register
CLRN
Tables through describe ACEX device internal timing parameters.
Table Timing Microparameters
Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
delay data-in delay carry-in
Note
Parameter Conditions
delay register feedback Data-in packed register delay register enable delay Carry-in carry-out delay Data-in carry-out delay register feedback carry-out delay Cascade-in cascade-out delay register control signal delay register clock-to-output delay Combinatorial delay register setup time data enable signals before clock; register recovery time after asynchronous clear, preset, load register hold time data enable signals after clock register preset delay register clear delay Minimum clock high time from clock Minimum clock time from clock
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Preliminary Information
Table Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
data delay
Note
Parameter Conditions
register control signal delay register clock-to-output delay combinatorial delay register setup time data enable signals before clock; register recovery time after asynchronous clear register hold time data enable signals after clock register clear time Output buffer delay, slow slew rate off, VCCIO VCCINT Output buffer delay, slow slew rate off, VCCIO voltage Output buffer delay, slow slew rate output buffer disable delay output buffer enable delay, slow slew rate off, VCCIO VCCINT output buffer enable delay, slow slew rate off, VCCIO voltage output buffer enable delay, slow slew rate input buffer register delay register feedback delay input buffer FastTrack Interconnect delay
Table Timing Microparameters (Part
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tEABCH tEABCL
Note
Conditions
Parameter
Data address delay combinatorial input Data address delay registered input Write enable delay combinatorial input Write enable delay registered input Read enable delay combinatorial input Read enable delay registered input register clock delay register clock-to-output delay Bypass register delay register setup time before clock register hold time after clock register asynchronous clear time output delay Clock high time Clock time Address access delay (including read enable output delay)
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Preliminary Information
ACEX Programmable Logic Family
Table Timing Microparameters (Part
Symbol
tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT
Write pulse width Read pulse width
Note
Conditions
Parameter
Data setup time before falling edge write pulse Data hold time after falling edge write pulse Address setup time before rising edge write pulse Address hold time after falling edge write pulse Address setup time before rising edge read pulse Address hold time after falling edge read pulse Write enable data output valid delay Data-in data-out valid delay Data-out delay
Table Timing Macroparameters
Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWESH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
address access delay
Notes (1),
Parameter Conditions
asynchronous read cycle time synchronous read cycle time write pulse width asynchronous write cycle time synchronous write cycle time data-in data-out valid delay clock-to-output delay when using output registers data/address setup time before clock when using input register data/address hold time after clock when using input register setup time before clock when using input register hold time after clock when using input register data setup time before falling edge write pulse when using input registers data hold time after falling edge write pulse when using input registers address setup time before rising edge write pulse when using input registers address hold time after falling edge write pulse when using input registers write enable data output valid delay
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ACEX Programmable Logic Family
Preliminary Information
Table Interconnect Timing Microparameters
Symbol
tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC tDIN2IOE tDIN2LE tDCLK2IOE tDCLK2LE tDIN2DATA
Notes tables:
Note
Conditions
Parameter
Routing delay driving another same Routing delay IOE, driving IOE, same Routing delay driving same column
Routing delay column IOE, driving different Routing delay driving different Routing delay driving control signal peripheral control Routing delay carry-out signal driving carry-in signal different different Routing delay cascade-out signal driving cascade-in signal different different Delay from dedicated input control input Delay from dedicated input control input Delay from dedicated clock clock Delay from dedicated clock clock Delay from dedicated input clock data
Microparameters timing delays contributed individual architectural elements. These parameters cannot measured explicitly. Operating conditions: VCCIO commercial industrial ACEX devices Operating conditions: VCCIO 0.125 commercial industrial ACEX devices. Operating conditions: VCCIO Because self-timed, this parameter ignored when signal registered. macroparameters internal parameters that simplify predicting behavior boundary; these parameters calculated summing selected microparameters. These parameters worst-case values typical applications. Post-compilation timing simulation timing analysis required determine actual worst-case performance.
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ACEX Programmable Logic Family
Tables through describe ACEX external timing parameters their symbols.
Table External Reference Timing Parameters
Symbol
tDRR
Note
Conditions
Parameter
Register-to-register delay four LEs, three interconnects, four local interconnects
Table External Timing Parameters
Symbol
tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Parameter
Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock register Setup time with global clock registers used designs Hold time with global clock registers used designs Clock-to-output delay with global clock registers used designs
Conditions
(3), (3), (3),
Table External Bidirectional Timing Parameters
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Note
Conditions
Parameter
Setup time bidirectional pins with global clock same-row samecolumn register Hold time bidirectional pins with global clock same-row same-column register Clock-to-output delay bidirectional pins with global clock register Synchronous output buffer disable delay Synchronous output buffer enable delay, slow slew rate
External reference timing parameters factory-tested, worst-case values specified Altera. representative subset signal paths tested approximate typical device applications. Contact Altera Applications test circuit specifications test conditions. These timing parameters sample-tested only. This parameter measured with measurement test conditions, including load, specified Local Specification, Revision 2.2.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Tables through show EP1K10 device internal external timing parameters. timing specifications EP1K10 preliminary.
Table EP1K10 Device Timing Microparameters
Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB tPRE tCLR
Note
Unit
Speed Grade
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K10 Device Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note
Unit
Speed Grade
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K10 Device Internal Microparameters
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note
Unit
Speed Grade
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K10 Device Internal Timing Macroparameters
Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note
Unit
Speed Grade
10.2 10.6
10.2
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K10 Device Interconnect Timing Microparameters
Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note
Unit
Speed Grade
Table EP1K10 External Timing Parameters
Symbol
tDRR tINSU (2), tINH (2), tOUTCO (2), tINSU (3), tINH (3), tOUTCO (3), tPCISU tPCIH tPCICO
Note
Speed Grade
Unit
12.5 10.2
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K10 External Bidirectional Timing Parameters
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tOUTCOBIDIR tXZBIDIR(3) tZXBIDIR Notes tables:
Notes (1),
Unit
Speed Grade
timing parameters described Tables through this data sheet. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits. These parameters specified characterization.
Tables through show internal external timing parameters EP1K30 devices.
Table EP1K30 Device Timing Microparameters (Part
Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB
Altera Corporation
Note
Unit
Speed Grade
ACEX Programmable Logic Family
Preliminary Information
Table EP1K30 Device Timing Microparameters (Part
Symbol
tPRE tCLR
Note
Unit
Speed Grade
Table EP1K30 Device Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note
Unit
Speed Grade
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K30 Device Internal Microparameters
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note
Unit
Speed Grade
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K30 Device Internal Timing Macroparameters
Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note
Unit
Speed Grade
10.2 10.6
10.2
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K30 Device Interconnect Timing Microparameters
Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note
Unit
Speed Grade
Table EP1K30 External Timing Parameters
Symbol
tDRR tINSU (2), tINH (2), tOUTCO (2), tINSU (2), tINH (2), tOUTCO (2), tPCISU tPCIH tPCICO
Note
Speed Grade
Unit
12.5 10.2
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K30 External Bidirectional Timing Parameters
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Notes (1),
Unit
Speed Grade
timing parameters described Tables through this data sheet. These parameters specified characterization. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Tables through show EP1K50 device internal external timing parameters.
Table EP1K50 Device Timing Microparameters (Part
Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB
Note
Unit
Speed Grade
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K50 Device Timing Microparameters (Part
Symbol
tPRE tCLR
Note
Unit
Speed Grade
Table EP1K50 Device Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note
Unit
Speed Grade
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K50 Device Internal Microparameters
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note
Unit
Speed Grade
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K50 Device Internal Timing Macroparameters
Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note
Unit
Speed Grade
10.2 10.6
10.2
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K50 Device Interconnect Timing Microparameters
Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note
Unit
Speed Grade
Table EP1K50 External Timing Parameters
Symbol
tDRR tINSU (2), tINH (2), tOUTCO (2), tINSU (2), tINH (2), tOUTCO (2), tPCISU tPCIH tPCICO
Note
Speed Grade
Unit
12.5 10.5
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K50 External Bidirectional Timing Parameters
Symbol
tINSUBDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Note tables:
Notes (1),
Unit
Speed Grade
timing parameters described Tables through this data sheet. These parameters specified characterization. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Tables through show EP1K100 device internal external timing parameters.
Table EP1K100 Device Timing Microparameters (Part
Symbol
tLUT tCLUT tRLUT tPACKED tCICO tCGEN tCGENR tCASC tCOMB
Altera Corporation
Note
Unit
Speed Grade
ACEX Programmable Logic Family
Preliminary Information
Table EP1K100 Device Timing Microparameters (Part
Symbol
tPRE tCLR
Note
Unit
Speed Grade
Table EP1K100 Device Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note
Unit
Speed Grade
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K100 Device Internal Microparameters
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABRE1 tEABRE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCLR tWDSU tWDH tWASU tWAH tRASU tRAH tEABOUT tEABCH tEABCL
Note
Unit
Speed Grade
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K100 Device Internal Timing Macroparameters
Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note
Unit
Speed Grade
10.2 10.6
10.2
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table EP1K100 Device Interconnect Timing Microparameters
Symbol
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note
Unit
Speed Grade
Table EP1K100 External Timing Parameters
Symbol
tDRR tINSU (2), tINH (2), tOUTCO (2), tINSU (2), tINH (2), tOUTCO (2), tPCISU tPCIH tPCICO
Note
Unit
12.0
Speed Grade
16.0
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table EP1K100 External Bidirectional Timing Parameters
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
Notes (1),
Unit
Speed Grade
timing parameters described Tables through this data sheet. These parameters specified characterization. This parameter measured without ClockLock ClockBoost circuits. This parameter measured with ClockLock ClockBoost circuits.
Power Consumption
supply power ACEX devices calculated with following equation: PINT (ICCSTANDBY ICCACTIVE) ICCACTIVE value depends switching frequency application logic. This value calculated based amount current that each typically consumes. value, which depends device output load characteristics switching frequency, calculated using guidelines given Application Note (Evaluating Power Altera Devices). Compared rest device, embedded array consumes negligible amount power. Therefore, embedded array ignored when calculating supply current.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
ICCACTIVE value calculated with following equation: ICCACTIVE fMAX togLC Where: fMAX togLC Maximum operating frequency Total number used device Average percent toggling each clock (typically 12.5%) Constant
Table provides constant values ACEX devices.
Table ACEX Constant Values
Device
EP1K10 EP1K30 EP1K50 EP1K100
Value
This supply power calculation provides estimate based typical conditions with output load. actual should verified during operation because this measurement sensitive actual pattern device environmental operating conditions. better reflect actual designs, power model (and constant power calculation equations) continuous interconnect ACEX devices assumes that drive FastTrack Interconnect channels. contrast, power model segmented FPGAs assumes that drive only short interconnect segment. This assumption lead inaccurate results when compared measured power consumption actual designs segmented FPGAs. Figure shows relationship between current operating frequency ACEX devices. information other ACEX devices, contact Altera Applications (800) 800-EPLD.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Figure ACEX ICCACTIVE Operating Frequency
EP1K30
EP1K50
Supply
Supply
Current (mA)
Current (mA)
Frequency (MHz)
Frequency (MHz)
EP1K100
Supply
Current (mA)
Frequency (MHz)
Configuration Operation
ACEX architecture supports several configuration schemes. This section summarizes device operating modes available device configuration schemes.
Operating Modes
ACEX architecture uses SRAM configuration elements that require configuration data loaded every time circuit powers process physically loading SRAM data into device called configuration. Before configuration, rises, device initiates Power-On Reset (POR). This event clears device prepares configuration. ACEX time does exceed however, when configuring with configuration device, configuration device imposes 200-ms delay that allows system power stabilize before configuration.
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
During initialization, which occurs immediately after configuration, device resets registers, enables pins, begins operate logic device. pins tri-stated during power-up, before during configuration. Together, configuration initialization processes called command mode; normal device operation called user mode. SRAM configuration elements allow ACEX devices reconfigured in-circuit loading configuration data into device. Real-time reconfiguration performed forcing device into command mode with device pin, loading different configuration data, re-initializing device, resuming user-mode operation. entire reconfiguration process requires less than used reconfigure entire system dynamically. In-field upgrades performed distributing configuration files. Before during configuration, pins (except dedicated inputs, clock, configuration pins) pulled high weak pull-up resistor.
Configuration Schemes
configuration data ACEX device loaded with five configuration schemes (see Table 59), chosen basis target application. EPC2, EPC1, EPC1441 configuration device, intelligent controller, JTAG port used control configuration ACEX device, allowing automatic configuration system power-up. Multiple ACEX devices configured five configuration schemes connecting configuration enable (nCE) configuration enable output (nCEO) pins each device. Additional APEX 20K, APEX 20KE, FLEX 10K, FLEX 10KA, FLEX 10KE, ACEX FLEX 6000 devices configured same serial chain.
Table Data Sources ACEX Configuration
Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG
Data Source
EPC1, EPC2, EPC1441 configuration device BitBlaster, ByteBlaster, ByteBlasterMV download cables, serial data source Parallel data source Parallel data source BitBlaster ByteBlasterMV download cables, microprocessor with File File
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Device PinOuts
Tables through describe device pin-outs.
Table ACEX Device Pin-Outs (Part
Name
Note
208-Pin PQFP EP1K30 EP1K50 EP1K100
182,
144-Pin TQFP EP1K30 EP1K50
MSEL0 MSEL1 nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBUSY CLKUSR DATA7 DATA6(4) DATA5 DATA4 DATA3 DATA2 DATA1(4) DATA0 (2), TMS(2) TRST Dedicated Inputs Dedicated Clock Pins GCLK1
124,
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table ACEX Device Pin-Outs (Part
Name
Note
208-Pin PQFP EP1K30 EP1K50 EP1K100
106, 124, 130, 152, 185, 110, 118, 138, 146, 165, 178, 109. 117, 123, 129, 137, 145, 151, 171, 181,
144-Pin TQFP EP1K30 EP1K50
103, 115, 104, 123, 129,
LOCK(8) DEV_CLRn(3) DEV_OE VCCINT (2.5 VCCIO (2.5 VCC_CKLK GNDINT
GND_CKLK Total User Pins (10)
Table ACEX Device Pin-Outs (Part
Name
Note
256-Pin FineLine EP1K50 EP1K100
256-Pin FineLine EP1K30
MSEL0 MSEL1 nSTATUS(2) nCONFIG DCLK(2) CONF_DONE(2) INIT_DONE(3) nCEO RDYnBSY CLKUSR
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table ACEX Device Pin-Outs (Part
Name
Note
256-Pin FineLine EP1K50 EP1K100
256-Pin FineLine EP1K30
DATA7 DATA6(4) DATA5 DATA4(4) DATA3 DATA2 DATA1 DATA0 (2), TRST Dedicated Inputs Dedicated Clock Pins GCLK1 LOCK(8) DEV_CLRn DEV_OE VCCINT (2.5 VCCIO (2.5 VCC_CKLK(9)
E11, F12, H10, E11, F12, H10, J10, J11, L12, M11, J10, J11, L12, M11, D12, F10, G11, H11, K11, L10, D12, F10, G11, H11, K11, L10,
A14, E12, F11, A14, E12, F11, G10, K10, G10, K10, L11, L11, E16, H16, K14, K16, M14, M16,
GND_CKLK(9) Connect (N.C.)
Total User Pins (10)
Altera Corporation
Preliminary Information
ACEX Programmable Logic Family
Table ACEX Device Pin-Outs (Part
Name 484-Pin FineLine EP1K50
E12, H11, R12, D12, E12, H11, R12, D12,
484-Pin FineLine EP1K100
MSEL0(2) MSEL1 nSTATUS nCONFIG DCLK CONF_DONE(2) INIT_DONE nCEO nRS(4) RDYnBSY(4) CLKUSR DATA7 DATA6 DATA5(4) DATA4 DATA3 DATA2 DATA1 DATA0 (2), TRST(2) Dedicated Inputs Dedicated Clock Pins GCLK1 LOCK(8) DEV_CLRn DEV_OE
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Table ACEX Device Pin-Outs (Part
Name 484-Pin FineLine EP1K50
C11, C15, H14, J10, J12, J15, L10, L13, M10, M13, M14, N12, P10, P15, R14, W21, AA12 A13, G15, H20, J11, J13, K11, K14, K20, L14, N11, N14, N20, P13, T15, T22, V22, AB13 A22, B17, B21, B22, C21, D17, E21, F10, G21, H15, J14, J20, K10, K12, K13, L11, L12, M11, M12, M20, N10, N13, P14, R15, R22, W20, Y21, Y22, AA1, AA6, AA22, AB11, AB16 A11, A12, A14, A15, A20, A21, B10, B12, B16, B19, B20, C10, C12, C13, C14, C16, C17, C22, D20, D21, E20, E22, F20, F21, G20, G22, J21, K22, L20, L22, M22, N21, N22, P20, P21, P22, R21, T20, T21, U20, U21, U22, V20, W22, Y12, Y13, Y16, Y19, Y20, AA2, AA3, AA4, AA9, AA11, AA13, AA15, AA21, AB1, AB2, AB3, AB4, AB5, AB7, AB8, AB9, AB12, AB15, AB17, AB18, AB19, AB20, AB21, AB22
484-Pin FineLine EP1K100
C11, C15, H14, J10, J12, J15, L10, L13, M10, M13, M14, N12, P10, P15, R14, W21, AA12 A13, G15, H20, J11, J13, K11, K14, K20, L14, N11, N14, N20, P13, T15, T22, V22, AB13 A22, B17, B21, B22, C21, D17, E21, F10, G21, H15, J14, J20, K10, K12, K13, L11, L12, M11, M12, M20, N10, N13, P14, R15, R22, W20, Y21, Y22, AA1, AA6, AA22, AB11, AB16 B10, C17, P20, P22, T20, T21, W22, Y16, AA15, AB3, AB4, AB5, AB7, AB15, AB17, AB18, AB19, AB20
VCCINT (2.5 VCCIO (2.5
VCC_CKLK
GND_CKLK Connect (N.C.)
Total User Pins (10)
Altera Corporation
Preliminary Information Notes tables:
ACEX Programmable Logic Family
pins that listed user pins. This dedicated pin; available user pin. This used user used device-wide configuration function. This used user after configuration. This tri-stated user mode. optional JTAG TRST used 144-pin TQFP package. This drives ClockLock ClockBoost circuitry. This shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK goes periodic clock stops clocking. LOCK optional; LOCK output used, this user pin. This power ground ClockLock ClockBoost circuitry PLL. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. used, this power ground should connected VCCINT GNDINT, respectively. (10) user count includes dedicated input pins, dedicated clock pins, pins.
Revision History
information contained ACEX Programmable Logic Family Data Sheet version 1.01 supersedes information published previous versions. Version 1.01 contains addition Tables and62. These tables describe device pin-outs.
Altera Corporation
ACEX Programmable Logic Family
Preliminary Information
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
Altera, ACEX, ACEX APEX, APEX 20K, APEX 20KE, BitBlaster, ByteBlaster, ByteBlasterMV, ClockBoost, ClockLock, EP1K10, EP1K30, EP1K50, EP1K100, FineLine BGA, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, Jam, MasterBlaster, MAX, MAX+PLUS, MAX+PLUS MegaCore, MultiVolt, SameFrame trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
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Altera Corporation

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