BiMOS DUAL 8-BIT LATCHED DRIVER WITH READ BACK With CMOS data lat

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BiMOS DUAL 8-BIT LATCHED DRIVER WITH READ BACK With CMOS data lat

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5881 BiMOS DUAL 8-BIT LATCHED DRIVER
BiMOS DUAL 8-BIT LATCHED DRIVER WITH READ BACK
With CMOS data latches (two sets eight), CMOS control circuitry each latches, bipolar saturated driver each latch, UCN5881EP provides low-power interface with maximum flexibility. driver includes thermal shutdown circuitry protect against damage from high junction temperatures clamp diodes inductive load transient suppression. CMOS inputs cause minimal circuit loading compatible with standard CMOS, PMOS, NMOS circuits. circuits require appropriate pull resistors. When reading back, each data input will sink corresponding latch low) source corresponding latch high). read back feature error checking. allows system verify that data been received latched. bipolar outputs suitable with low-power relays, solenoids, stepping motors. very-low output saturation voltage makes this device well-suited driving arrays. output transistors capable sinking will maintain least state. Outputs paralleled higher current capability.
Data Sheet 26180.16
ABSOLUTE MAXIMUM RATINGS
Output Voltage, VOUT Output Sustaining Voltage, VCE(sus) Output Current, IOUT Input Voltage Range, -0.3 Logic Supply Voltage, Package Power Dissipation, Graph Operating Temperature Range, +85°C Storage Temperature Range, -55°C +150°C
Caution: CMOS devices have input static protection, susceptible damage when exposed extremely high static electrical charges.
Dwg. A-14,225
UCN5881EP dual 8-bit latched sink driver rated operation over temperature range -20°C +85°C supplied plastic 44-lead chip carrier conforming JEDEC MS-007AB outline.
FEATURES
Minimum Data-Input Rate Low-Power CMOS Logic (Max.) Outputs Transient-Protected Outputs Thermal Shutdown Protection Low-Profile Leaded Chip Carrier
Always order complete part number:
UCN5881EP
5881 BiMOS DUAL 8-BIT LATCHED DRIVER
FUNCTIONAL BLOCK DIAGRAM
Channels)
Dwg. A-14,227
TRUTH TABLE
ALLOWABLE PACKAGE POWER DISSIPATION WATTS
Read/ln Strobe Clear
Output Enable
Latch Read/Write Contents
Output
46°C/W
Present Latch Contents Previous Latch Contents Irrelevant
AMBIENT TEMPERATURE
Dwg. GP-025-1A
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 1985, 1995, Allegro MicroSystems, Inc.
5881 BiMOS DUAL 8-BIT LATCHED DRIVER
ELECTRICAL CHARACTERISTICS 25°C, (unless otherwise noted).
Characteristic Output Leakage Current Output Saturation Voltage Symbol ICEX VCE(SAT) Test Conditions VOUT IOUT IOUT Output Sustaining Voltage Input Voltage VCE(sus) VIN(0) VIN(1) Input Current IIN(0) IIN(1) Readback Output Voltage VOUT(1) VOUT(0) Logic Supply Current IOUT -400 IOUT Drivers Drivers Clamp Diode Leakage Current Clamp Diode Forward Voltage IOUT Min. -0.3 Limits Max. Units
Dwg. A-14,228
high READ/WRITE input allows circuit accept data Information then present input transferred latch when STROBE high. high CLEAR input will latches output condition regardless data STROBE input levels. high OUTPUT ENABLE will outputs condition regardless other input conditions. When OUTPUT ENABLE low, outputs depend state their respective latches. READ/WRITE input will allow latched data read back data input lines. Allow minimum delay (will increase with capacitive loading) before reading back state latches. read back feature error checking applications allows system verify that data been received latched.
TIMING CONDITIONS
(VDD Logic Levels Ground)
Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time) Minimum Data Active Time After Strobe Disabled (Data Hold Time) Minimum Strobe Pulse Width Typical Time Between Strobe Activation Output Transition Typical Time Between Strobe Activation Output Transition Minimum Clear Pulse Width Minimum Data Pulse Width
5881 BiMOS DUAL 8-BIT LATCHED DRIVER
Dimensions Inches (controlling dimensions)
0.319 0.291 0.021 0.013 0.695 0.685 0.656 0.650 0.319 0.291 0.050
INDEX AREA
0.032 0.026
0.020
0.656 0.650 0.695 0.685
Dwg. MA-005-44A
0.180 0.165
Dimensions Millimeters (for reference only)
8.10 7.39 0.533 0.331 17.65 17.40 16.662 16.510
INDEX AREA
0.812 0.661
8.10 7.39 1.27
0.51
4.57 4.20
16.662 16.510 17.65 17.40
Dwg. MA-005-44A
NOTES: Exact body lead configuration vendor's option within limits shown. Lead spacing tolerance non-cumulative.
Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements design products. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringements patents other rights third parties which result from use.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

BiMOS DUAL 8-BIT LATCHED DRIVER WITH READ BACK With CMOS data lat

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