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L64724 Satellite Receiver
Orner Number I14030
This document contains proprietary information Logic Corporation. information contained herein used disclosed third parties without express written permission officer Logic Corporation. Document DB14-000032-03, April 2000 This document describes release Logic Corporation's L64724 Satellite Receiver will remain official reference source revisions/releases this product until rescinded update. receive product literature, visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 2000 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design registered trademarks Logic Corporation. other brand product names trademarks their respective companies.
Contents
Chapter
Introduction General Description Typical Application Features Summary L64724 Signal Definitions Channel Interface Channel Clock Interface Phase-Locked Loop (PLL) Interface Control Signals Interface AGC/Clock Control Interface Channel Data Output Interface Analog-to-Digital Converter (ADC) Interface Microcontroller Interfaceea L64724 Registers L64724 Register Overview Reset Affects Registers Groups Address Pointer Register Group System Mode System Status Registers Group Status Registers Group Configuration Registers Group Self-Tuning Microcontroller Registers Group Reserved (Internal Only) Group Arbiter Control Register 3.10 Reset Effect Register Bits 3.11 Internal Data Path Reset Effects
Chapter
Chapter
3-23 3-33 3-77 3-81 3-81 3-82 3-84
Contents
Chapter
Channel Interfaces Data Control Data Control Clocking Schemes Clock Generation Data Path Input Interface Data Output Interface Demodulator Module Functional Description Overview Analog Digital Conversion Offset Compensation Coupling Output Decimation Filters Matched Filter Timing Clock Recovery Carrier Recovery Loop Automatic Gain Control (AGC) Output Control 5.10 External Controls Decoding Pipeline Synchronization Synchronization Scheme Viterbi Decoder Synchronization Reed-Solomon Deinterleaver Synchronization Descrambler Synchronization Decoder Pipeline Viterbi Decoder Module Deinterleaver Module Reed-Solomon Decoder Descrambler Module Architecture Operation Module Software Reset L64724 Specifications Electrical Requirements Timing L64724 Packaging
4-12 4-14
Chapter
5-12 5-20 5-22 5-23
Chapter
6-13
Chapter
7-10 7-15 7-17
Chapter
8-15
Contents
Appendix
Programming L64724 Using Serial Protocol Serial Protocol Overview Programming Slave Address Using Serial Interface Write Cycle Using Serial Interface Read Cycle Using Serial Interface L64724 Application Notes L64724 QPSK Demodulator Acquisition Debugging Tips Demodulator Configuration Tips QPSK Demodulator Configuration Example: High Data Rates QPSK Demodulator Configuration Example: Data Rates Programming Serializer Serializer Overview Serializer Interface Signals Configuration Registers Programming Serial Mode (2-Wire Compliant) Programming 3-Wire Mode Converters Overview Board Level Interface Characteristics Characteristics L64724 On-chip Microcontroller L64724 Microcontroller Instruction Microcontroller Address Customer Feedback
Appendix
B-10 B-30
Appendix
Appendix
Appendix
Contents
Figures 5.10 6.10 L64724 Block Diagram Set-Top Decoder Block Diagram L64724 Logic Symbol Register File Structure Issue Hard Reset Initialize APR0 APR1 Zero Write Locations Group Read Back Group L64724 Clocking: Internal Clock Synthesis L64724 Functional Blocks Decoding Pipeline Analog Inputs Channel Data Input Digital Inputs Bypass Mode Parallel Output Interface Waveforms Descrambler Parallel Output Waveforms Descrambler Serial Output Waveforms Demodulator Module Associated Circuitry Input Quantization Clock Recovery Loop Timing Loop Sweep Operation Carrier Recovery Loop Frequency Sweeping Threshold Es/No Carrier Loop Filter Parameters Pattern Range Loop Control Synchronization Module Viterbi Decoder Synchronization Phase Rotation Synchronization Channel Symbol Error Rate Rate Channel Symbol Error Rate Rate Channel Symbol Error Rate Rate Channel Symbol Error Rate Rate Channel Symbol Error Rate Rate Channel Symbol Error Rate Rate Reed-Solomon, Deinterleaver Synchronization 4-12 4-13 4-13 4-15 4-16 4-17 5-11 5-12 5-13 5-17 5-17 5-20 5-22
Code Code Code Code Code Code
Contents
6.11 6.12 6.13 6.14 6.15 6.16 6.17 7.10 7.11 7.12
Synchronization, Tracking, Loss Sync Three Missed Sync Words Minimum Maximum Number States Acquisition Phase Minimum Maximum Number States Tracking Phase Packet MPEG-2 Transport Packet L64724 Transport Packet Descrambler Synchronization Viterbi Decoder Block Diagram Puncturing Depuncturing Block Diagram Puncture Pattern Different Code Rates Block Diagram Viterbi Error Detection Circuit Interleaving/Deinterleaving Operation Interleaving/Deinterleaving Operation Code Word Structure Data Path 122-Bit Burst Example Descrambler Block Diagram 15-Bit Shift Register Initialization Inverted Sync Words Descrambler Test Load Waveform Standard Outputs Test Load Waveforms 3-State Outputs L64724 Synchronous Timing L64724 RESET Timing Diagram L64724 3-State Delay Timing L64724 Decoder Read Cycle L64724 Decoder Write Cycle 100-Pin PQFP/MQFP Pinout 100-Pin PQFP/MQFP Mechanical Drawing 100-Pin PQFP/MQFP Mechanical Drawing (Cont.) Serial Architecture 7-Bit Slave Address L64724 Serial Serial Write/Read Cycle Overview General Call Structure Burst Write Single Write Slave (Master-Transmitter, Slave-Receiver)
6-10 6-11 6-12 6-12 6-12 6-13 7-12 7-12 7-14 7-16 7-16 7-17 8-16 8-17 8-18
Contents
Tables
viii
Burst Read Single Read Cycle from Slave Loop Control 2-Wire Compliant Interface 3-Wire Interface 28-Bit Write Using 3-Wire Mode Connections L64724 Board Level Interface Registers Shared Between Host L64724
Register Overview Group System Mode Register (Write-Only) Group System Status Register (Read-Only) Group Register Group Register Group Register Reset Parameters Crystal Clock (CLK) Parameters Crystal Clock (CLK) Input Configuration Output Selection Decimation Procedure Decimation Results Roll-Off Factor Gain Carrier Loop PWR_BW Function Symbol Rate Puncture Patterns Various Code Rates L64724 Absolute Maximum Rating (Referenced VSS) L64724 Recommended Operating Conditions L64724 Capacitance Characteristics L64724 L64724 Description Summary L64724-75 Timing Parameters with Microcontroller Disabled L64724-75 Timing Parameters with Microcontroller Enabled L64724-90 Timing Parameters with Microcontroller Disabled L64724-90 Timing Parameters with Microcontroller Enabled
3-10 3-17 3-23 3-34 3-77 3-83 4-13 4-14 5-19 5-21 8-11 8-12 8-14
Contents
8.10 B.10 B.11 B.12 B.13 B.14
L64724 Ordering Information PWR_LVL Register Setting Decimation Procedure Decimation Results Carrier Loop Control Register Bits Clock Loop Configuration Register Bits Demodulator Configuration Register Bits External Output Control Bits Reset Register Bits High Data Rate Register Values Carrier Loop Configuration Register Bits Clock Loop Configuration Register Bits Demodulator Configuration Register Bits External Output Control Bits Reset Register Bits Group Register Bits Data Rate Register Values Characteristics Characteristics L64724 Instruction Microcontroller Address
8-15 B-19 B-22 B-23 B-23 B-26 B-38 B-42 B-43 B-43 B-44 B-45
Contents
Contents
Preface
This manual primary reference technical manual L64724 Satellite Receiver. contains complete functional description L64724 includes complete physical electrical specifications.
Audience This document assumes that have some familiarity with digital satellite communications, microprocessors, related support devices. people benefit from this book are:
Engineers managers evaluating L64724 possible digital satellite receiver Engineers designing L64724 into digital satellite receiver
Organization This document following chapters appendices:
Chapter Introduction, defines general characteristics capabilities L64724 Satellite Receiver. Chapter L64724 Signal Definitions, describes characteristics L64724 signals that used interface with external channel microcontroller. Chapter L64724 Registers, provides summary registers L64724. Chapter Channel Interfaces Data Control, discusses Input Channel Output Channel interfaces circuitry that supports them.
Preface
Chapter Demodulator Module Functional Description, describes operation Demodulator portion Satellite Receiver. Chapter Decoding Pipeline Synchronization, discusses mechanism synchronizing internal decoder modules incoming data stream. Chapter Decoder Pipeline, describes various logic modules that comprise decoding pipeline. Chapter L64724 Specifications, describes electrical mechanical characteristics L64724. Appendix Programming L64724 Using Serial Protocol, provides information program L64724 using Serial protocol. Appendix L64724 Application Notes, provides application information connecting L64724 your circuit programming meet your needs. Appendix Programming Serializer, discusses programming Serializer module. Appendix Converters, discusses Analog-to-Digital Converters used L64724 device. Appendix L64724 On-chip Microcontroller, summarizes features L64724 on-chip microcontroller.
Related Publications
European Digital Video Broadcast Standard, DTVB 1110 Revision This document available from:
Project Office European Broadcasting Union Ancienne Route, Grand Saconnex Geneva, Switzerland Logic L64002 MPEG-2 Audio/Video Decoder Technical Manual, Document DB14-000004-00. Order I14011 Logic L64007 MPEG-2, TSAT Transport Demultiplexer Technical Manual, Document DB14-000007-00.
Preface
Conventions Used This Manual first time word phrase defined this manual, italicized. word assert means drive signal true active. word deassert means drive signal false inactive. Hexadecimal numbers indicated prefix "0x" before number-for example, 0x32CF. Binary numbers indicated prefix "0b" before number-for example, 0b0011. Operations registers referred using binary numbers Output signal levels referred designations HIGH LOW. Example: XCTR0 register force XCTR_OUT0 HIGH.
Preface
xiii
Preface
Chapter Introduction
This chapter introduces L64724 Satellite Receiver from Logic. L64724 designed specifically meet needs satellite broadcast digital compliant with European digital video broadcast (DVB-S) standard technical specifications systems. sections this chapter are:
Section 1.1, "General Description" Section 1.2, "Typical Application" Section 1.3, "Features Summary"
General Description
L64724 Satellite Receiver contains main blocks: BPSK/QPSK Demodulator Concatenated Decoder. BPSK/QPSK module performs binary quadrature phase-shift keying (BPSK/QPSK) demodulation, method extracting digital signal from phase-modulated analog signal. Concatenated Decoder complete concatenated Forward Error Correction decoder that uses Viterbi inner code ReedSolomon outer code. decoding pipeline also contains necessary synchronization, deinterleaving, scrambling functions complete decoding solution. Logic fabricates L64724 using 3.3-volt HCMOS process technology. L64724 provides maximum integration flexibility system designers minimum cost. contains on-chip dual 6-bit analog-todigital converter (ADC) well on-chip microcontroller. microcontroller controls tuner well acquisition tracking,
L64724 Satellite Receiver
which eliminates interaction from main CPU, freeing perform other functions. number external components required build system minimal because both clock carrier loops incorporated into device. Figure block diagram L64724. Figure L64724 Block Diagram
Control Carrier Loop Control Channel Input from Satellite Microcontroller Data Address External Microcontroller Interface Internal Microcontroller Interface Dual Interpolator/Decimation Filter Timing Loop Control
BPSK/QPSK Demodulator
DEMI Matched Filter Output Control DEMQ
Microcontroller Data Address
Channel Output (MPEG-2 Transport Stream)
Descrambler
ReedSolomon Decoder
Convolutional Deinterleaver
ReedSolomon Syncronizer
Viterbi Decoder
Decoder Pipeline
Viterbi Synchronizer
Introduction
Typical Application
typical application L64724 satellite digital reception accordance with 1110 Rev. standard. Figure shows L64724 satellite receiver implemented typical satellite receiver settop decoder box. Also shown other Logic products:
L64008 MPEG-2 Transport Demultiplexer L64005 MPEG-2 Audio/Video Decoder
Typical Application
Figure Set-Top Decoder Block Diagram
Optional DRAM DRAM 256K (required)
[7:0]
Satellite TUNER L64724
L64008 Transport Demux
High-Speed Port
Serial Control
Microcontroller Data Address
VCXO
Audio Oversampling Clock
NTSC S-Video L-Speaker R-Speaker
NTSC Encoder
CCIR601VIDEO
L64005 Audio/Video Decoder
Audio/Video
Audio
AUDIO
SDRAM
Introduction
Features Summary
This section summarizes main features L64724. Subsequent chapters describe these features more detail.
On-chip self-tuning microcontroller acquisition tracking, eliminating microprocessor interaction, simplifying software development. Supports system specifications. BPSK/QPSK demodulation rates from Mbaud. Matched filter (square root raised cosine filter with roll-off factor 35%). Antialiasing filters operation from MBaud without switching external filters need low-pass filters. On-chip digital clock synchronization. On-chip digital carrier synchronization, featuring frequency sweep capability signal acquisition. Auto-acquisition demodulator mode tuner control through on-chip microcontroller. Integrated phase-locked loop (PLL) clock synthesis, allowing fundamental mode crystal. Dual ADC. Fast channel switching mode. Power estimation control. Programmable Viterbi decoder module following rates: 1/2, 2/3, 3/4, 5/6, 6/7, 7/8. (204/188), (146/130) Reed-Solomon decoder. Auto-synchronization Viterbi decoder. Programmable synchronization deinterleaver, Reed-Solomon decoder, descrambler. error monitoring channel performance measurements. Deinterleaver (DVB DSS).
Features Summary
Serial host interface compatible with Logic Serial Control interface. Power-down mode.
Introduction
Chapter L64724 Signal Definitions
This chapter describes L64724 signals divided into following sections:
Section 2.1, "Channel Interface" Section 2.2, "Channel Clock Interface" Section 2.3, "Phase-Locked Loop (PLL) Interface" Section 2.4, "Control Signals Interface" Section 2.5, "AGC/Clock Control Interface" Section 2.6, "Channel Data Output Interface" Section 2.7, "Analog-to-Digital Converter (ADC) Interface" Section 2.8, "Microcontroller Interface"
Figure shows logic symbol L64724.
L64724 Satellite Receiver
Figure
L64724 Logic Symbol
IVIN BCLKOUT CO[7:0] COEn DVALIDOUT ERROROUTn Channel Data Output Interface
Channel Interface
QVIN IBYPASS[5:0] QBYPASS[5:0]
Channel Clock Interface
XOIN XOOUT
FSTARTOUT
IBIAS QBIAS LCLK PCLK Interface PLLAGND PLLVDD PLLVSS A[2:0] IDDTN Control Signals Interface RESET XCTR_IN XCTR_OUT[3:0] D[7:0] DTACKn/WAIT DTACK/POL HOST_MODE AGC/Clock Control Interface PWRP INTn READ/WRITE Microcontroller Interface ADCVSSI/Q ADCVDDI/Q ADCVREFI/Q ADCVREFNI/Q Interface
shown Figure 2.1, L64724 following major interfaces:
Channel Channel Clock
L64724 Signal Definitions
Control Signals AGC/Clock Control Channel Data Output Microcontroller
following signal descriptions listed according major interface groups.
Channel Interface
Channel interface input path L64724 satellite receiver. signals IVIN QVIN streams from satellite tuner circuit. signal strobes data signals. IBYPASS[5:0] Channel Data Input IBYPASS[5:0] signals form Digital Received Channel data input bus, which supplies Stream L64724 when bypassed. IVIN Channel Data Input IVIN signal Analog Received Channel data input bus, which supplies Stream L64724.
QBYPASS[5:0] Channel Data Input QBYPASS[5:0] signals form Digital Received Channel data input bus, which supplies Stream L64724 when bypassed. QVIN Channel Data Input QVIN signal Analog Received Channel data input bus, which supplies Stream L64724.
Channel Interface
Channel Clock Interface
Channel Clock interface consists clock crystal oscillator signals. IVIN/QVIN Input Clock Input positive, edge-triggered clock that strobes input data L64724. Crystal Oscillator Input XOIN used crystal oscillator external reference clock input. Crystal Oscillator Output XOOUT crystal oscillator output pin.
XOIN
XOOUT
Phase-Locked Loop (PLL) Interface
circuitry multiplies external clock signal times symbol rate, based Viterbi code rate. LCLK Decimated Clock Output Output L64724 internal clock generation module generates LCLK signal. LCLK derived from dividing value CLK_DIV2 parameter (Group 23). Input Input signal input internal voltagecontrolled oscillator. normally connected output external timing circuit. Clock Output Output L64724 internal clock synthesis module generates PCLK signal. signal drives PLL. clock synthesis module configured generate PCLK rate that appropriate data rates. Analog Ground Input PLLAGND analog ground module normally connected system ground plane.
PCLK
PLLAGND
L64724 Signal Definitions
PLLVDD
Power Input PLLVDD power supply module normally connected system power (VDD) plane. Ground Input PLLVSS ground module normally connected system ground plane.
PLLVSS
Control Signals Interface
Control Signals Interface controls operation L64724 associated with particular interface. IDDTN Test Input IDDTN Logic internal test pin. IDDTN normal operation. Reset Input RESET active-HIGH signal that, when asserted, resets internal data paths. RESET signal resets Group Group registers some Group register bits. Group registers unaffected. RESET timing asynchronous device clocks. RESET signal performs same operation reset bits specified Group register. PCLK must running RESET take effect. Control Input Input XCTR_IN external input control pin. sensed reading XCTR_IN (D6) Group register.
RESET
XCTR_IN
XCTR_OUT[3] Control Output/Sync Status Flag Output XCTR_OUT[3] indicates synchronization status three synchronization modules L64724. modules Viterbi Decoder, ReedSolomon Deinterleaver (DI/RS), Descrambler. three synchronization outputs, XCTR_OUT[3] signal, when asserted, indicates that synchronization been achieved sync module chosen using SSS[1:0] bits (Group APR16). When deasserted, signal indicates out-of-synchronization condition.
Control Signals Interface
XCTR_OUT[2:0] Control Output Output XCTR_OUT[2:0] pins external output control pins. They programming corresponding bits Group register. XCTR_OUT[1] function Serial Clock (SCLK) signal, XCTR_OUT[0] function Serial Data (SDATA) signal.
AGC/Clock Control Interface
PWRP Power Control Output PWRP signal positive modulated output used power control drive external passive filter that feeds tuner gain control stage.
Channel Data Output Interface
Channel Data Output Interface output path from L64724. typically connected input transport demultiplexer set-top decoder application. BCLKOUT Byte Clock Output BCLKOUT output signal strobe that indicates valid data bytes CO[7:0] when L64724 Parallel Channel Output mode. BCLKOUT signal cycles once every valid output data byte used transport demultiplexer latch output data from L64724 BCLKOUT rate. BCLKOUT signal must disregarded Serial Channel Output mode. Channel Data Output CO[7:0] signals form decoded output data port. When (Group APR17), L64724 operates Parallel Channel Output mode. this mode, L64724 outputs channel data 8-bit wide parallel data CO[7:0] signals. Serial Channel Output mode L64724 outputs channel data serial data CO[0]. data latched every clock cycle. chronological ordering Serial Channel output mode oldest, newest.
CO[7:0]
L64724 Signal Definitions
COEn
Channel Output Enable Input When asserted, COEn signal enables ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, FSTARTOUT pins. Operation receiver continues regardless state COEn signal. Valid Data Output DVALIDOUT signal indicates that CO[7:0] signals contain corrected channel data. data valid CO[7:0] signals when DVALIDOUT signal asserted. DVALIDOUT asserted during propagated check bytes. DVALIDOUT signal deasserted after FEC_RST register (Group
DVALIDOUT
ERROROUTn Error Detection Flag Output L64724 asserts ERROROUTn (LOW) flag uncorrectable errors. L64724 asserts ERROROUTn signal beginning frame that contains uncorrectable error, deasserts frame error condition removed. ERROROUTn signal exactly aligned with output data stream asserted after FEC_RST register (Group Errorout_Invert (Group 31), when changes active state ERROROUTn signal from active-LOW active-HIGH. FSTARTOUT Frame Start Output Output L64724 asserts FSTARTOUT signal during first every frame with valid data Serial Channel Output mode during first byte Parallel Channel Output mode. FSTARTOUT valid only when DVALIDOUT signal asserted. FSTARTOUT signal deasserted after FEC_RST register (Group
Analog-to-Digital Converter (ADC) Interface
module converts incoming IVIN QVIN signals into internal 6-bit digital representation processing. following pins support module.
Analog-to-Digital Converter (ADC) Interface
ADCVDDI/Q
Power Input ADCVDDI/Q analog power supply pins module normally connected system power (VDD) plane. Reference Input This supplies internal reference generator. Negative Reference Input This supplies VREFN internal cells. Reference Input This used should left unconnected. other connection will cause unpredictable unreliable operation device. Negative Reference Input This supplies ground internal cell. Analog Ground Input ADCVSSI/Q analog ground pins module normally connected system ground plane. Current Bias Input IBIAS supplies current bias ADCs. Current Bias Input This used Logic internal purposes, should connected shown Figure D.2. other connection will cause unpredictable unreliable operation device.
ADCVREFI ADCVREFNI ADCVREFQ
ADCREFNQ ADCVSSI/Q
IBIAS QBIAS
Microcontroller Interface
Microcontroller Interface connects L64724 microcontroller such 64008. A[2:0] Address Input A[2:0] signals form receiver address bus. address used conjunction with 8-bit data D[7:0], read/write strobe (READ/WRITE), chip select strobe (CS), address strobe (AS) select, read, write internal registers.
L64724 Signal Definitions
Address Strobe Input signal active-LOW address strobe input. L64724 latches address A[2:0] signals falling edge signal. Chip Select Input signal active-LOW chip select strobe input. During read cycle, microcontroller must assert (LOW) access on-chip data registers. microcontroller must latch data from L64724 rising edge CSn. During write cycle, must asserted prior data being valid from microcontroller L64724. After data minimum setup time, microcontroller deasserts (HIGH) strobe data. There minimum write time allow internal synchronization. Setup hold times measured with respect falling edge CSn. Data Bidirectional D[7:0] signals form bidirectional data bus, which input data when data written L64724 chip data output when L64724 chip read Parallel Host Interface mode1 (HOST_MODE HIGH). data lines 3-stated when being read written. When Serial Host Interface mode selected (HOST_MODE LOW), D[0] used Serial Clock (SCLK) signal synchronize transfer serial data Serial Data (SDATA) pin. Serial Host interface mode, XCTR_OUT[1] functions SDATA, D[1] used SDATA signal transfer serial data, D[3:2] used LSBs L64724 slave address. Data Acknowledge/Wait Polarity Input DTACK/POL signal determines polarity Data Acknowledge/Wait Signal. When DTACK/POL signal LOW, DTACKn/WAIT active-LOW. When DTACK/POL signal HIGH, DTACKn/WAIT signal active-HIGH.
D[7:0]
DTACK/POL
Serial Mode recommended interface mode. Logic does recommend parallel mode designs.
Microcontroller Interface
DTACKn/WAIT Data Acknowledge/Wait Output DTACKn/WAIT signal output indicating that transaction D[7:0] been completed. active-LOW when DTACK/POL active-HIGH when DTACK/POL HIGH. base chip programming this signal. HOST_MODE Serial Parallel Host Interface Select Input When HOST_MODE signal deasserted, selects Serial Host Interface mode. When asserted, selects Parallel Host Interface mode1. INTn Interrupt Output L64724 asserts INTn signal (LOW) when internal unmasked interrupt flag set. INTn signal remains asserted long interrupt condition persists interrupt flag masked.
READ/WRITE Read/Write Strobe Input microcontroller asserts READ/WRITE signal (HIGH) indicate that current transaction read from L64724, deasserts (LOW) indicate that write L64724.
Serial Mode recommended interface mode. Logic does recommend parallel mode designs.
2-10
L64724 Signal Definitions
Chapter L64724 Registers
This chapter discusses L64724 internal registers. also provides description internal memory mapping describes access registers from system interface. This chapter intended primarily system programmers developing software drivers contains following sections:
Section 3.1, "L64724 Register Overview" Section 3.2, "Reset Affects Registers" Section 3.3, "Groups Address Pointer Register" Section 3.4, "Group System Mode System Status Registers" Section 3.5, "Group Status Registers" Section 3.6, "Group Configuration Registers" Section 3.7, "Group Self-Tuning Microcontroller Registers" Section 3.8, "Group Reserved (Internal Only)" Section 3.9, "Group Arbiter Control Register" Section 3.10, "Reset Effect Register Bits" Section 3.11, "Internal Data Path Reset Effects"
This chapter provides complete information these registers, does provide information program registers specific application. Appendix "L64724 Application Notes," some programming examples.
L64724 Register Overview
L64724 registers memory resources divided into eight groups, Group through Group
L64724 Satellite Receiver
Groups contain Address Pointer Register. This pointer used address registers Groups Group addresses System Mode Register when written System Status Register when read. Group contains Status Registers. Group contains Configuration Registers. Group contains program space on-board microprocessor. Group reserved internal only. Group used Arbiter control.
Table shows complete Register L64724 Satellite Receiver. Table
Group
Register Overview
Name APR0 APR1 SMR/STS STATUS CONFIG MICRO RESERVED ARBITER Function Address Pointer Register, Address Pointer Register, System Mode/System Status Registers Status Registers Configuration Registers Microcontrol Registers Reserved Arbiter Control Register Page 3-23 3-33 3-77 3-81 3-81
Figure shows simplified diagram L64724 register groups.
L64724 Registers
Figure
Register File Structure
Register Group APR0 APR1 SMR/STS STATUS CONFIG MICRO RESERVED ARBITER
Group System Mode/System Status Registers
Group Status Registers
Group Configuration Registers
Group Microcontrol Registers
Group Arbiter Control Register
reduce number memory locations occupied L64724 microprocessor memory, L64724 uses pair Address Pointer Registers (APR0 APR1). Address Pointer Registers have auto-increment feature that simplifies initialization procedure reduces number memory cycles needed read write registers. address pointer auto-increment features used whenever access Groups L64724 automatically points next register entry after complete access three groups. When writing reading register groups easier initially APR0 APR1 zero auto-increment mechanism step through locations within group. example, access PLL_N configuration register (Group first APR0 APR1 0x00 writing zero addresses then A[2:0] 0b100. value 0b100 address A[2:0] selects Group
L64724 Register Overview
L64724 internal 8-bit architecture. Most registers bits wide, while some either bits wide. registers memory-mapped system with 8-bit resolution. When accessing register that wider than bits, must read write three 8-bit sections. sections divided into least-significant byte (LSB), middle-significant byte (MB), most-significant byte (MSB). Each 8-bit section assigned specific address, requires individual memory cycle during programming.
3.1.1 Parallel Host Interface Mode1
L64724 addressable through either serial parallel host interface. interface used depends state HOST_MODE input when L64724 reset. interface selected follows:
HOST_MODE HIGH Parallel Host Interface mode HOST_MODE Serial Host Interface mode
interface mode cannot changed once part operation. following paragraphs show steps required read write L64724 registers when Parallel Host Interface mode. Serial Host Interface mode discussed Section 3.1.2, "Serial Host Interface Mode," page 3-6, Appendix "Programming L64724 Using Serial Protocol,". Figure through Figure demonstrate read write operation through parallel microprocessor interface. Note: PCLK signal must operate user able access Groups Group however, programmed absence PCLK.
read write registers using parallel interface mode, follow these steps: Issue hard reset L64724 three clock cycles, shown Figure 3.2. Wait wake-up time (tWK), which PCLK cycles, before continuing.
Serial Mode recommended interface mode. Logic does recommend parallel mode designs.
L64724 Registers
Figure
PCLK RESET
Issue Hard Reset
PCLK Cycles
APR0 APR1 registers zero writing zero Groups Figure 3.3. Figure
D[7:0] A[2:0] READ/WRITE DTACKn
Initialize APR0 APR1 Zero
Write Configuration registers Group Because APRs were both initialized zero, first location written Group location zero, second location written long address lines A[2:0] contain value auto-increment mechanism advances next location Group with every low-to-high transition CSn. Figure Figure show first writes Group 0x82 0x04 values shown D[7:0] typical values locations respectively. Section 3.6, "Group Configuration Registers," page 3-33, more details data values.
L64724 Register Overview
Figure
D[7:0] A[2:0] READ/WRITE DTACKn
Write Locations Group
also choose read back Group Configuration registers, demonstrated Figure 3.5. Just APR0 APR1 zero (see Figure 3.3) step through configuration locations using value A[2:0]. READ/WRITE signal asserted, autoincrement mechanism selects location then location Figure
Read Back Group
D[7:0] A[2:0] READ/WRITE DTACKn
3.1.2 Serial Host Interface Mode
Setting HOST_MODE during reset places L64724 Serial Host Interface mode. When L64724 addressed using serial interface, must first programmed with 2-bit slave address before other read write cycles. Appendix "Programming L64724 Using Serial Protocol," contains detailed description protocol used when programming L64724 Serial Host Interface mode.
L64724 Registers
Reset Affects Registers
There three separate resets available L64724, follows:
hardware RESET DEMOD_RST register (Group FEC_RST register (Group
Each reset affects registers differently, follows:
Toggling hardware RESET resets Group Group registers some Group registers. Registers Group unaffected. Setting DEMOD_RST External Output Control bits Reset Register (Group affects only bits Group registers that directly concerned with demodulator circuitry. Setting FEC_RST External Output Control bits Reset Register (Group resets System Mode/Status registers (Group bits Group registers that directly concerned with circuitry.
Registers Group unaffected reset operations. contents Group registers random immediately after power-up, retain their last known value after three reset operations listed above. following steps should followed when resetting L64724: Issue active-HIGH reset pulse RESET pin. reset pulse width must accordance with parameter tRWH (see Figure 8.4). Program Configuration (Group registers their proper values. Issue soft reset setting DEMOD_RST FEC_RST bits (Group 55). bits self-resetting, have cleared. After RESET been deasserted (LOW), wait wake-up time amount specified parameter (see Figure 8.4).
Reset Affects Registers
L64724 acquisition mode. When data applied L64724 input, ready start demodulating decoding. details reset affects various register bits, Section 3.10, "Reset Effect Register Bits," page 3-82.
Groups Address Pointer Register
Address Pointer Register (APR) 13-bit register that points registers Groups accessed when A[2:0] 0b000 0b001. Before accessing register location from Group must initialize contents with address first register entry that going read write. automatically increments after reading writing byte within Group (A[2:0] 0b010), Group (A[2:0] 0b011) Group (A[2:0] 0b100) Group (A[2:0] 0b101) register.
Address Pointer, APR[12:0]
consecutive writes required load complete APR. first write Group load eight LSBs, second Group load five MSBs. read well written. Group Data D[7:0]
APR[12:8]
Group Data D[7:0]
APR[7:0]
Reserved
reserved bits these registers internal test procedures future expansion should always zero.
L64724 Registers
access Group register: Initialize with address first register want access within particular register group. should write both bytes APR. Read write first register within register group accessing using appropriate register group address. addresses are: Group 2-0b010 Group 3-0b011 Group 4-0b100 Group 5-0b101 register 16-bit register, just perform another read write group register address access second byte. increments automatically. When through, automatically points next register group.
Group System Mode System Status Registers
Group contains 32-bit registers, System Mode Register (SMR) System Status Register (STS). System Mode Register accessed writing Group address, System Status Register accessed reading Group address. Because L64724 8-bit architecture, each 32-bit register accessed four 8-bit registers. microprocessor accesses these registers setting A[2:0] 0b010. access these registers point during Satellite Receiver operation without interrupting internal processing unit. Note: phase-locked loop must locked (PCLK running) status signals valid.
Group System Mode System Status Registers
3.4.1 System Mode Register (SMR)
32-bit System Mode Register (SMR) write-only register that allows external microprocessor control L64724. Table shows map. Table
VBER_IE S3_LS_IE S3_S_IE
Group System Mode Register (Write-Only)
SMR[7:0] S2_LS_IE S2_S_IE S1_LS_IE SMR[15:8] S1_S_IE Reserved
CLK_LK_ CLK_LLK_ CP_LK_IE CP_LLK_ Reserved uC_IE7 uC_IE6 uC_IE5
Reserved
CL_FS_LL_ CL_FS_UL_
SMR[23:16] TL_FS_LL_ TL_FS_UL_ SMR[31:24] uC_IE4 uC_IE3 uC_IE2 uC_IE1 uC_IE0
bits register allocated follows:
SMR[7:0] enable module interrupts. SMR[23:8] enable Demodulator interrupts. SMR[31:24] enable interrupts on-chip microcontroller.
Because arranged four 8-bit registers, microprocessor must perform four consecutive writes register address. lower eight bits must 0x00 order access bits SMR[7:0]. eight LSBs accessed first. autoincrement mechanism toggles Address Pointer Register after first access that next write goes SMR[15:8] bits. want access starting with bytes equal 0b01, 0b10, 0b11, respectively.
3-10
L64724 Registers
following register diagram shows organization SMR[7:0]. Descriptions bits follow register diagram. L64724 clears bits zero after software hardware reset.
SMR[7:0] VBER_IE S3_LS_IE S3_S_IE S2_LS_IE S2_S_IE S1_LS_IE S1_S_IE Reserved
VBER_IE
Viterbi Error Rate Monitor Interrupt Enable microprocessor sets VBER_IE enable interrupt when Viterbi decoder reaches period specified VMDC2 (the period over which Viterbi errors counted). L64724 always sets VBER register when this condition occurs.
VBER_IE Definition Disable Interrupt Viterbi count Enable Interrupt Viterbi count
S3_LS_IE
Stage Loss Synchronization Interrupt Enable microprocessor sets S3_LS_IE enable interrupt when Descrambler synchronization lost. S3_LS_IE used mode.
S3_LS_IE Definition Disable Interrupt Stage Loss Synchronization Enable Interrupt Stage Loss Synchronization
S3_S_IE
Stage Synchronization Interrupt Enable microprocessor sets S3_S_IE enable interrupt when Descrambler synchronization established. S3_S_IE used mode.
S3_S_IE Definition Disable Interrupt Stage Synchronization Enable Interrupt Stage Synchronization
Group System Mode System Status Registers
3-11
S2_LS_IE
Stage Loss Synchronization Interrupt Enable microprocessor sets S2_LS_IE enable interrupt when Deinterleaver/Reed-Solomon Decoder synchronization lost.
S2_LS_IE Definition Disable Interrupt Stage Loss Synchronization Enable Interrupt Stage Loss Synchronization
S2_S_IE
Stage Synchronization Interrupt Enable microprocessor sets S2_S_IE enable interrupt when Deinterleaver/Reed-Solomon Decoder synchronization established.
S2_S_IE Definition Disable Stage Synchronization Interrupt Enable Stage Synchronization Interrupt
S1_LS_IE
Stage Loss Synchronization Interrupt Enable microprocessor sets S1_LS_IE enable interrupt when Viterbi Decoder synchronization lost.
S1_LS_IE Definition Disable Stage Loss Synchronization Interrupt Enable Stage Loss Synchronization Interrupt
S1_S_IE
Stage Synchronization Interrupt Enable microprocessor sets S1_S_IE enable interrupt when Viterbi Decoder synchronization established.
S1_S_IE Definition Disable Stage Synchronization Interrupt Enable Stage Synchronization Interrupt
Reserved
Reserved Reserved Logic internal only should always cleared
following register diagram shows organization SMR[15:8]. Descriptions bits follow register diagram. L64724 sets bits SMR[15:8] after software hardware reset.
3-12 L64724 Registers
SMR[15:8] CLK_LK_IE CLK_LLK_IE CP_LK_IE CP_LLK_IE Reserved CL_FS_LL_IE CL_FS_UL_IE
CLK_LK_IE
Timing Lock Detect Interrupt Enable microcontroller sets CLK_LK_IE enable interrupt when timing lock detected. L64724 always sets CLK_LK register when this condition occurs.
CLK_LK_IE Definition Disable Interrupt Timing Lock Detect Enable Interrupt Timing Lock Detect
CLK_LLK_IE Timing Lock Lost Detect Interrupt Enable microcontroller sets CLK_LLK_IE enable interrupt when timing lock loss detected. L64724 always sets CLK_LLK register when this condition occurs.
CLK_LLK_IE Definition Disable Interrupt Timing Lock Lost Detect Enable Interrupt Timing Lock Lost Detect
CP_LK_IE
Carrier Phase Lock Detect Interrupt Enable microprocessor sets CP_LK_IE enable interrupt when Carrier Phase Lock detected (CAR_LC Group APR11). L64724 always sets CP_LK register when this condition occurs.
CP_LK_IE Definition Disable Interrupt Carrier Phase Lock Detect Enable Interrupt Carrier Phase Lock Detect
CP_LLK_IE
Carrier Phase Lock Lost Detect Interrupt Enable microprocessor sets CP_LLK_IE enable interrupt when Carrier Phase Lock Loss detected
Group System Mode System Status Registers
3-13
(CAR_LC Group APR11). L64724 always sets CP_LLK register when this condition occurs.
CP_LLK_IE Definition Disable Interrupt Carrier Phase Lock Loss Detect Enable Interrupt Carrier Phase Lock Loss Detect
Reserved
Reserved [11:10] Reserved bits Logic internal only must always cleared Frequency Sweep Lower Limit Reached Interrupt Enable microprocessor sets CL_FS_LL_IE enable interrupt when Carrier Loop Frequency Sweep reached lower limit. L64724 always sets CL_FS_LL register when this condition occurs.
CL_FS_LL_IE Definition Disable Interrupt Frequency Sweep Lower Limit Reached Detect Enable Interrupt Frequency Sweep Lower Limit Reached Detect
CL_FS_LL_IE
CL_FS_UL_IE Frequency Sweep Upper Limit Reached Interrupt Enable microprocessor sets CL_FS_UL_IE enable interrupt when Carrier Loop Frequency Sweep reached upper limit. L64724 always sets CL_FS_UL register when this condition occurs.
CL_FS_UL_IE Definition Disable Interrupt Frequency Sweep Upper Limit Reached Enable Interrupt Frequency Sweep Upper Limit Reached Detect
3-14
L64724 Registers
following register diagram shows organization SMR[23:16]. Descriptions fields follow register diagram. L64724 sets bits SMR[23:16] after software hardware reset.
SMR[23:16]
Reserved TL_FS_LL_IE TL_FS_UL_IE
Reserved
Reserved [23:18] Reserved bits Logic internal only must always cleared
TL_FS_LL_IE Frequency Sweep Lower Limit Reached Interrupt Enable microprocessor sets TL_FS_LL_IE enable interrupt when Timing Loop Frequency Sweep reached lower limit. L64724 always sets TL_FS_LL register when this condition occurs.
TL_FS_LL_IE Definition Disable Interrupt Frequency Sweep Lower Limit Reached Detect Enable Interrupt Frequency Sweep Lower Limit Reached Detect
TL_FS_UL_IE Frequency Sweep Upper Limit Reached Interrupt Enable microprocessor sets TL_FS_UL_IE enable interrupt when Frequency Sweep reached upper limit. L64724 always sets TL_FS_UL register when this condition occurs.
TL_FS_UL_IE Definition Disable Interrupt Frequency Sweep Upper Limit Reached Enable Interrupt Frequency Sweep Upper Limit Reached Detect
Group System Mode System Status Registers
3-15
following register diagram shows organization SMR[31:24]. Descriptions bits follow register diagram. L64724 clears bits SMR[31:24] after software hardware reset.
SMR[31:24]
uC_IE7 uC_IE6 uC_IE5 uC_IE4 uC_IE3 uC_IE2 uC_IE1 uC_IE0
uC_IE7
Interrupt Enable microprocessor sets uC_IE7 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore this user-programmable interrupt. Interrupt Enable microprocessor sets uC_IE6 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt. Interrupt Enable microprocessor sets uC_IE5 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt. Interrupt Enable microprocessor sets uC_IE4 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt. Interrupt Enable microprocessor sets uC_IE3 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt. Interrupt Enable microprocessor sets uC_IE2 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt.
uC_IE6
uC_IE5
uC_IE4
uC_IE3
uC_IE2
3-16
L64724 Registers
uC_IE1
Interrupt Enable microprocessor sets uC_IE1 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt. Interrupt Enable microprocessor sets uC_IE0 enable interrupt from on-chip microcontroller. microcode define meaning interrupt therefore, this user-programmable interrupt.
uC_IE0
3.4.2 System Status Register (STS)
Register read-only register that provides external microprocessor access L64724 status information. Table shows map. Table
VBER S3_LS S3_S S2_LS S2_S STS[15:8] S1_LS S1_S Reserved
Group System Status Register (Read-Only)
STS[7:0]
CLK_LK CLK_LLK CP_LK CP_LLK STS[23:16] CL_FS_LL CL_FS_UL
Reserved STS[31:24]
TL_CL_FS_
TL_CL_FS_
uC_I7 uC_I6 uC_I5 uC_I4 uC_I3 uC_I2 uC_I1 uC_I0
register bits indicate event that generated internal interrupt condition. interrupt status bits regardless enable interrupt bits Register. internal status updated every L64724 CLK. When microprocessor reads status, current information buffered special-purpose 32-bit buffer that locks value until microprocessor read operation.
Group System Mode System Status Registers
3-17
Four consecutive read operations must done same Group address (A[2:0] 0b010) access four bytes status registers. register bits cleared after hardware reset. They also cleared each time register byte read-when read eight LSBs, eight interrupts cleared, when read eight MSBs, eight interrupts cleared. following register diagram shows organization STS[7:0]. Descriptions bits follow register diagram.
STS[7:0]
VBER S3_LS S3_S S2_LS S2_S S1_LS S1_S Reserved
VBER
Viterbi Error Rate Flag L64724 sets VBER when period specified VMDC2 (Group 4-APR reached. L64724 also generates interrupt VBER_IE set. L64724 clears VBER after reset Group (STS) read.
VBER Definition VMDC2 period reached VMDC2 period reached
S3_LS
Stage Loss Synchronization Flag L64724 sets S3_LS when Descrambler synchronization module determines that synchronization lost. also generates interrupt S3_LS_IE SMR. L64724 clears S3_LS after reset Group (STS) read.
S3_LS Definition Stage Synchronization status unchanged Loss Stage Synchronization detected
S3_S
Stage Synchronization Flag L64724 sets S3_S when Descrambler synchronization module acquires synchronization. L64724 also generates interrupt S3_S_IE
3-18
L64724 Registers
SMR. L64724 clears S3_S after reset Group (STS) read.
S3_S Definition Stage Synchronization status unchanged Stage Synchronization acquired
S2_LS
Stage Loss Synchronization Flag L64724 sets S2_LS when Deinterleaver/Reed-Solomon Decoder synchronization module determines that synchronization lost. L64724 also generates interrupt S2_LS_IE SMR. L64724 clears S2_LS after reset Group (STS) read.
S2_LS Definition Stage Synchronization status unchanged Loss Stage Synchronization detected
S2_S
Stage Synchronization Flag L64724 sets S2_S when Deinterleaver/Reed-Solomon Decoder synchronization module acquires synchronization. L64724 also generates interrupt S2_S_IE SMR. L64724 clears S2_S after reset Group (STS) read.
S2_S Definition Stage Synchronization status unchanged Stage Synchronization acquired
S1_LS
Stage Loss Synchronization Flag L64724 sets S1_LS when Viterbi Decoder synchronization module determines that synchronization lost. L64724 also generates interrupt S1_LS_IE SMR. L64724 clears S1_LS after reset Group (STS) read.
S1_LS Definition Stage Synchronization status unchanged Loss Stage Synchronization detected
Group System Mode System Status Registers
3-19
S1_S
Stage Synchronization Flag L64724 sets S1_S when Viterbi Decoder synchronization module acquired synchronization. L64724 also generates interrupt S1_S_IE SMR. L64724 clears S1_S after reset Group (STS) read.
S1_S Definition Stage Synchronization status unchanged Stage Synchronization acquired
Reserved
Reserved This reserved Logic internal only. Reading this will give unpredictable results.
following register diagram shows organization STS[15:8]. Descriptions bits follow register diagram.
STS[15:8]
CLK_LK CLK_LLK CP_LK CP_LLK Reserved CL_FS_LL CL_FS_UL
CLK_LK
Timing Lock Established L64724 sets CLK_LK when Timing Lock established.
CLK_LK Definition Timing Lock Status Unchanged Timing Lock Established
CLK_LLK
Timing Lock Lost L64724 sets CLK_LLK when Timing Lock lost.
CLK_LLK Definition Timing Lock Status Unchanged Timing Lock Lost
3-20
L64724 Registers
CP_LK
Carrier Phase Lock Established L64724 sets CP_LK when Carrier Phase Lock established.
CP_LK Definition Carrier Phase Lock Status Unchanged Carrier Phase Lock Established
CP_LLK
Carrier Phase Lock Lost L64724 sets CP_LLK when Carrier Phase Lock lost.
CP_LLK Definition Carrier Phase Lock Status Unchanged Carrier Phase Lock Lost
Reserved
Reserved [11:10] Reserved bits Logic internal only must always cleared Frequency Sweep Lower Limit Reached L64724 sets CL_FS_LL when lower limit Carrier Loop Frequency Sweep reached.
FS_LL Definition Frequency Sweep Status Unchanged Frequency Sweep Lower Limit Reached
CL_FS_LL
CL_FS_UL
Frequency Sweep Upper Limit Reached L64724 sets CL_FS_UL when upper limit Carrier Loop Frequency Sweep reached.
FS_UL Definition Frequency Sweep Status Unchanged Frequency Sweep Upper Limit Reached
following register diagram shows organization STS[23:16]. Descriptions fields follow register diagram.
Group System Mode System Status Registers
3-21
STS[23:16]
Reserved TL_CL_FS_LL TL_CL_FS_UL
Reserved
Reserved [23:18] These bits reserved Logic internal only. bits, when read, return value zero. Frequency Sweep Lower Limit Reached L64724 sets TL_CL_FS_LL when lower limit Timing Loop Frequency Sweep reached.
TL_CL_FS_LL Definition Frequency Sweep Status Unchanged Frequency Sweep Lower Limit Reached
TL_CL_FS_LL
TL_CL_FS_UL Frequency Sweep Upper Limit Reached L64724 sets TL_CL_FS_UL when upper limit Timing Loop Frequency Sweep reached.
TL_CL_FS_UL Definition Frequency Sweep Status Unchanged Frequency Sweep Upper Limit Reached
following register diagram shows organization STS[31:24].
STS[31:24]
uC_I7 uC_I6 uC_I5 uC_I4 uC_I3 uC_I2 uC_I1 uC_I0
microcontroller interrupt register (uC_I) bits reset after hardware reset. They also reset each time register byte read. definition each interrupt determined microcode. interrupts user-defined.
3-22
L64724 Registers
Group Status Registers
Group consists number internal status registers that used diagnostics performance evaluation purposes. registers internally updated every PCLK cycle read asynchronously. When microprocessor reads register, current information buffered special-purpose buffer that stores value respective register until read operation. particular, registers that occupy more than byte frozen when first byte read. With exception uC_Status_bytes, L64724 clears bits Group registers after software hardware reset. uC_Status_bytes cleared through hardware reset Reset_Mode bit, located Group 520, definition software reset, Group FEC_RST DEMOD_RST. Table shows addresses fields Group registers. Table
(Sheet
Group Register
Reed-Solomon Corrected Error Count byte, CEC[7:0] Reed-Solomon Corrected Error Count high byte, CEC[15:8] Reed-Solomon Uncorrected Error Count byte, UEC[7:0] Reed-Solomon Uncorrected Error Count high byte, UEC[15:8] Viterbi Error Rate Count byte, VBERC[7:0] Viterbi Error Rate Count high byte, VBERC[15:8] Demod_SNR XCTR_IN Reserved Chip_ID
Frequency Deviation, CAR_NCOF[7:0] Frequency Deviation, CAR_NCOF[15:8] Frequency Deviation, CAR_NCOF[23:16] Loop Voltage Meter, PWR_LVL[7:0] Reserved Active Reserved CAR_LC Reserved
Reserved Reserved
Read Back, RI[5:0] Read Back, RQ[5:0]
Group Status Registers
3-23
Table
(Sheet
Group Register (Cont.)
Reserved Reserved Reserved uC_Status_byte0 [7:0] uC_Status_byte1 [7:0] uC_Status_byte2 [7:0] uC_Status_byte3 [7:0] uC_Status_byte4 [7:0] Demodulator Estimate, SNR[7:0] Reserved Demodulator Estimate, SNR[11:8] IMQ_ Active
Viterbi Code Rate[2:0]
3.5.1 Reed-Solomon Corrected Error Count (Group
When read, Reed-Solomon Corrected Error Count (CEC) register presents corrected byte error count since last reset. byte error count function RS_Bit/Byte_Select configuration (Group D7). When error count mode chosen, value register represents error count, which multiplied eight. When written, register reset field bits long. located count saturates (stops) when reaches maximum count (65,535), counter reset after read. When register written, bits cleared Read/Write:
Reed-Solomon Corrected Error Count high byte, CEC[15:8] Reed-Solomon Corrected Error Count byte, CEC[7:0]
Reset Value: 0x0000
3-24
L64724 Registers
3.5.2
Reed-Solomon Uncorrected Error Count (Group
When read, Reed-Solomon Uncorrected Error Count (UEC) register presents uncorrected blocks count since last reset. When written, register cleared field bits long. located count saturates (stops) when reaches maximum count (65,535), counter reset after read. When register written, bits cleared. Read/Write:
Reed-Solomon Uncorrected Error Count high byte, UEC[15:8] Reed-Solomon Uncorrected Error Count byte, UEC[7:0]
Reset Value: 0x0000
3.5.3
Viterbi Error Rate Count (Group
When read, Viterbi Error Rate Count register presents Viterbi decoder error count during time period specified VMDC2 (Group 5,6,7). Viterbi Error rate Count (VBERC) field bits long. located actual number errors equal four times VBERC. VBERC updated each time Viterbi error encountered, reset beginning each VMDC2 period. Read/Write:
Viterbi Error Rate Count high byte, VBERC[15:8] Viterbi Error Rate Count byte, VBERC[7:0]
Reset Value: 0x0000
3.5.4 Control Input, SNR, Chip_ID register (Group
Control Input, SNR, Chip_ID register contains Demodulator Signal-to-Noise Ratio (Demod_SNR) bit, Control Input (XCTR_IN), Chip_ID bit.
Group Status Registers
3-25
Read/Write:
Reserved
Reset Value: 0x0000
Chip_ID
Demod XCTR_IN _SNR
Demod_SNR Demodulator Signal Noise Ratio When read, Demod_SNR gives indication SNR. When (above threshold), When good (below threshold), thresholds discussed Section 5.7.2.1, "Phase Error Estimator," page 5-16, shown Figure 5.7. XCTR_IN External Control Input When read, XCTR_IN shows logic level applied External Control Input (XCTR_IN) pin. Reserved These bits reserved.
Reserved Chip_ID
[5:1]
Chip Identification When read, this shows stepping L64724 When Chip_ID indicates that L64724 L64724b. When indicates that L64724a.
3.5.5 Frequency Deviation (Group
L64724 puts result Carrier Loop (number-controlled oscillator) frequency measurement into Frequency Deviation 24-bit register. value, corresponds frequency deviation observed carrier loop function Noise Block Converter (LNB) drift. updated 24-bit CAR_NCOF value, first access APR7.
3-26
L64724 Registers
ReaPBd/WPBrite:
CAR_NCOF[23:16] CAR_NCOF[15:8] CAR_NCOF[7:0]
Reset Value: 0x0000
3.5.6
Automatic Gain Control (AGC) Loop Voltage Meter (Group
L64724 stores loop control voltage Loop Voltage Meter register. Section 5.8.3, "Power Level," page 5-22, equation that relates VAGC PWR_LVL[7:0]. Section B.1, "L64724 QPSK Demodulator Acquisition Debugging Tips," more details PWR_LVL[7:0]. Read/Write:
PWR_LVL[7:0]
Reset Value: 0x00
3.5.7
Carrier Synchronization Status (Group
Carrier Synchronization Status register contains Carrier Loop pipeline synchronization status bits. Read/Write:
Reset Value: 0x00
Reserved uC_Active Reserved CAR_LC Reserved
Reserved
Reserved This reserved Logic internal only. When read, returns indeterminate value.
Group Status Registers
3-27
uC_Active
Microcontroller Active Flag L64724 sets uC_Active indicate that internal microcontroller running.
uC_Active Definition Internal microcontroller active Internal microcontroller running
Reserved
Reserved Reserved Logic internal only must always Carrier Phase Lock Flag L64724 sets CAR_LC indicate that carrier phase lock detector locked.
CAR_LC Definition Carrier Phase Lock detector lock Carrier Phase Lock detector locked
CAR_LC
Reserved
Reserved This reserved Logic internal only. When read, returns indeterminate value. Stage Synchronization Flag L64724 sets when Descrambler synchronization module synchronization. When this Descrambler module synchronized. valid Mode.
Definition Descrambler Sync Descrambler Sync
Stage Synchronization Flag L64724 sets when Deinterleaver/Reed-Solomon Decoder synchronization module synchronization. When
3-28
L64724 Registers
Deinterleaver/Reed-Solomon Decoder synchronized.
Definition Deinterleaver/Reed-Solomon Decoder Synchronization Deinterleaver/Reed-Solomon Decoder Synchronization
Stage Synchronization Flag L64724 sets when Viterbi Decoder synchronization module synchronization. When Viterbi Decoder synchronized.
Definition Viterbi Decoder Synchronization Viterbi Decoder Synchronization
3.5.8
Read Back (Group
Readback register displays digital value channel input. Read/Write:
RI[5:0]
Reset Value: 0x00
Reserved
Reserved
Reserved [7:6] These bits reserved Logic internal only. When read, they return indeterminate value. Read Back [5:0] This register displays value RI[5:0] input bus. Note that PCLK needs running this feature operate properly.
3.5.9
Read Back (Group
Readback register displays digital value channel input.
Group Status Registers
3-29
Read/Write:
RQ[5:0]
Reset Value: 0x00
Reserved
Reserved
Reserved [7:6] These bits reserved Logic internal only. When read, they return indeterminate value. Read Back [5:0] This register displays value RQ[5:0] input bus. Note that PCLK needs running this feature operate properly.
3.5.10 Viterbi Code Rate (Group
Read/Write:
Reserved IMQ_ Active
Reset Value: 0x00
Viterbi Code Rate, VCR[2:0]
Reserved
Reserved Bits [7:4] These bits reserved Logic internal only. When read, they return indeterminate value. Mode Active When IMQ_Active Indicates that state machine detected inversion1 compensating automatically. Viterbi Code Rate [2:0] These bits display Viterbi decoder code rate that found during acquisition process convolutional decoder. Viterbi Code Rate information this register meaningful only after synchronization
IMQ_Active
portion spectrum inverted portion inverted.
3-30
L64724 Registers
been achieved indicated when
VCR[2:0] Definition Rate Rate Rate Rate Rate Rate Unused Unused
3.5.11 Reserved (Group
Read/Write:
Reserved
Reset Value: 0x00
Reserved
Reserved Bits [7:0] These bits reserved Logic internal only. When read, they will return indeterminate value.
3.5.12 Reserved (Group
Read/Write:
Reserved
Reset Value: 0x00
Reserved
Reserved Bits [7:0] These bits reserved Logic internal only. When read, they will return indeterminate value.
3.5.13 Status Bytes (Group
status bytes user-defined. They cleared hardware reset when microcontroller disabled.
Group Status Registers
3-31
Read/Write:
Reset Value: 0x0000
MicroController Status Byte uCSB4[7:0] MicroController Status Byte uCSB3[7:0] MicroController Status Byte uCSB2[7:0] MicroController Status Byte uCSB1[7:0] MicroController Status Byte uCSB0[7:0]
uCSB0
MicroController Status Byte [7:0] UCSB0 user-defined status byte updated defined microcoded instructions on-chip microcontroller. MicroController Status Byte [7:0] UCSB1 user-defined status byte updated defined microcoded instructions on-chip microcontroller. MicroController Status Byte [7:0] UCSB2 user-defined status byte updated defined microcoded instructions on-chip microcontroller. MicroController Status Byte [7:0] UCSB3 user-defined status byte updated defined microcoded instructions on-chip microcontroller. MicroController Status Byte [7:0] UCSB4 user-defined status byte updated defined microcoded instructions on-chip microcontroller.
uCSB1
uCSB2
uCSB3
uCSB4
3-32
L64724 Registers
3.5.14 Demodulator Estimate (Group
Read/Write:
Reserved Demod Estimate, SNR[7:0]
Reset Value: 0x0000
Demod Estimate, SNR[11:8]
When read, Demodulator Signal Noise Ratio (SNR) Estimate register presents value Demodulator estimate. bits long. found Section 5.7.2.1, "Phase Error Estimator," page 5-16, additional details SNR[7:0].
Group Configuration Registers
Although most Group registers bits wide, some wide bits. accesses done 8-bit widths. Address Pointer Register (APR) used access these registers described Section 3.3, "Groups Address Pointer Register."
Group Configuration Registers
3-33
Group registers affected reset-the values random immediately after power-up retain their last known value after three reset operations shown Section 3.2, "Reset Affects Registers." Table shows addresses fields Group registers. Table
[5:0]
(Sheet
Group Register
Reserved
PLL_N[5:0] PLL_S[5:0] SYNC2_ PLL_T[4:0] Reserved PLL_M[1:0]
Reserved DVB_
Viterbi Code Rate, VCR[2:0]
Viterbi Data Count VMDC1[7:0] Viterbi Data Count VMDC2[7:0], byte Viterbi Data Count VMDC2[15:8], middle byte Viterbi Data Count VMDC2[23:16], high byte Viterbi Maximum Error Count[7:0], Rate Viterbi Maximum Error Count[7:0], Rate Viterbi Maximum Error Count[7:0], Rate Viterbi Maximum Error Count[7:0], Rate Viterbi Maximum Error Count[7:0], Rate Viterbi Maximum Error Count[7:0], Rate Synchronization Word[7:0] Reserved Auto Rate Reserved Sync Status Select, SSS[1:0] IMQ_EN Bypass L[1:0] Sync States Track, SST[1:0]
Reserved Reserved
Sync States Acq, SSA[1:0] Reserved
3-34
L64724 Registers
Table
[5:0]
(Sheet
Group Register (Cont.)
PLL_RESET DF_SELECT[2:0] Reserved PCLK_INV PLL_BP LCLK_ CLK_DIV2[7:0] DC_Offset_On_ Off[1:0] Reserved PWR_REF[7:0] Reserved INT_DC PWR_BW[1:0] CLK_DIV2[12:8] DF_GAIN[1:0] DF_RATIO[2:0] Reserved CLK_DIV1[4:0] MF_20_
Scale factor DEMI, DEMQ, SCALE[7:0] Estimator Threshold, SNR_THS[7:0] Carrier Loop Lambda, CAR_LAMBDA_SEL[3:0] Carrier Loop CAR_MU_SEL[3:0]
Carrier Phase Lock Detector Threshold, CAR_LC_THSL[7:0] Reserved Bit/Byte Select Errorout_ Invert SPI_On_ Reserved
Carrier Synchronizer Sweep Rate, CAR_SWR[7:0] Carrier Synchronizer Sweep Rate, CAR_SWR[15:8] Carrier Synchronizer Upper Sweep Limit, CAR_USWL[7:0] Carrier Synchronizer Upper Sweep Limit, CAR_USWL[15:8] Carrier Synchronizer Lower Sweep Limit, CAR_LSWL[7:0] Carrier Synchronizer Lower Sweep Limit, CAR_LSWL[15:8]
Group Configuration Registers
3-35
Table
[5:0]
Group Register (Cont.)
Carrier Loop Filter Initialization, CAR_LF_INIT[7:0] Carrier Loop Filter Initialization, CAR_LF_INIT[15:8] Carrier Loop Filter Initialization, CAR_LF_INIT[23:16] CAR_ SWP_ SWAP CAR_ ERROR_ SWAP CAR_ AUTO_ Reserved CAR_ PED_SEL CAR_ OPEN CAR_SW
Clock Loop Lambda, CLK_LAMBDA_SEL[3:0]
Clock Loop CLK_MU_SEL[3:0]
Clock Synchronizer Sweep Rate, CLK_SWR[7:0] Clock Synchronizer Sweep Rate, CLK_SWR[15:8] Clock Synchronizer Upper Sweep Limit, CLK_USWL[7:0] Clock Synchronizer Upper Sweep Limit, CLK_USWL[15:8] Clock Synchronizer Lower Sweep Limit, CLK_LSWL[7:0] Clock Synchronizer Lower Sweep Limit, CLK_LSWL[15:8] Clock Loop Bias, CLK_BIAS[7:0] Clock Loop Bias, CLK_BIAS[15:8] Clock Loop Bias, CLK_BIAS[23:16] Reserved CLK_SWP _SWAP SNR_EST CLK_ ERROR_ SWAP PWRP_ OB_2C CLK_ AUTO_ ADC_PD Clock Loop Bias, CLK_BIAS[30:24] AGC_ CLK_SEL PWRP Reserved CLK_ OPEN CLK_SW
ADC_BP
LOCK_
Reserved
CLK_ ALPHA_ FEC_
External Control Output Bits, XCTR[3:0] Reserved Reserved
DEMOD _RST
(Sheet
3-36
L64724 Registers
Table
[5:0]
(Sheet
Group Register (Cont.)
Reserved
Serial Transmission Start Data, TXSD[6:0] Serial Transmission Data, STXD[7:0] Serial Transmission Data, TXED[7:0] Serial_B FMODE Serial_C[1:0] SPI_CLK_ SPI_MOD E_A_B Reserved SPI_Gain[7:0](LSB) Reserved SPI_Bias[7:0] (LSB) SPI_Bias[15:8] (MSB) Reserved SPI_Bias[22:16] Timing Lock Detector Threshold, CLK_LC_THSL[7:0] SPI_M[3:0] SPI_N[3:0]
Reserved
Serial_A
SPI_Gain[9:8]
3.6.1 Parameter (Group
Configuration Parameter (PLL_N[5:0]) configures module clock synthesis. Read/Write:
PLL_N[5:0]
Reserved
Reserved
This internal test that must Reserved This internal test that must cleared
Group Configuration Registers
3-37
PLL_N
Configuration Parameter [5:0] PLL_N[5:0] four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information, Section 4.2, "PLL Clock Generation," page 4-3.
3.6.2 Parameter (Group
Configuration Parameter (PLL_S[5:0]) configures module clock synthesis. Read/Write:
PLL_S[5:0]
Reserved
Reserved
Reserved [7:6] Reserved bits internal test bits that must cleared Configuration Parameter [5:0] PLL_S[5:0] four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information Section 4.2, "PLL Clock Generation."
PLL_S
3.6.3 Parameter Demodulator Symbol Select (Group
Configuration Parameter (PLL_T[4:0]) configures module clock synthesis. This register also contains bits configure demodulator select symbol format. Read/Write:
DVB_DSS PLL_T[4:0]
Symbol Format indicates format incoming symbol stream. IMQ_EN (APR must cleared
3-38
L64724 Registers
take effect. When IMQ_EN will disregarded.
Symbol Format I,-Q
DVB_DSS
DVB/DSS Mode Select DVB_DSS indicates format incoming symbol stream. L64724 supports data stream formats that conform either Digital Video Broadcast Standard (DVB) specifications Digital Satellite System (DSS). Note that when mode selected (DVB_DSS indicator (APR must cleared
DVB_DSS Symbol Format Format Selected Format Selected
QPSK/BPSK Format Select specify format incoming symbol stream. should cleared systems that input QPSK symbol pair once cycle. should BPSK input stream only).
Symbol Stream Format QPSK BPSK
PLL_T
Configuration Parameter [4:0] PLL_T[4:0] four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information, Section 4.2, "PLL Clock Generation," page 4-3. Allowed values even numbers.
Group Configuration Registers
3-39
3.6.4 Parameter Transport Viterbi Code Rate Select (Group
Configuration Parameter (PLL_M[1:0]) configures module clock synthesis. This register also contains bits Viterbi Decoder module code rate configure Transport Error Indicator. Read/Write:
Viterbi Code Rate, VCR[2:0]
SYNC2_ Reserved
PLL_M[1:0]
Viterbi Code Rate [7:5] these bits select code rate L64724 Viterbi decoder module. three bits assigned follows:
VCR[2:0] Definition Rate Rate Rate Rate Rate Rate Unused Unused
bits disregarded when automatic Viterbi rate acquisition selected (Auto Rate bit: Group Transport Error Indicator Select When Transport Error Indicator Select activates transport error indicator mechanism. this mode, first following synchronization byte Transport Packet forced HIGH whenever ReedSolomon decoder finds data block uncorrectable. Otherwise, remains unchanged. When cleared transport error indicator will time (see MPEG-2 System
3-40
L64724 Registers
Specification H.222 Transport Stream Packet Layer, paragraph 2.4.3.2). Using feature allows simpler interface Logic L64007 Transport Demultiplexer. more information, Logic L64007 MPEG-2, DVB, TSAT Transport Demultiplexer Technical Manual.
SYNC2_MOD Sync2 Modified SYNC2_MOD selects alternate method acquiring Sync should normal operation. Reserved PLL_M Reserved This must cleared proper operation.
Frequency Range Module [1:0] PLL_M four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information Section 4.2, "PLL Clock Generation," page 4-3. Configure PLL_M[1:0] bits tell L64724 frequency range PLL.
PLL_M[1:0] Range 40-50 50-60 60-70 70-90
3.6.5 Viterbi Maximum Data Count (Group
This register specifies number valid symbols, divided 256, over which number Viterbi decoded symbol errors counted synchronization. example, value VMDC1[7:0] 0x02 specifies data bits.
Equation
Symbols VMDC1 -256
Group Configuration Registers
3-41
more information Section 7.1.3, "Viterbi Monitor," page 7-7. Read/Write:
Viterbi Maximum Data Count VMDC1[7:0]
3.6.6 Viterbi Data Count (Group
These registers specify number valid symbols, divided four, over which number symbol errors Viterbi output data stream counted, after synchronization. symbol error count then displayed VBERC (Group 4,5). value VMDC2 occupies bits arranged three bytes with being least significant being most significant bit. example, value VMDC2[23:0] 0x00.00F0 specifies data bits.
Equation
Symbols VMDC2
more information Section 7.1.3, "Viterbi Monitor." Read/Write:
Viterbi Maximum Data Count High Byte, VMDC2[23:16] Viterbi Maximum Data Count Middle Byte, VMDC2[15:8] Viterbi Maximum Data Count Byte, VMDC2[7:0]
3.6.7 Viterbi Maximum Error Count, Rate (Group
This register specifies maximum number Viterbi symbol errors that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization.
3-42
L64724 Registers
Note:
This register used during Viterbi code rate acquisition Rate 1/2.
Whenever symbol error count from internal error counter exceeds value VMBEC_1_2[7:0], synchronization module concludes that Viterbi decoder module synchronization proceeds adjust phase incoming symbol stream until synchronization reached. symbol error count given Equation 3.3.
Equation Number Symbol Errors VMBEC_1_2
example, value VMBEC_1_2[7:0] 0x03 specifies errors. more information, Section 7.1.3, "Viterbi Monitor," page 7-7. Note that software reset (FEC_RST, does affect contents register. Read/Write:
Viterbi Maximum Error Count VMBEC_1_2[7:0], Rate
3.6.8 Viterbi Maximum Error Count, Rate (Group
This register specifies maximum number Viterbi symbol errors that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization. Note: This register used during Viterbi code rate acquisition Rate 2/3.
Whenever symbol error count from internal error counter exceeds value VMBEC_2_3[7:0], synchronization module concludes that Viterbi decoder module synchronization proceeds adjust phase incoming symbol stream until synchronization reached. symbol error count given Equation 3.4.
Equation Number Symbol Errors VMBEC_2_3
Group Configuration Registers
3-43
example, value VMBEC_2_3[7:0] 0x03 specifies errors. more information, Section 7.1.3, "Viterbi Monitor." Note that software reset (FEC_RST, does affect contents register. Read/Write:
Viterbi Maximum Error Count VMBEC_2_3[7:0], Rate
3.6.9 Viterbi Maximum Error Count, Rate (Group
This register specifies maximum number Viterbi symbol errors that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization. Note: This register used during Viterbi code rate acquisition Rate 3/4.
Whenever symbol error count from internal error counter exceeds value VMBEC_3_4[7:0], synchronization module concludes that Viterbi decoder module synchronization proceeds adjust phase incoming symbol stream until synchronization reached. symbol error count given Equation 3.5.
Equation Number Symbol Errors VMBEC_3_4
example, value VMBEC_2_3[7:0] 0b0000.0011 specifies errors. more information, Section 7.1.3, "Viterbi Monitor," page 7-7. Note that software reset (FEC_RST, does affect contents register. Read/Write:
Viterbi Maximum Error Count VMBEC_3_4[7:0], Rate
3-44
L64724 Registers
3.6.10 Viterbi Maximum Error Count, Rate (Group
This register specifies maximum number Viterbi symbol errors that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization. Note: This register used during Viterbi code rate acquisition Rate 5/6.
Whenever symbol error count from internal error counter exceeds value VMBEC_5_6[7:0], synchronization module concludes that Viterbi decoder module synchronization proceeds adjust phase incoming symbol stream until synchronization reached. symbol error count given Equation 3.6.
Equation Number Symbol Errors VMBEC_5_6
example, value VMBEC_5_6[7:0] 0x03 specifies errors. more information, Section 7.1.3, "Viterbi Monitor," page 7-7. Note that software reset (FEC_RST, does affect contents register. Read/Write:
Viterbi Maximum Error Count VMBEC_5_6[7:0], Rate
3.6.11 Viterbi Maximum Error Count, Rate (Group
This register specifies maximum number Viterbi symbol errors that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization. Note: This register used during Viterbi code rate acquisition Rate 6/7.
Whenever symbol error count from internal error counter exceeds value VMBEC_6_7[7:0], synchronization module concludes that Viterbi decoder module synchronization
Group Configuration Registers
3-45
proceeds adjust phase incoming symbol stream until synchronization reached. symbol error count given Equation 3.7.
Equation Number Symbol Errors VMBEC_6_7
example, value VMBEC_6_7[7:0] 00x03 specifies errors. more information, Section 7.1.3, "Viterbi Monitor," page 7-7. Note that software reset (FEC_RST, does affect contents register. Read/Write:
Viterbi Maximum Error Count VMBEC_6_7[7:0], Rate
3.6.12 Viterbi Maximum Error Count, Rate (Group
This register specifies maximum number Viterbi symbol errors that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization. Note: This register used during Viterbi code rate acquisition Rate 7/8.
Whenever symbol error count from internal error counter exceeds value VMBEC_7_8[7:0], synchronization module concludes that Viterbi decoder module synchronization proceeds adjust phase incoming symbol stream until synchronization reached. symbol error count given Equation 3.8.
Equation Number Symbol Errors VMBEC_7_8
3-46
L64724 Registers
example, value VMBEC_7_8[7:0] 0b0000.0011 specifies errors. more information, Section 7.1.3, "Viterbi Monitor," page 7-7. Note that software reset (FEC_RST, does affect contents register. Read/Write:
Viterbi Maximum Error Count VMBEC_7_8[7:0], Rate
3.6.13 Synchronization Word (Group
This register contains synchronization word used synchronization module stages three. Within this byte, chronologically oldest chronologically newest. Section B.4, "QPSK Demodulator Configuration Example: Data Rates," page B-30, typical setting Synchronization Word[7:0]. Read/Write:
Synchronization Word[7:0]
Group Configuration Registers
3-47
3.6.14 Mismatching Bits Sync Tracking Mode (Group
This register used maximum number mismatching bits allowed declare match when comparing data stream reference synchronization word during tracking phase second synchronization stage. Read/Write:
L[1:0]
Reserved Auto Rate
Reserved
IMQ_EN DI_Bypass
Reserved Auto Rate
Reserved This should cleared normal operation.
Viterbi Decoder Automatic Rate Acquisition Auto Rate bit, when enables automatic acquisition Viterbi code rate convolutional decoder. When mode selected (APR DVB_DSS code rates that being considered automatic acquisition 1/2, 2/3, 3/4, 7/8. When mode selected (APR DVB_DSS rates include 6/7. bits (APR disregarded when Auto Rate set. code rate identified Auto Rate mechanism available under Group (Viterbi Coder Rate Registers). When Auto Rate Viterbi code rate determined contents field (APR
Auto Rate Viterbi Decoder Acquisition Mode Code rate determined VCR[2:0] Automatic Code Rate Acquisition
Reserved
Reserved [5:4] Reserved bits internal only. They should always cleared produce random results when read.
3-48
L64724 Registers
IMQ_EN
Format Resolution Enable When IMQ_EN synchronization mechanism used convolutional decoder automatically resolves phase reflection -Q). this case, polarity (APR disregarded. When IMQ_EN determines symbol format.
IMQ_EN Symbol Format Determined value (APR Automatically determined synchronization mechanism.
DI_Bypass
Deinterleaver Bypass When DI_Bypass causes Deinterleaver module bypassed. When deinterleaver functions according specifications. Mismatching Bits, Tracking Mode, Sync2 [1:0] This field used maximum number mismatching bits allowed declare match when comparing eight bits data stream reference synchronization word during tracking phase second synchronization stage. L[1:0] bits configured from 0b00 0b10. Higher values L[1:0] result smaller probability loss lock random noise. Lower values result higher probability loss.
L[1:0] Number Mismatching Bits Illegal Value
L[1:0]
3.6.15 Synchronization States BCLKOUT Format (Group
This register used select algorithms used synchronization modules, which module's synchronization status will shown SYNC output pin. register also selects frequency clock that will output BCLKOUT pin.
Group Configuration Registers
3-49
Read/Write:
Reserved
[1:0]
[1:0]
[1:0]
Reserved
Reserved [7:6] Reserved bits must cleared proper operation. Synchronization Status/XCTR[3] Select [5:4] SSS[1:0] bits allow observe synchronization status three synchronization modules XCTR[3] output XCTR[3] output pin. synchronization modules that observed Viterbi Decoder synchronization, Deinterleaver/Reed-Solomon Decoder synchronization, Descrambler synchronization. Program SSS[1:0] field determine which these status bits will propagated XCTR[3] pin. Note that OS[4:0] (Group should 0b00000.
SSS[1:0] XCTR[3] Connection Viterbi decoder sync DI/RS decoder sync Descrambler sync XCTR[3] (APR
SSS[1:0]
SSA[1:0]
Synchronization States, Acquisition Mode [3:2] second synchronization module (after Viterbi Decoder before Deinterleaver module) allows three different state diagrams used acquisition phase. number properly identified synchronization words that will cause "in-synchronization" declared configured from more
3-50
L64724 Registers
information, Section 6.3, "Reed-Solomon Deinterleaver Synchronization," page 6-8.
SSA[1:0] Number Sync Words Found Acquire
SST[1:0]
Synchronization Status, Tracking Mode [1:0] second synchronization module (after Viterbi decoder before Deinterleaver module) allows two, three, four, five misdetected synchronization words before L64724 declares loss synchronization. more information, Section 6.3, "Reed-Solomon Deinterleaver Synchronization."
SST[1:0] Number Missed Sync Words Until Loss Lock
3.6.16 Output Control (Group
This register used configure Channel output data path. Read/Write:
Reserved
Reserved
Reserved
Reserved [7:6] Reserved bits must cleared proper operation. Descrambler Output Format Writing sets descrambler output mode shown following table.
Group Configuration Registers
3-51
CO[7:0] Channel Data Serial Channel Output Mode Parallel Channel Output Mode
Serial Channel Output mode, decoded data presented CO[0] every PCLK cycle. Parallel Channel Output mode, byte decoded data presented CO[7:0] channel data every eight PCLK cycles. When serial mode selected, BCLKOUT forced LOW. When SPI_On_Off (Group ignored. Reserved Reserved [4:0] Reserved bits must proper operation.
3.6.17 Reset (Group
Read/Write: Write Only
PLL_RESET
Writing value generates internal reset pulse module. L64724 ignores data D[7:0] during write this register. should reset module before operating Reset register (APR18) cannot read.
3.6.18 Decimation Filter Control (Group
Read/Write:
DF_SELECT[2:0] DF_RATIO[2:0]
DF_GAIN[1:0]
Decimation Filter Control register sets clock parameters related Demodulator module carrier synchronization logic.
3-52
L64724 Registers
DF_SELECT[2:0] Decimation Filter Select [7:5] Program DF_SELECT[2:0] field select four filters contained decimation filter module bypass decimation filter.
DF_SELECT[2:0] Filter Filter (bypass) Filter Filter Filter Filter
DF_GAIN[1:0] Decimation Filter Gain [4:3] table below indicates gain decimation filter.
DF_GAIN[1:0] Gain Factor
DF_RATIO[2:0] Decimation Filter Ratio [2:0] Program DF_RATIO[2:0] field amount decimation. value indicates ratio outgoing incoming samples decimation filter. more information Section 5.4, "Decimation Filters," page 5-4.
DF_RATIO[2:0] Decimation Ratio 1/16
Group Configuration Registers
3-53
3.6.19 Clock Loop Control (Group
Clock Loop Control register sets matched filter roll-off factor, used Demodulator Module PLL. register also contains power down control bit. Read/Write:
Reserved Reserved MF_20_35
Reserved
Reserved [7:5] These Reserved bits must cleared proper operation. Power Down When modules except asynchronous microprocessor interface turned minimize power consumption. data processing occurs during power down. When clear elements operate. should apply reset pulse after change from (wake-up) before start processing data.
Definition Normal Operation Device Power Down Mode
Reserved
Reserved [3:1] These Reserved bits must cleared proper operation. Matched Filter Roll-Off Factor MF_20_35 bit, when selects roll-off factor 0.35 matched filter accordance with specifications. When MF_20_35 0.20 rolloff factor selected systems.
MF_20_35 Matched Filter Roll-Off Factor 0.20 0.35
MF_20_35
3-54
L64724 Registers
3.6.20 Clock Divider (Group
This register used division ratio sampling clock. Read/Write:
CLK_DIV1[4:0]
PCLK_INV PLL_BP LCLK_OFF
PCLK_INV
PCLK Inversion When PCLK_INV clock signal generated internally available PCLK pin. When PCLK_INV polarity PCLK output waveform inverted. Bypass When PLL_BP internal module used generate clock ADC, Demodulator, modules. When module bypassed PCLK signal generated dividing frequency value CLK_DIV1. details, Chapter LCLK LCLK_OFF bit, when turns LCLK signal. When LCLK_OFF LCLK signal turned Input Division Factor [4:0] When module bypassed (PLL_BP CLK_DIV1[4:0] field sets input division factor clock signal supplied L64724 pin. CLK_DIV1[4:0] bits used when PLL_BP
PLL_BP
LCLK_OFF
CLK_DIV1
Group Configuration Registers
3-55
3.6.21 Clock Divider (Group
This register used division ratio generation LCLK. Read/Write:
Reserved CLK_DIV2[7::0] CLK_DIV2[12:8]
DC_Offset_On_ Off[1:0]
DC_Offset_On_Off Offset Off[15:14] DC_Offset_On_Off[1:0] bits control offset circuit shown following table.
DC_Offset_ On_Off[1] DC_Offset_ On_Off[0] Definition DC_Offset DC_Offset Noise Feedback DC_Offset Noise Feedback
Reserved
Reserved Reserved must always cleared produces random results when read.
CLK_DIV2
Input Division Factor LCLK [7:0], [12:8] frequency output signal LCLK determined value CLK_DIV2[12:0] follows: LCLK CLK/CLK_DIV2[12:0].
3.6.22 Power Reference Level (Group
Read/Write:
PWR_REF[7:0]
3-56
L64724 Registers
This register sets reference power level analog-to-digital converter. details setting this register, Section 5.8.1, "ADC Range Power Reference," page 5-20. PWR_REF[7:0] positive, unsigned number.
3.6.23 Power Estimation Bandwidth Offset (Group
This register used enable internal offset compensation signals sets power estimation bandwidth. Read/Write:
Reserved INT_
PWR_BW[1:0]
Reserved
Reserved [7:3] Reserved bits must always cleared will produce random results when read. Internal Offset Compensation INT_DC enable internal offset compensation signals output matched filter.
INT_DC Definition Disabled Enabled
INT_DC
PWR_BW
Power Estimation Bandwidth Program PWR_BW[1:0] bits power estimation bandwidth. more information Section 5.8.2, "Power Control Loop," page 5-21.
PWR_BW[1:0] Symbol Rate (MHz) 20-45 10-20 5-10
[1:0]
Group Configuration Registers
3-57
3.6.24 Scale Factor DEMI DEMQ Outputs (Group
Read/Write:
SCALE[7:0]
Program SCALE[7:0] bits scale factor DEMI DEMQ outputs from Demodulator decoder. relationship between SCALE[7:0] PWR_REF[7:0], Section 5.9, "Output Control," page 5-22. SCALE[7:0] positive, unsigned number.
3.6.25 Estimator Threshold (Group
Read/Write:
SNR_THS[7:0]
this register value that phase detector's signal noise ratio (SNR) comparator uses threshold when deciding which gain value use. details, Figure Section 5.7.2, "Carrier Phase Tracking," page 5-16. SNR_THS[7:0] unsigned number.
3.6.26 Carrier Loop Filter Parameters (Group
Read/Write:
CAR_LAMBDA_SEL[3:0]
CAR_MU_SEL[3:0]
CAR_LAMBDA_SEL[3:0] Carrier Loop Lambda [7:4] Program CAR_LAMBDA_SEL[3:0] field with values that parameters carrier recovery loop. details, Section 5.7.2.2, "Loop Characteristics," page 5-17.
3-58
L64724 Registers
CAR_MU_SEL[3:0] Carrier Loop [3:0] Program CAR_MU_SEL[3:0] field with values that parameters carrier recovery loop. details, Section 5.7.2.2, "Loop Characteristics," page 5-17.
3.6.27 Carrier Phase Lock Detector Threshold (Group
Read/Write:
CAR_LC_THSL[7:0]
CAR_LC_THSL[7:0] determines threshold Carrier Phase Lock Detector. details, Section 5.7.1.5, "Phase Lock Detection," page 5-15. CAR_LC_THSL[7:0] unsigned number.
3.6.28 Reserved (Group
Read/Write:
Reserved
Reserved
Reserved [7:0] Reserved bits Logic internal only must cleared
3.6.29 Bit/Byte Error Correct Mode Control (Group
following register controls Reed Solomon Bit/Byte error count selection mode selection. Read/Write:
SPI_On_Off Reserved
Bit/Byte_ Errorout_Invert Select
Group Configuration Registers
3-59
Bit/Byte_Select Reed Solomon Bit/Byte Select Bit/Byte_Select controls Reed-Solomon Corrected Error Count/Byte Error Count selection. When reading group registers (APR0 APR1) yields Reed-Solomon byte error count. When reading group registers (APR0 APR1) yields Reed-Solomon error count, which multiplied eight. Errorout_Invert ERROROUT Signal Invert When Error_Out_Invert ERROROUT signal polarity inverted from active-LOW activeHIGH. SPI_On_Off
When SPI_On_Off mode When mode off. When setting this bit, APR63 should also appropriately select mode. L64724 Revision only supports modes specification, mode Reserved These bits reserved. [4:0]
Note:
Reserved
3.6.30 Carrier Synchronizer Sweep Rate (Group
Read/Write:
CAR_SWR[15:8] CAR_SWR[7:0]
CAR_SWR
Carrier Synchronizer Sweep Rate [15:0] CAR_SWR[15:0] value determines Carrier Synchronizer sweep rate. details, Section 5.7.1.3, "Frequency Sweep Rate," page 5-14. CAR_SWR[15:0] signed, two's complement number.
3-60
L64724 Registers
3.6.31 Carrier Synchronizer Sweep Upper Limit (Group
values CAR_USWL[15:0] register upper limits frequency sweep. details, Section 5.7.1.1, "Frequency Sweep Limits," page 5-13. CAR_USWL[15:0] two's-complement number. Read/Write:
CAR_USWL[15:8] CAR_USWL[7:0]
CAR_USWL
Carrier Sweep Upper Sweep Limit [15:0] Program CAR_USWL[15:0] bits upper limit frequency sweep.
3.6.32 Carrier Synchronizer Sweep Lower Limit (Group
Program CAR_LSWL[15:0] register lower limit frequency sweep. details, Section 5.7.1.4, "CAR_SWR," page 5-14. CAR_LSWL[15:0] two's-complement number. Read/Write:
CAR_LSWL[15:8] CAR_LSWL[7:0]
CAR_LSWL
Carrier Sweep Lower Sweep Limit [15:0] Program CAR_LSWL[15:0] bits lower limit frequency sweep.
Group Configuration Registers
3-61
3.6.33 Carrier Loop Filter Initialization (Group
Program CAR_LF_INIT[23:0] bits with values that content Carrier Loop Filter Accumulator. details, Section 5.7.2.2, "Loop Characteristics," page 5-17. Read/Write:
APRS CAR_LF_INIT[23:16] CAR_LF_INIT[15:8] CAR_LF_INIT[7:0]
CAR_LF_INIT Carrier Loop Filter Init [23:0] Program CAR_LF_INIT[23:0] bits value accumulator loop filter carrier recovery loop. CAR_LF_INIT[23:0] two's-complement number.
3.6.34 Carrier Loop Configuration Register (Group
This resister contains various control bits that configure Carrier Loop Synchronizer Loop logic. more information, Section 5.7, "Carrier Recovery Loop," page 5-12. Read/Write:
CAR_SWP_ SWAP CAR_ERROR_ SWAP CAR_AUTO_ CAR_PED_ CAR_OPEN CAR_SW
Reserved
CAR_SWP_SWAP Swap Carrier Sweep Direction CAR_SWP_SWAP control whether Carrier acquisition frequency sweep direction normal reversed. should toggled whenever carrier
3-62
L64724 Registers
sweep reaches limit without achieving carrier lock, when constellation locked degrees.
CAR_SWP_SWAP Sweep Operation Increasing Frequency Decreasing Frequency
CAR_ERROR_SWAP Swap Carrier Error Detector CAR_ERROR_SWAP control polarity Carrier Loop Error detector (NDAML, DDML). When polarity detector output inverted.
CAR_ERROR_SWAP Error Detector Output Normal Inverted
CAR_AUTO_SWP Automatic Carrier Sweep Control CAR_AUTO_SWP enable automatic control carrier sweep mechanism. When control sweep handled internally. Section 5.6, "Timing Clock Recovery," page 5-8, more information carrier sweep.
CAR_AUTO_SWP Sweep Mode Manual sweep control user Automatic internal sweep control
Reserved
Reserved [4:3] Reserved bits reserved internal only. They should always cleared produce random results when read.
CAR_PED_SEL Carrier Phase Error Detector Select Program CAR_PED_SEL select which phase error estimator will used carrier phase tracking.
Group Configuration Registers
3-63
details, Section 5.7.2, "Carrier Phase Tracking," page 5-16, Table 5.4.
CAR_PED_SEL Estimator Selected Decision Directed Maximum Likelihood (DDML) Nondata Aided Maximum Likelihood (NDAML)
CAR_OPEN
Carrier Loop Open CAR_OPEN disable carrier loop (the carrier loop integrator maintains current value). When CAR_OPEN carrier loop operates normally.
CAR_OPEN Definition Enable Carrier Loop Disable Carrier Loop
CAR_SW
Sweep Enable Carrier Loop CAR_SW enable carrier acquisition sweep generator. more information Section 5.7.1, "Carrier Acquisition," page 5-13.
CAR_SW Definition Sweep mechanism Sweep mechanism
3.6.35 Clock Loop Terms (Group
Read/Write:
CLK_LAMBDA_SEL[7:4] CLK_MU_SEL[3:0]
CLK_LAMBDA_SEL Clock Loop Lambda [7:4] Program CLK_LAMBDA_SEL[7:4] bits with values that parameters clock recovery loop. details, Section 5.6.1, "Clock Acquisition Tracking Modes," page 5-9.
3-64
L64724 Registers
CLK_MU_SEL Clock Loop [3:0] Program CLK_MU_SEL[3:0] bits with values that parameters clock recovery loop. details, Section 5.6.1, "Clock Acquisition Tracking Modes," page 5-9.
3.6.36 Clock Synchronizer Sweep Rate (Group
This register determines Clock Synchronizer sweep rate. Read/Write:
CLK_SWR[15:8] CLK_SWR[7:0]
CLK_SWR
Clock Synchronizer Sweep Rate [15:0] CLK_SWR[15:0] signed, two's complement number. details, Section 5.6.1.2, "Timing Loop Sweep Equations Timing Loop Bias," page 5-11.
3.6.37 Clock Synchronizer Sweep Upper Limit (Group
Read/Write:
CLK_USWL[15:8] CLK_USWL[7:0]
CLK_USWL
Clock Sweep Upper Sweep Limit [15:0] Program CLK_USWL[15:0] register upper limit frequency sweep. details, Section 5.6.1.2, "Timing Loop Sweep Equations Timing Loop Bias," page 5-11, CLK_USWL[15:0] two's complement number.
Group Configuration Registers
3-65
3.6.38 Clock Synchronizer Sweep Lower Limit (Group
Read/Write:
CLK_LSWL[15:8] CLK_LSWL[7:0]
CLK_LSWL
Clock Sweep Lower Sweep Limit [15:0] Program CLK_LSWL[15:0] register lower limit frequency sweep. details, Section 5.6.1.1, "Timing Loop Sweep Limits," page 5-10. CLK_LSWL[15:0] two's-complement number.
3.6.39 Clock Loop Bias (Group
Program CLK_BIAS[30:0] register with values that parameters clock recovery loop. details, Section 5.6.1.2, "Timing Loop Sweep Equations Timing Loop Bias," page 5-11. Read/Write:
Reserved CLK_BIAS[30:24] CLK_BIAS[23:16] CLK_BIAS[15:8] CLK_BIAS[7:0]
Reserved
Reserved must Reserved normal operation.
3-66
L64724 Registers
CLK_BIAS
Clock Loop Bias [30:0] Program CLK_BIAS registers value bias parameter within clock recovery loop.
3.6.40 Clock Loop Configuration Register (Group
This register contains various control bits that used configure Clock Synchronizer Loop logic. Read/Write:
CLK_ AUTO_ AGC_CLK_
CLK_SWP_ CLK_ERROR SWAP _SWAP
Reserved
CLK_OPEN
CLK_SW
CLK_SWP_SWAP Swap Clock Sweep Direction CLK_SWP_SWAP control whether Clock acquisition frequency sweep direction normal reversed. should toggled whenever clock sweep reaches limit without achieving clock lock.
CLK_SWP_SWAP Sweep Operation Increasing Frequency Decreasing Frequency
CLK_ERROR_SWAP Swap Timing Error Detector CLK_ERROR_SWAP control polarity timing error detector. When polarity detector output inverted.
CLK_ERROR_ SWAP Error Detector Output Normal Inverted
CLK_AUTO_SWP Automatic Timing Sweep Control CLK_AUTO_SWP enable automatic control timing sweep mechanism. When control sweep handled internally.
Group Configuration Registers
3-67
Section 5.6, "Timing Clock Recovery," page 5-8, more information timing sweep.
CLK_AUTO_SWP Sweep Mode Manual sweep control user Automatic internal sweep control
This must proper operation.
AGC_CLK_SEL Sigma-Delta Clocking Select When AGC_CLK_SEL Sigma-Delta module integrates value continuously sampling frequency over samples. When SigmaDelta module operates valid symbols only.
AGC_CLK_SEL Clocking Select valid symbols only samples used Sigma-Delta
Reserved CLK_OPEN
Reserved This reserved.
Clock Loop Open CLK_OPEN disable clock loop. clock loop integrator maintains current value. When clock loop operates normally.
CLK_OPEN Definition Enable Clock Loop Disable Clock Loop
CLK_SW
Sweep Enable Clock Loop CLK_SW enable Clock acquisition sweep generator.
CLK_SW Definition Sweep mechanism Sweep mechanism
3-68
L64724 Registers
3.6.41 Demodulator Configuration Register (Group
This register contains control bits that configure L64724 Demodulator logic. Read/Write:
SNR_EST PWRP_TRI ADC_PD FP_LOCK_ PWRP Reserved CLK_ ALPHA_
SNR_EST
Estimator On/Off SNR_EST enables disables Estimator circuit.
SNR_EST Estimator
PWRP_TRI
PWRP Signal 3-state Control PWRP_TRI bit, when set, forces PWRP output 3-state condition.
PWRP_TRI PWRP Output Normal 3-State
ADC_PD
Converter Power-Down ADC_PD bit, when turns Converter module minimize power consumption. data processing occur during power-down. Converter operates full power when ADC_PD When Converter experiences wakeup (ADC_PD changes from apply reset pulse L64724 before processing data.
ACD_PD Definition operates normally Power Down Mode
Group Configuration Registers
3-69
FP_LOCK_LEN Frequency/Phase Lock Detector Length FP_LOCK_LEN operates conjunction with Carrier Threshold field (Group phase lock detector estimation period. details, Section 5.7.1.5, "Phase Lock Detection," page 5-15.
FP_LOCK_LEN Estimation Period Normal (long) Short
PWRP
PWRP Signal Invert PWRP bit, when inverts polarity signal output PWRP pin.
PWRP PWRP Output Normal Inverted
Reserved
Reserved [2:1] must Reserved bits normal operation.
CLK_ALPHA_SEL Clock Loop Coefficient CLK_ALPHA_SEL configures coefficient value (ALPHA) Interpolator structure within clock recovery loop. When value ALPHA 0.43. When value ALPHA 0.5. default value CLK_ALPHA_SEL
3.6.42 External Output Control Bits Reset Register (Group
This register contains control bits XCTR_OUT[3:0] external output pins bits that reset demodulator circuitry. Read/Write:
ADC_BP OB_2C XCTR[3:0] DEMOD_ FEC_
3-70
L64724 Registers
ADC_BP
Converter Bypass When ADC_BP dual Converter modules bypassed digital input signals channel accepted IBYPASS[5:0] QBYPASS[5:0] buses, respectively. When Converters active analog input signals accepted IVIN QVIN pins. Input Format Select When OB_2C input signal demodulator module assumed offset-binary format. When signal assumed two's-complement format. operation using Converters (ADC_BP OB_2C should cleared When modules bypassed (ADC_BP either format acceptable through IBYPASS QBYPASS buses.
OB_2C Definition Offset-Binary Format 2's-Complement Format
OB_2C
XCTR
External Control Output Bits [5:2] value XCTR[3:0] field appears external output pins XCTR_OUT[3:0] when Serial_A (APR When Serial_A internal microcontroller determines values external output pins XCTR_OUT[3:0]. more information Section 5.10, "External Controls," page 5-23, Appendix "Programming Serializer,".
XCTR[3:0] Definition Corresponding output Corresponding output
DEMOD_RST QPSK Demodulator Software Reset L64724 resets internal datapath control modules QPSK Demodulator when DEMOD_RST L64724 also resets demodulator processing unit state machines their initial states.The Decoder module affected. does need cleared back complete reset. L64724 issues single reset pulse each
Group Configuration Registers
3-71
time microprocessor writes this bit. additional details, Section 3.10, "Reset Effect Register Bits," page 3-82.
DEMOD_RESET Definition Reset L64724 Issues Demodulator Reset
FEC_RST
Decoder Software Reset L64724 resets internal datapath control modules portion device when FEC_RST L64724 also resets processing unit state machines their initial states. demodulator module affected. does need cleared back complete reset. L64724 issues single reset pulse each time microprocessor writes this bit. additional details, Section 3.10, "Reset Effect Register Bits."
FEC_RST Definition Reset L64724 Issues Reset
3.6.43 Reserved (Group
Read/Write:
Reserved 0x00 Reserved 0x00 Reserved 0x14
Reset Value: 0x00
Reserved
Reserved Bits [7:0] Reserved bits internal only. bits return value 0x00 when read, returns value 0x14 when read.
3-72
L64724 Registers
3.6.44 Serial Interface Tuner, Data, Control (Group
These registers used communicate serial tuner using XCTR[3:0] output pins. Both host microprocessor on-chip microcontroller write registers. SCLK serial protocol generated on-chip dividing crystal clock (assumed MHz) SCLK signal output XCTR[1] pin. SDATA serial protocol output XCTR[0] pin. When Serial_C 3-wire protocol used transmit serialized data XCTR[2:0], with XCTR[2] acting ENABLE signal. Read/Write:
Serial_B Reserved
Serial Transmission Start Data, TXSD[6:0] Serial Transmission Data, STXD[7:0] Serial Transmission Data, TXED[7:0] Serial_C[1:0] SPI_M[3:0]
Serial_A
TXSD[6:0]
Serial Transmission Start Data [7:1] When register written, on-chip serializer module generates START condition SCLK (XCTR[1]) SDATA (XCTR[0]) pins, serializes transmits address TXSD[7:1] (MSB first), appends indicate write cycle tuner. Serial Transmission Data [7:0] When register written, STXD[7:0] data serialized transmitted next data byte. first sent serially MSB, This register buffered serializer that second 8-bit data byte loaded into STXD before waiting previous byte serialized. detailed description cycles, please refer Appendix "Programming Serializer."
STXD[7:0]
Group Configuration Registers
3-73
TXED[7:0]
Serial Transmission Data [7:0] When register written, TXED[7:0] bits serialized transmitted last serial data byte, STOP condition generated SDATA (XCTR[0]) SCLK (XCTR[1]) pins. Serial Transmission Control Serial_B indicates whether host microprocessor on-chip microcontroller controls XCTR[2:0] pins. When on-chip microcontroller controls XCTR[2:0] pins. When host microprocessor controls pins.
Serial_B
Serial_C[1:0] Serial Transmission Control [6:5] Serial_C[1:0] bits control whether data serialized with serial 2-wire 3-wire protocol. These bits used serialize data, shown table below:
Serial_C[1:0] Selected Function Serial 2-Wire Interface 3-wire interface, ENABLE HIGH valid data 3-wire interface, ENABLE HIGH clock cycle start data transfer 3-wire interface, ENABLE HIGH clock cycle data transfer
more details, Appendix "Programming Serializer." SPI_M[3:0] SPI_M [4:1] SPI_M[3:0] bits contain value denominator Viterbi Code rate. Serial Transmission Control Serial_A indicates whether output pins XCTR_OUT[3:0] controlled directly programmed Group register "External Control Output Bits," XCTR[3:0], serializer module with data from TXSD, STXD, TXED registers. When (the default), indicates that control dictated XCTR[3:0].
Serial_A
3-74
L64724 Registers
3.6.45 FMODE, SPI_CLK_AND, SPI_MODE_A_B, SPI_N (Group
This register used configure Interface.
FMODE SPI_N[3:0]
SPI_CLK SPI_MODE Reserved _AND _A_B
FMODE
BCLK Format When FMODE descrambler byte clock signal (BCLKOUT) enabled during Reed-Solomon check bytes. When BCLKOUT signal disabled during check bytes. Enabling setting SPI_On_Off automatically takes care setting proper values FMODE bit. SPI_On_Off located Group
SPI_CLK_AND SPI_Clock AND'ing When SPI_CLK_AND Byte Clock logically AND'ed with DVALIDOUT signal. SPI_MODE_A_B Mode Select5 SPI_MODE_A_B selects between Mode (similar specification mode Mode (similar specification mode When Mode selected. When Mode selected. Reserved Reserved This reserved Logic must cleared SPI_N [3:0] SPI_N[3:0] bits contain numerator Viterbi Code rate.
SPI_N
Group Configuration Registers
3-75
3.6.46 SPI_Gain[9:0] (Group
This register sets gain Byte Clock generation loop. Read/Write:
Reserved SPI_Gain[7:0]
SPI_Gain[9:8]
SPI_Gain[9:0] value used control loop gain Byte Clock generation module. Typical values high data rates decimation decimation decimation decimation decimation
3.6.47 SPI_Bias (Group
This register sets bias Byte Clock generation loop. Read/Write:
Reserved SPI_Bias[22:16] SPI_Bias[15:8] SPI_Bias[7:0]
This 23-bit value determined Equation 3.9. value must rounded closest integer.
Equation symbol Bias sample
terms Equation have following meanings: Bias SPI_Bias[22:0] Viterbi Code Rate
3-76
L64724 Registers
Fsymbol Symbol Clock Frequency Fsample Sampling Clock Frequency
3.6.48 Timing Lock Detector Threshold (Group
This register contains control bits Timing Lock Detector Threshold. Read/Write:
Timing Lock Detector Threshold, CLK_LC_THSL[7:0]
CLK_LC_THSL[7:0] Timing Lock Detector Threshold Select [7:0] Program these bits select threshold values timing lock detector mechanism.
Group Self-Tuning Microcontroller Registers
Group contains memory space instructions configuration microprogrammed controller (uC). registers accessed through chip-level serial parallel interface1. Note: These registers write-only internal scratch registers visible host microprocessor.
Table shows addresses fields Group registers. Table
(Sheet Unused
Group Register
uC-Instruction [7:0] Instruction [11:8]
Serial Mode recommended interface mode. Logic does recommend parallel mode designs.
Group Self-Tuning Microcontroller Registers
3-77
Table
Group Register (Cont.)
uC-Instruction [7:0] Unused Instruction [11:8]
uC-Instruction [7:0] Unused Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Configuration [4:0] Arbitration_On Reset_ Mode Micro_ Enable Instruction [11:8]
(Sheet
3-78
L64724 Registers
3.7.1 Microcontroller Instructions (Group 511)
first locations group (0-511) occupied microinstructions Demodulator Control Module. Each 12-bit microinstruction distributed over address locations APR. Read/Write:
Microinstruction [7:0] Unused Microinstruction [11:8]
value ranges from 510.
3.7.2 Reserved (Group 519)
reserved Logic internal only. They must cleared Read/Write:
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reset Value: 0x00
Group Self-Tuning Microcontroller Registers
3-79
3.7.3 Microcontrol Enable Configuration (Group 5:APR 520)
contains enable configuration mechanism microcontroller. Read/Write:
Configuration [4:0]
Reset Value: 0x00
Arbitration Reset_ Mode Micro_ Enable
Configuration[4:0] Microcontrol Configuration [7:3] When particular Configuration field used enable disable, respectively, portions flow chart implemented microcontroller program. Section B.1, "L64724 QPSK Demodulator Acquisition Debugging Tips," page B-1, sample flowchart. Arbitration_On Arbitration When Arbitration_On host microprocessor accesses L64724 status configuration registers (Groups allowed while on-chip running. host thus disable writing into Micro_Enable while running. When Arbitration_On host accesses L64724 status configuration registers (Groups allowed while on-chip running. host then disable when running only writing into Group (A[2:0] 0b111). more details, Group registers description. Reset_Mode Reset Mode When Reset_Mode does reset instruction pointer when disabled while running, resumes instruction last decoding when enabled again. When resets instruction pointer being disabled. also resets internal scratch registers, uC_status registers (Group 21), associated interrupt bits.
3-80
L64724 Registers
Micro_Enable Demodulator Micro Control Enable When Micro_Enable L64724 internal microcontroller demodulator section starts operation. this mode, demodulator acquires synchronization carrier symbol timing without intervention external microprocessor. When microcontrol unit demodulator disabled acquisition operation must performed through serial parallel microprocessor interface1.
Micro_ Enable Definition Microcontroller disabled. Acquisition through Microprocessor Interface. Microcontroller enabled. Automatic internal demodulator acquisition.
Group Reserved (Internal Only) Group Arbiter Control Register
Group contains memory space internal control microcontroller/microprocessor arbitration module. contains Microcontroller Disable mechanism. Read/Write: Reset Value: 0x00
Microcontroller Disable
Microcontroller Disable [7:0] write operation Group disables on-chip microcontroller when running. Group write used microcontroller/host microprocessor arbitration register disabled, which means that host
Serial Mode recommended interface mode. Logic does recommend parallel mode designs.
Group Reserved (Internal Only)
3-81
microprocessor write operations Groups disallowed while on-chip microcontroller enabled. operation described follows: power-up Micro_Enable (Group 520) cleared external microprocessor loads register Groups then loads micro instructions into Group this point, Micro_Enable Group Configuration[2] cleared (indicating that arbitration turned off), further host microprocessor writes Configuration Micro_Enable bits Group allowed while on-chip microcontroller running. host microprocessor then shuts on-chip microcontroller writing Group Configuration[2] (indicating that arbitration turned on), further host microprocessor writes register groups allowed, host microprocessor disable microcontroller writing either Group Micro_Enable Group
3.10 Reset Effect Register Bits
This section contains summary table showing various reset operations affect L64724 register bits. following reset operation abbreviations appear table:
HR-Hardware reset through L64724 RESET pin. SF-Software reset module (FEC_RST bit). SD-Software reset Demodulator module (DEMOD_RST bit) UR-Microcontroller reset based falling edge Micro_Enable (Group 520), with Reset Mode (Group 520) cleared NR-Not affected reset.
3-82
L64724 Registers
Table
Group
Reset
Name APR0 APR1 SMR/
(all bits) (all bits) (all bits) (all bits) (all bits) (all bits)
STATUS
bits Used (all bits)
7-10 (Sheet Used
Used Used Used
(all bits) (all bits) (all bits)
(all bits) (all bits)
Reset Effect Register Bits
3-83
Table
Group
Reset (Cont.)
Name CONFIG MICRO CONTROL
0-69 512-
(all bits) (all bits) (all bits) Group access
(Sheet
Reserved (all bits)
3.11 Internal Data Path Reset Effects
Hardware reset through L64724 RESET (HR) Software reset Demodulator module (SD) affect Demodulator. Software reset module (SR) affect module.
3-84
L64724 Registers
Chapter Channel Interfaces Data Control
L64724 interface supports independent interfaces incoming channel data decoded output data. Both interfaces used simultaneously. input interface transfers data from external device L64724's internal module. output interface transfers data from L64724 next processing device, typically MPEG-2 transport demultiplexer such Logic L64007/8. This chapter contains following sections:
Section 4.1, "Data Control Clocking Schemes" Section 4.2, "PLL Clock Generation" Se
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