L64724 designed specifically meet needs satellite broadcast digital co

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L64724 Satellite Receiver
L64724 designed specifically meet needs satellite broadcast digital compliant with European digital video broadcast (DVB-S) standard technical specifications systems. block diagram L64724 shown Figure Figure L64724 Block Diagram
Control Carrier Loop Control Channel Input from Satellite Dual Interpolator/Decimation Filter Timing Loop Control
BPSK/QPSK Demodulator
DEMI Matched Filter Output Control DEMQ
Microcontroller Data Address External Microcontroller Interface Internal Microcontroller Interface
Microcontroller Data Address
Channel Output (MPEG-2 Transport Stream)
Descrambler
ReedSolomon Decoder
Convolutional Deinterleaver
ReedSolomon Syncronizer
Viterbi Decoder
Decoder Pipeline
Viterbi Syncronizer
MD94.345
June 1999
Copyright 1995-1997 Logic Corporation. rights reserved.
L64724 contains following main blocks:
BPSK/QPSK demodulator Concatenated forward error correction (FEC) decoder
BPSK/QPSK module performs binary quadrature phase-shift keying (BPSK/QPSK) demodulation, method extracting digital signal from phase-modulated analog signal. concatenated decoder complete concatenated decoder that uses Viterbi inner code Reed-Solomon outer code. decoding pipeline also contains necessary synchronization, deinterleaving, scrambling functions complete decoding solution. L64724 provides maximum integration flexibility system designers minimum cost. contains on-chip dual 6-bit analog-todigital converter (ADC) well on-chip microcontroller. microcontroller controls tuner well acquisition tracking, which eliminates interaction from main CPU, freeing perform other functions. number external components required build system minimal because both clock carrier loops incorporated into device.
L64724 Satellite Receiver
Features Benefits
Supports sys- Fast channel switching mode.
specifications.
BPSK/QPSK demodulation
rates from Mbaud.
Power estimation
control.
Matched filter (square root
Programmable Viterbi decoder
module rates 1/2, 2/3, 3/4, 5/6, 6/7, 7/8. (204/188), (146/130) Reed-Solomon decoder. Auto-synchronization Viterbi decoder. Programmable synchronization deinterleaver, Reed-Solomon decoder, descrambler. performance measurements.
raised cosine filter with roll factor 35%). Anti-aliasing filters operation from MBaud with- switching external filters need low-pass filters.
On-chip digital clock synchronization.
On-chip digital carrier synchronization, featuring frequency sweep capability signal acquisition.
error monitoring channel Depth convolutional
deinterleaver.
Auto-acquisition demodulator Serial host interface compatible
with Logic Serial Control mode tuner control interface. through on-chip microcontroller. Power-down mode. (PLL) clock synthesis, allowing fundamental mode crystal. tion tracking, eliminating microcontroller interaction, simplifying software development.
Integrated phase-locked loop On-chip microcontrolled acquisi-
Dual ADC.
Typical Application
typical application L64724 satellite digital reception
accordance with 1110 Rev. standard. Figure shows
L64724 Satellite Receiver
L64724 satellite receiver implemented typical satellite receiver set-top decoder box. Also shown other Logic products:
L64008 MPEG-2 Transport Demultiplexer L64005 MPEG-2 Audio/Video Decoder
Figure Set-Top Decoder Block Diagram
Optional DRAM DRAM 256K (required)
XTAL
Satellite
TUNER
L64724
[7:0]
L64008
High-Speed Port
Serial Control
Microcontroller Data Address
VCXO
Audio Oversampling Clock
NTSC S-Video L-Speaker R-Speaker
NTSC Encoder
CCIR601VIDEO
L64005 Audio
PCM-AUDIO 64/16
Audio/Video
SDRAM 256K
L64724 Satellite Receiver
Signal Descriptions
This section provides detailed information L64724 signals. Figure shows logic symbol L64724. Figure L64724 Logic Symbol
IVIN Channel Interface QVIN IBYPASS[5:0] QBYPASS[5:0]
BCLKOUT CO[7:0] DVALIDOUT ERROROUT Channel Data Output Interface
Channel Clock Interface
XOIN XOOUT
FSTARTOUT IBIAS QBIAS
LCLK PCLK Interface PLLAGND PLLVDD PLLVSS
ADCVSSI/Q ADCVDDI/Q ADCVREFI/Q ADCVREFNI/Q
Interface
A[2:0]
IDDTN Control Signals Interface RESET XCTR_IN XCTR_OUT[3:0]
D[7:0] DTACK/WAIT DTACK/POL HOST_MODE Microcontroller Interface
AGC/Clock Control Interface
PWRP
READ/WRITE
L64724 Satellite Receiver
shown Figure L64724 following major interfaces:
Channel Channel Clock Channel Data Output AGC/Clock Control Microcontroller Control Signal
following signal descriptions listed according major interface groups.
Channel Interface
Channel Interface input path L64724 satellite receiver. signals IVIN QVIN streams from satellite tuner circuit. signal strobes data signals. IBYPASS[5:0] Channel Data Input IBYPASS[5:0] signals form Digital Received Channel data input bus, which supplies Stream L64724 when bypassed. IVIN Channel Data Input IVIN signal Analog Received Channel data input bus, which supplies Stream L64724.
QBYPASS[5:0] Channel Data Input QBYPASS[5:0] signals form Digital Received Channel data input bus, which supplies Stream L64724 when bypassed. QVIN Channel Data Input QVIN signal Analog Received Channel data input bus, which supplies Stream L64724.
L64724 Satellite Receiver
Channel Clock Interface
IVIN/QVIN Input Clock Input positive, edge-triggered clock that strobes input data L64724. Crystal Oscillator Input XOIN used crystal oscillator external reference clock input. Crystal Oscillator Output XOOUT crystal oscillator output pin.
XOIN
XOOUT
Channel Data Output Interface
Channel Data Output Interface output path from L64724. typically connected input transport demultiplexer set-top decoder application. BCLKOUT Byte Clock Output BCLKOUT output signal strobe that indicates valid data bytes CO[7:0] when L64724 Parallel Channel Output mode. BCLKOUT signal cycles once every valid output data byte used transport demultiplexer latch output data from L64724 BCLKOUT rate. BCLKOUT signal must disregarded Serial Channel Output mode. Channel Data Output CO[7:0] signals form decoded output data port. Parallel Channel Output mode (OF=1, Group L64724 outputs channel data 8-bit wide parallel data CO[7:0] signals. Serial Channel Output mode L64724 outputs channel data serial data CO[0]. latched every clock cycle. chronological ordering Serial Channel output mode oldest, newest. Channel Output Enable Input When asserted, signal enables ERROROUT, CO[7:0], DVALIDOUT, BCLKOUT, FSTARTOUT pins. Operation receiver continues regardless state signal.
CO[7:0]
L64724 Satellite Receiver
DVALIDOUT
Valid Data Output DVALIDOUT signal indicates that CO[7:0] signals contain corrected channel data. data valid output when DVALIDOUT signal asserted. DVALIDOUT asserted during propagated check bytes. DVALIDOUT signal deasserted after FEC_RST register (Group one. Error Detection Flag Output L64724 asserts ERROROUT flag uncorrectable errors. L64724 asserts ERROROUT signal beginning frame that contains uncorrectable error, deasserts frame error condition removed. ERROROUT exactly aligned with output data stream.The ERROROUT signal asserted after FEC_RST register (Group one.
ERROROUT
FSTARTOUT Frame Start Output Output L64724 asserts FSTARTOUT signal during first every frame with valid data Serial Channel Output mode during first byte Parallel Channel Output mode. FSTARTOUT valid only when DVALIDOUT signal asserted. FSTARTOUT signal deasserted after FEC_RST register (Group one.
Interface
circuitry multiplies Channel Clock Recovery circuit Serial Clock (SCLK) signal (XCTR_OUT[0] functions SCLK) times symbol rate, based Viterbi code rate. LCLK Decimated Clock Output Output L64724's internal clock generation module generates LCLK signal. LCLK derived from dividing value CLK_DIV2 parameter. Input Input signal input internal voltagecontrolled oscillator. normally connected output external timing circuit.
L64724 Satellite Receiver
PCLK
Clock Output Output L64724's internal clock synthesis module generates PCLK signal. signal drives PLL. clock synthesis module configured generate PCLK rate that appropriate data rates. Analog Ground Input PLLAGND analog ground module normally connected system ground plane. Power Input PLLVDD power supply module normally connected system power (VDD) plane. Ground Input PLLVSS ground module normally connected system ground plane.
PLLAGND
PLLVDD
PLLVSS
Interface
module converts incoming IVIN QVIN signals into internal 6-bit digital representation processing. following pins support module. ADCVDDI/Q Power Input ADCVDDI/Q analog power supply pins module normally connected system power (VDD) plane.
ADCVREFI/Q Reference Input ADCVREFI/Q connected reference voltage. ADCVREFNI/Q Reference Input ADCVREFNI/Q connected reference voltage. ADCVSSI/Q Analog Ground Input ADCVSSI/Q analog ground pins module normally connected system ground plane.
L64724 Satellite Receiver
IBIAS
Current Bias Input IBIAS supplies current bias channel ADC. Current Bias Input QBIAS supplies current bias channel ADC.
QBIAS
AGC/Clock Control Interface
PWRP Power Control Output PWRP signal positive modulated output used power control drive external passive filter that feeds gain control stage.
Microcontroller Interface
Microcontroller Interface connects L64724 microcontroller, such 64008. A[2:0] Address Input A[2:0] signals form receiver address bus. address used conjunction with eight-bit data D[7:0], read/write strobe (READ/WRITE), chip select strobe (CS), address strobe (AS) select, read, write internal registers. Address Strobe Input signal active-LOW address strobe input. L64724 latches address A[2:0] signals falling edge signal. Chip Select Input signal active-LOW chip select strobe input. During read cycle, microcontroller must assert (LOW) access on-chip data registers. controller must latch data from L64724 rising edge During write cycle, must asserted prior data being valid from controller L64724. After data minimum setup time, microcontroller deasserts (HIGH) strobe data. There minimum write time allow internal synchronization. Setup hold times measured with respect falling edge
L64724 Satellite Receiver
D[7:0]
Data Bidirectional D[7:0] signals form bidirectional data bus, which input data when data written L64724 chip data output when L64724 chip read Parallel Host Interface mode (the HOST_MODE HIGH). data lines 3-stated when being read written. When Serial Host Interface mode selected (the HOST_MODE LOW), D[0] used Serial Clock (SCLK) signal synchronize transfer serial data Serial Data (SDATA) (XCTR_OUT[1] functions SDATA), D[1] used SDATA signal transfer serial data, D[2] D[3] used LSBs L64724 slave address. Data Acknowledge/Wait Polarity Input DTACK/POL signal determines polarity Data Acknowledge/Wait Signal. When DTACK/POL signal LOW, DTACK/WAIT active-LOW. When DTACK/POL HIGH, DTACK/WAIT active-HIGH.
DTACK/POL
DTACK/WAIT Data Acknowledge/Wait Output DTACK/WAIT signal output indicating that transaction D[7:0] been completed. active-LOW when DTACK/POL active-HIGH when DTACK/POL HIGH. HOST_MODE Serial Parallel Host Interface Select Input When HOST_MODE signal deasserted, selects Serial Host Interface mode. When asserted, selects Parallel Host Interface mode. Interrupt Output L64724 asserts signal (LOW) when internal unmasked interrupt flag set. signal remains asserted long interrupt condition persists interrupt flag masked.
READ/WRITE Read/Write Strobe Input microcontroller asserts READ/WRITE signal (HIGH) indicate that current transaction read from L64724, deasserts (LOW) indicate that write L64724.
L64724 Satellite Receiver
Control Signal Interface
Control Signal Interface signals control operation L64724. They associated with particular interface. IDDTN Test Input IDDTN Logic internal test pin. IDDTN normal operation. Reset Input RESET active-HIGH signal that resets internal data paths. RESET timing asynchronous device clocks does affect configuration registers. performs same operation reset bits specified Group register. Control Input Input XCTR_IN external input control pin. sensed reading corresponding Group register.
RESET
XCTR_IN
XCTR_OUT[3] Control Output/Sync Status Flag Output XCTR_OUT[3] indicates synchronization status three synchronization modules L64724 (Viterbi decoder sync, DI/RS sync, descrambler sync) XCTR.3 field Group three synchronization outputs, XCTR_OUT[3] signal, when asserted, indicates that synchronization been achieved chosen sync module. When deasserted, signal indicates out-of-synchronization condition. XCTR_OUT[2:0] Control Output Pins Output XCTR_OUT[2:0] pins external output control pins. They programming corresponding bits Group register. XCTR_OUT[0] function Serial Clock (SCLK) signal, XCTR_OUT[1] function Serial Data (SDATA) signal.
L64724 Satellite Receiver
Specifications
This section contains electrical, timing, mechanical specifications L64724 satellite receiver.
Electrical Specifications
This section contains electrical parameters L64724. Table lists absolute maximum values. Exceeding values listed cause damage L64724. Table gives recommended operating supply voltage temperature. Table shows capacitance, Table gives characteristics, Table summarizes pins. Table L64724 Absolute Maximum Rating (Referenced VSS)
Symbol Parameter TSTG Supply Voltage LVTTL Input Voltage Compatible Input Voltage Input Current Storage Temperature Range (Plastic) Limits1 -0.3 +3.9 -1.0 -1.0 +125 Units
Note that ratings this table those beyond which permanent device damage likely occur. These values should used limits normal device operation.
Table L64724 Recommended Operating Conditions
Symbol Parameter Supply Voltage Operating Ambient Temperature Range (Commercial) Case Temperature Limits1 Units
+3.14 3.47
normal device operation, adhere limits this table. Sustained operation device conditions exceeding these values, even they within absolute maximum rating limits, result permanent device damage impaired device reliability. Device functionality stated limits guaranteed conditions exceed recommended operating conditions.
L64724 Satellite Receiver
Table L64724 Capacitance
Symbol COUT Parameter1 Input Capacitance Output Capacitance Units
Measurement conditions clock frequency MHz.
Table
Symbol
Characteristics L64724
Parameter1 Supply Voltage Input Voltage Input Voltage HIGH LVTTL Com/Ind/Mil Temp Range compatible Condition2 Max, -1.0, -2.0, -4.0, -6.0, -8.0, -12.0 1.0, 2.0, 4.0, 6.0, 8.0, 12.0 Max, VOUT MHz, Units
IIPU IIPD
Switching Threshold Input Current Leakage Input Current Leakage w/Pull-up Input Current Leakage w/Pull-down Output Voltage HIGH Output Voltage 3-state Output Leakage Current Quiescent Supply Current Dynamic Supply Current
-215 -384 -215 -384
L64724 Satellite Receiver
Table L64724 Description Summary
Mnemonic A[2:0] ADCVDDI/Q ADCVREFI/Q ADCVREFNI/Q ADCVSSI/Q BCLKOUT CO[7:0] D[7:0] DTACK/POL DTACK/WAIT DVALIDOUT ERROROUT FSTARTOUT HOST_MODE IBIAS IBYPASS[5:0] IDDTN IVIN LCLK (Sheet Description Address Power Reference Input Reference Ground Address Strobe Byte Clock Clock Channel Data Channel Output Enable Chip Select Data Type Input with pull-down1 Input Input Input Input Input with pull-up1 3-State Output Input 3-State Output Input with pull-up1 Input with pull-up1 Bidirectional
Data Acknowledge/Wait Polarity Input Data Acknowledge/Wait Valid Data Output Error Detection Flag Frame Start Output Interface Select Current Bias Channel Data Test Interrupt Channel Data Decimated Clock Output Open Drain Output 3-State Output 3-State Output 3-State Output Input Input Inputs Input Open Drain Output Input Output
L64724 Satellite Receiver
Table L64724 Description Summary (Cont.)
Mnemonic PCLK PLLAGND PLLVDD PLLVSS PWRP QBIAS QBYPASS[5:0] QVIN READ/WRITE RESET XCTR_IN XCTR_OUT[3: XOIN XOOUT (Sheet pull-up pull-down signals active edge timing. Description Loop Filter Clock Output Analog Ground Power Ground Power Control Current Bias Channel Data Channel Data Read/Write Strobe Reset Control Input Control Output Pins Crystal Oscillator Crystal Oscillator Digital Power Supply Digital Ground Type Input Output Input Input Input Open Drain Output Input Inputs Input Input with pull-up1 Input CMOS Input CMOS Outputs CMOS Input CMOS Output Input Input
This section includes timing information L64724. During testing, HIGH inputs driven inputs driven transitions between HIGH, LOW, invalid states, timing measurements made shown Figure
L64724 Satellite Receiver
Figure Test Load Waveform Standard Outputs
Test Point
Output
MD94.361
3-state outputs, timing measurements made from point which output turns OFF. output when voltage greater than less than output when voltage less than greater than shown Figure Figure Test Load Waveforms 3-State Outputs
Test Point Iref
Output
Vref Vref
Iref
MD94.362
Synchronous timing shown Figure Synchronous inputs must have setup hold relationship with respect clock signal that samples them. Synchronous outputs have delay from clock edge that asserts them.
L64724 Satellite Receiver
Figure L64724 Synchronous Timing
PCLK INPUTS OUTPUTS
reset pulse requirements shown Figure Figure L64724 RESET Timing Diagram
RESET
Figure shows relationship L64724 3-state signals signal. Figure L64724 3-State Delay Timing
FSTARTOUT ERROROUT DVALIDOUT BCLKOUT
Figure Figure show L64724 read write cycle timing requirements.
L64724 Satellite Receiver
Figure L64724 Receiver Read Cycle
D[7:0] A[2:0] Valid
Valid
READ/WRITE DTACK/ WAIT
Figure L64724 Receiver Write Cycle
D[7:0] Valid
A[2:0]
Valid
READ/WRITE DTACK/ WAIT
L64724 Satellite Receiver
numbers first column Table (microcontroller disabled) Table (microcontroller enabled) refer timing parameters shown preceding figures. parameters timing tables apply capacitive load Table L64724 Timing Parameters with Microcontroller Disabled
Parameter tCYCLE tPWH tPWL tRWH TDLY tSURCS tSUA tHLDA tDCSDTL tHLDD tCYCLE_CS tHLDRCS Description Clock Cycle PCLK Clock Pulse Width HIGH Clock Pulse Width Input Setup Time Input Hold Output Delay from Reset Pulse Width HIGH Wake-Up Time Delay from READ/WRITE Setup before A[2:0] Setup before A[2:0] Hold after Data Valid DTACK/WAIT Write Data Hold after HIGH Minimum Width READ/WRITE Hold after HIGH Groups 0,1,4 Groups Groups 0,1,4 Groups Groups 0,1,4 Groups Register Groups 11.1 15.0 45.0 15.0 15.0 Units cycles cycles cycles cycles cycles
(Sheet
L64724 Satellite Receiver
Table L64724 Timing Parameters with Microcontroller Disabled (Cont.)
Parameter tWRREC tDCSDTH tDELD tDELLZ tSUD tHLDW tDELDTL tRDREC Description Write Recovery Time HIGH DTACK/WAIT HIGH Data Valid HIGH Data 3-State Data Setup before Change Hold after DTACK/WAIT Read Recovery Time Groups 0,1,4 Groups Groups 0,1,4 Groups Groups 0,1,4 Groups Register Groups Groups 0,1,4 Groups Groups 0,1,4 Groups Groups 0,1,4 Groups Groups 0,1,4 Groups 30.0 17.0 17.0 14.0 15.0 10.0 30.0 28.0 28.0 30.0 24.0 Units cycles cycles cycles cycles cycles
(Sheet
L64724 Satellite Receiver
Table L64724 Timing Parameters with Microcontroller Enabled
Parameter tCYCLE tPWH tPWL tRWH TDLY tSURCS tSUA tHLDA tDCSDTL tHLDD tCYCLE_CS tHLDRCS tWRREC tDCSDTH Description Clock Cycle PCLK Clock Pulse Width HIGH Clock Pulse Width Input Setup Time Input Hold Output Delay from Reset Pulse Width HIGH Wake-Up Time Delay from READ/WRITE Setup before A[2:0] Setup before A[2:0] Hold after Data Valid DTACK/WAIT Write Data Hold after HIGH Minimum Width READ/WRITE Hold after HIGH Write Recovery Time HIGH DTACK/WAIT HIGH Register Groups 11.1 15.0 Groups Groups Groups Groups Groups 15.0 Units cycles cycles
cycle cycles 28.0 cycles Cycles
(Sheet
L64724 Satellite Receiver
Table L64724 Timing Parameters with Microcontroller Enabled (Cont.)
Parameter tDELD tDELLZ tSUD tHLDW tDELDTL tRDREC Description Data Valid HIGH Data 3-State Data Setup before Change Hold after DTACK/WAIT Read Recovery Time Register Groups 24.0 Units cycles cycles cycles cycles
Groups 17.0 Groups 14.0 15.0 Groups Groups Groups
(Sheet
Pinout, Package, Ordering Information
L64724 available 100-pin PQFP 80-pin TQFP package. Table lists ordering information L64724. Table L64724 Ordering Information
Clock Frequency (MHz)
Order Number L64724QC L64724BC
Package Type 100-pin PQFP 80-pin TQFP
Operating Range Commercial Commercial
tables figures that follow provide pinout mechanical drawing each package.
Pinouts
Figure gives pinout 100-pin PQFP L64724 package, Figure gives 80-pin TQFP pinout. 80-pin version offers serial, rather than parallel, microcontroller interface makes internal module instead external ADCs.
L64724 Satellite Receiver
A[0] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] XCTR_OUT[0] XCTR_OUT[1] XCTR_OUT[2] XCTR_OUT[3] PWRP
XCTR_IN DTACK/POL QBIAS ADCVREFQ ADCVREFQN ADCVDDQ ADCVSSQ QVIN IBIAS ADCVREFI ADCVREFIN ADCVDDI ADCVSSI IVIN HOST_MODE IBYPASS[5] IBYPASS[4] IBYPASS[3] IBYPASS[2] IBYPASS[1] IBYPASS[0] QBYPASS[5] QBYPASS[4] QBYPASS[3]
Figure 100-Pin PQFP Pinout
97.L64724.VD
PLLVSS PLLAGND PLLVDD PCLK LCLK A[1] A[2] READ/WRITE DTACK/WAIT CO[0] CO[1] CO[2] CO[3] CO[4] CO[5] CO[6]
L64724 Satellite Receiver
View
CO[7] XOOUT XOIN BCLKOUT DVALIDOUT FSTARTOUT ERROROUT RESET IDDTN QBYPASS[0] QBYPASS[1] QBYPASS[2]
Figure 80-Pin TQFP Pinout
PLLVSS PLLAGND PLLVDD PCLK LCLK CO[0] CO[1] CO[2] CO[3] CO[4] D[3] D[2] D[1] D[0] XCTR_OUT[0] XCTR_OUT[1] XCTR_OUT[2] XCTR_OUT[3] PWRP XCTR_IN
View
IDDTN RESET ERROROUT FSTARTOUT DVALIDOUT BCLKOUT XOIN XOOUT CO[7] CO[6] CO[5]
97.L64724.UJ
ADCVREFQ
ADCVDDQ ADCVSSQ QVIN IBIAS ADCVREFI
ADCVREFQN
L64724 Satellite Receiver
ADCVREFIN
ADCVDDI ADCVSSI IVIN
QBIAS
Mechanical Drawings
Figure mechanical drawing 100-pin PQFP L64724 package, Figure shows 80-pin TQFP drawing. Figure 100-pin PQFP (UD) Mechanical Drawing
board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
MD97.UD-1
L64724 Satellite Receiver
Figure (Cont.) 100-pin PQFP (UD) Mechanical Drawing
board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
MD97.UD-2
L64724 Satellite Receiver
Figure 80-pin TQFP (UJ) Mechanical Drawing
board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
MD97.UJ-1
L64724 Satellite Receiver
Figure (Cont.) 80-pin TQFP (UJ) Mechanical Drawing
board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
MD97.UJ-2
L64724 Satellite Receiver
Notes
L64724 Satellite Receiver
Notes
L64724 Satellite Receiver
Sales Offices Design Resource Centers
Logic Corporation Corporate Headquarters Tel: 408.433.8000 Fax: 408.433.8989 NORTH AMERICA
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Sales Offices with
Design Resource Centers
receive product literature, call 1-800-574-4286 (U.S. Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, Europe) Department JDS; visit http://www.lsilogic.com
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This document preliminary. such, contains data derived from functional simulations performance estimates. Logic verified functional descriptions electrical mechanical specifications using production parts. Logic logo design registered trademark Logic Corporation. other brand product names trademarks their respective companies.
Printed Order I15022 Doc. DB08-000056-00
Logic Corporation reserves right make changes products services herein time without notice. Logic does assume responsibility liability arising application product service described herein, except expressly agreed writing Logic; does purchase, lease, product service from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties.

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