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L64704 Satellite Decoder
Order Number I14010.A
Document DB14-000026-01, Second Edition (May 1997) This document describes Revision Logic Corporation's L64704 Satellite Decoder will remain official reference source revisions this product until rescinded update. receive product literature, call 1.800.574.4286 (U.S. Canada); +32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, Europe) Department JDS; visit http://www.lsilogic.com. Logic Corporation reserves right make changes products herein time without notice. Logic does assume responsibility liability arising application product described herein, except expressly agreed writing Logic; does purchase product from Logic convey license under patent rights, copyrights, trademark rights, other intellectual property rights Logic third parties. Copyright 1995, 1996, 1997 Logic Corporation. rights reserved. TRADEMARK ACKNOWLEDGMENT Logic logo design registered trademark Logic Corporation. other brand product names trademarks their respective companies.
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Contents
Chapter
Introduction General Description Typical Application Features Summary L64704 Signal Definitions Channel Interface Channel Clock Recovery Channel Data Output Interface Phase-Locked Loop Interface Carrier Synchronizer Loop Controls Microcontroller Interface Control Signals L64704 Registers L64704 Register Overview 3.1.1 Parallel Host Mode Register Operations 3.1.2 Programming Using Serial Interface Reset Affects Registers Group Address Pointer Register Group Registers 3.4.1 System Mode Register (SMR) 3.4.2 System Status Register (STS) Group Registers 3.5.1 Group Corrected Error Count 3.5.2 Group Uncorrected Error Count 3.5.3 Group Viterbi Error Count 3.5.4 Group Control Input 3.5.5 Group Measured Frequency
Chapter
Chapter
3-10 3-11 3-11 3-16 3-20 3-21 3-21 3-22 3-22 3-23
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Group Loop Voltage Meter 3-23 Group Carrier Synchronization Status 3-23 3.5.8 Group Readback 3-25 3.5.9 Group Readback 3-26 Group Registers 3-26 3.6.1 Group Parameter 3-28 3.6.2 Group Parameter 3-28 3.6.3 Group Parameter Demodulator Symbol Select 3-29 3.6.4 Group Parameter Transport Viterbi Code Rate Select 3-30 3.6.5 Group Viterbi Data Count 3-31 3.6.6 Group Viterbi Data Count 3-31 3.6.7 Group Viterbi Maximum Error Count 3-32 3.6.8 Group Synchronization Word 3-32 3.6.9 Group Monitor Mismatching Bits Sync Tracking Mode 3-33 3.6.10 Group Synchronization States BCLKOUT Format 3-34 3.6.11 Group Output Control 3-36 3.6.12 Group Reset 3-37 3.6.13 Group Clock Loop Control 3-37 3.6.14 Group Clock Loop Control 3-39 3.6.15 Group Nominal Frequency Clock Input 3-40 3.6.16 Group Clock Ratio 3-40 3.6.17 Group Power Reference Level 3-41 3.6.18 Group Power Estimation Bandwidth Offset 3-41 3.6.19 Group Scale Factor DEMI DEMQ Outputs 3-42 3.6.20 Group Estimator Threshold 3-42 3.6.21 Group Carrier Loop Offset Compensation Value 3-42 3.6.22 Group Carrier Frequency Reference Period 3-42 3.6.23 Group Carrier Loop Filter Gain Terms) 3-43
3.5.6 3.5.7
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
3.6.24 3.6.25 3.6.26 3.6.27 3.6.28 3.6.29 3.6.30 3.6.31
Group Carrier Lock Detector Threshold Group Carrier Synchronizer Sweep Rate Group Carrier Synchronizer Sweep Upper Limit Group Carrier Synchronizer Sweep Lower Limit Group Carrier Loop Configuration Register Group Group Decoder Configuration Register Group External Output Control Bits Reset Register
3-43 3-44 3-44 3-45 3-45 3-48 3-49 3-50
Chapter
Channel Interfaces Data Control Data Control Clocking Schemes Channel Data Input Interface Channel Data Output Interface Clock Generation Data Path Output Configurations 4.5.1 Descrambler Output 4.5.2 Synchronization Stage Output 4.5.3 Reed-Solomon Decoder Output 4.5.4 Deinterleaver Output 4.5.5 Synchronization Stage Output 4.5.6 Viterbi Decoder Output 4.5.7 Viterbi Depuncture/Synchronization Output 4.5.8 QPSK Demodulator Output Demodulator Module Functional Description Overview Offset Compensation Coupling Output Decimation Filters Matched Filter Channel Clock Recovery 5.5.1 Input Decimation 5.5.2 Clock Acquisition Tracking Modes
4-12 4-13 4-15 4-15 4-16 4-17 4-17 4-18 4-19
Chapter
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
5.5.3 Output Symbol Clock 5.5.4 Constraints Data Rates 5.5.5 Examples Carrier Synchronizer 5.6.1 Carrier Acquisition 5.6.2 Carrier Phase Tracking Automatic Gain Control (AGC) 5.7.1 Range Power Reference 5.7.2 Power Control Loop 5.7.3 Power Level Output Control Other Functions 5.9.1 Carrier Loop Offset Compensation 5.9.2 External Controls 5.9.3 Hi-Z Mode Functional Outputs
5-10 5-12 5-17 5-22 5-22 5-23 5-24 5-24 5-26 5-26 5-27 5-27
Chapter
Decoding Pipeline Synchronization Synchronization Scheme Viterbi Decoder Synchronization Reed-Solomon Deinterleaver Synchronization Descrambler Synchronization Decoder Pipeline Viterbi Decoder Module 7.1.1 Features 7.1.2 Code Performance 7.1.3 Punctured Codes 7.1.4 Viterbi Error Rate Monitor Deinterleaver Module 7.2.1 Deinterleaver Block Diagram 7.2.2 Deinterleaver Output Reed-Solomon Decoder 7.3.1 Terms Concepts 7.3.2 Features 7.3.3 Performance Analysis Descrambler Module Architecture Operation Module Software Reset
6-10
Chapter
7-11 7-12 7-13 7-14 7-14 7-17 7-18 7-19 7-21
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Chapter
L64704 Specifications Electrical Requirements Timing L64704 Packaging Programming L64704 Using Serial Protocol Serial Protocol Overview Programming Slave Address Using Serial Interface Write Cycle Using Serial Interface Read Cycle Using Serial Interface
8-10
Appendix
Appendix
L64704 Application Notes Controlling L64704's BPSK/QPSK Demodulator Loops L64704 QPSK Demodulator Debugging Tips B.2.1 Loop B.2.2 Clock Loop B.2.3 Carrier Loop B.2.4 QPSK Demodulator Debugging Summary QPSK Demodulator Configuration Example B.3.1 Programming L64704 QPSK Demodulator Registers B.3.2 Values Clock Loop B-16 B.3.3 Gains B-16 B.3.4 Data Rates B-17 Configuring L64704 Decoder Specifications B-18 Oscillator Cells Introduction Requirements Oscillator Circuits Crystal Oscillator Higher Frequency Oscillators Frequency Oscillation (kHz Range) Customer Feedback
Appendix
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Figures
4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19
L64704 Block Diagram Set-Top Decoder Block Diagram Typical Receiver Block Diagram with L64704 Concatenated Decoding Performance L64704 L64704 Logic Diagram Register-File Structure Issue Hard Reset Initialize APR0 APR1 Zero Write Locations Group Read Back Group L64704 Clocking: Internal L64704 Clocking: External Code Rate System Code Rate System; Different OCLK Reference Channel Data Input OCLK Reference Channel Data Output FSTARTOUT Related Symbols Clock Generation Clock Synthesis L64704 Functional Blocks Decoding Pipeline Descrambler Serial Output Waveforms Descrambler Parallel Output Format Synchronization Stage Output Waveforms Reed-Solomon Decoder Output Waveforms Deinterleaver Output Waveforms Synchronization Stage Output Waveforms Viterbi Decoder Output Waveforms Viterbi Depuncture/Synchronization Output Waveforms QPSK Demodulator Output Waveforms Demodulator Module Associated Circuitry Input Quantization with Coupling Clock Recovery Loop Spectrum Oversampled Signal Carrier Recovery Loop Frequency Sweeping Threshold ES/No Carrier Loop Filter Schematic
4-13 4-14 4-14 4-15 4-16 4-16 4-17 4-18 4-18 4-19 5-11 5-13 5-17 5-18
viii
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
5.10 5.11 5.12 5.13 6.10 6.11 7.10 7.11 7.12 7.13
Slope Using CAR_PED Outputs Pattern Range Loop Control Pattern Soft Decision Thresholds Synchronization Module Viterbi Decoder Synchronization Phase Rotation Synchronization Reed-Solomon, Deinterleaver Synchronization Synchronization, Tracking, Loss Sync Missed Sync Words Minimum Maximum Number States Acquisition Phase Minimum Maximum Number States Tracking Phase MPEG-2 Transport Packet L64704 Transport Packet Descrambler Synchronization Synchronization, Tracking, Loss Synchronization Descrambler Block Diagram Viterbi Decoder Core Code Performance Viterbi Decoder Puncturing Depuncturing Block Diagram Puncture Pattern Different Code Rates Block Diagram Viterbi Error Detection Circuit Percent Channel Symbol Errors Eb/No Rate Code Percent Channel Symbol Errors Eb/No Rate Code Percent Channel Symbol Errors Eb/No Rate Code Percent Channel Symbol Errors Eb/No Rate Code Percent Channel Symbol Errors Eb/No Rate Code Interleaving/Deinterleaving Operation Block Diagram Deinterleaver Core Deinterleaver Output Example
5-19 5-21 5-22 5-23 5-25 6-10 6-11 7-10 7-10 7-11 7-12 7-13 7-13
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
7.14 7.15 7.16 7.17 7.18 7.19 7.20 Tables
Code Word Structure Forward Error Correction Data Path 122-bit Burst Example (255, 255-2T) Code Performance Descrambler Block Diagram 15-bit Shift Register Inverting Sync Words Descrambler Test Load Waveform Standard Outputs Test Load Waveform 3-State Outputs L64704 Synchronous Timing L64704 RESET Timing Diagram L64704 3-State Delay Timing L64704 Decoder Read Cycle L64704 Decoder Write Cycle L64704 100-Pin PQFP Pinout 100-Pin PQFP Mechanical Drawing (Sheet Quick Overview Serial Quick Overview Serial Write/Read Cycles General Call Structure Burst Write Slave (Master-Transmitter, Slave-Receiver) Single Read From Slave Flow Diagram Microcontroller Monitoring External Loops Loop Control Simplest Oscillator Pierce Crystal Oscillator Circuit Third Overtone (Higher Frequency) Oscillator Circuit Frequency Range (kHz) Oscillator Circuit Register Overview Register Group Register Group Register CLK/SCLK Ratio Values PLL_S, PLL_N, PLL_T, PLL_M Function CLK_DR CLK_RATIO Natural Frequency Function Example Data Rates
7-15 7-15 7-17 7-19 7-20 7-20 7-21 8-11 8-12 3-20 3-27 5-10
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
B.10
Example Data Rates Narrow Filter PWR_BW Function Symbol Rate Stage Synchronization Values Puncture Patterns Various Code Rates Viterbi Threshold Values L64704 Absolute Maximum Rating (Referenced VSS) L64704 Recommended Operating Conditions L64704 Capacitance L64704 Characteristics L64704 Description Summary L64704 Timing Parameters L64704 Ordering Information Alphabetical List 100-pin PQFP QPSK Demodulator Loop Registers PWR_LVL Register Setting QPSK Demodulator Loop Registers Fixed Rate Operation (Damping Group Decoder Register Group Decoder Registers Actual Configuration Typical Clock Carrier Gains CAR_PED Output Pins Group Register Group Actual Configuration Component Values Circuit Shown Figure Component Values Circuit Shown Figure Component Values Circuit Shown Figure
5-10 5-23 8-10 8-10 B-11 B-14 B-15 B-16 B-17 B-18 B-19
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Contents
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Preface
This book primary reference technical manual L64704 Satellite Decoder. contains complete functional description L64704 includes complete physical electrical specifications L64704.
Audience
This document assumes that have some familiarity with digital satellite communications, microprocessors, related support devices. people benefit from this book are:
Engineers managers evaluating L64704 possible
digital satellite receiver
Engineers designing L64704 into digital satellite
receiver
Organization
This document following chapters appendix:
Chapter Introduction, defines general characteristics
capabilities L64704 Satellite Decoder.
Chapter L64704 Signal Definitions, describes characteristics
L64704 signals that used interface with external channel microcontroller.
Chapter L64704 Registers, provides summary registers
tables L64704.
Chapter Channel Interfaces Data Control, discusses
Input Channel Output Channel interfaces circuitry that supports them.
Chapter Demodulator Module Functional Description,
describes operation Demodulator portion Satellite Decoder.
Preface
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
xiii
Chapter Decoding Pipeline Synchronization, discusses
mechanism synchronizing internal decoder modules incoming data stream.
Chapter Decoder Pipeline, describes various logic
modules that comprise decoding pipeline.
Chapter L64704 Specifications, describes electrical
mechanical characteristics L64704.
Appendix Programming L64704 Using Serial
Protocol, provides information program L64704 using Serial protocol.
Appendix L64704 Application Notes, provides application information connecting L64704 your circuit programming meet your needs.
Appendix Oscillator Cells, provides information oscillator
cells used L64704, design oscillators using these cells.
Related Publications
L64002 MPEG-2 Audio/Video Decoder Technical Manual, Order l14011 L64007 MPEG-2, TSAT Transport Demultiplexer Technical Manual, Document DB14-000007-00 European Digital Video Broadcast Standard, DTVB 1110 Revision This document available from:
Project Office European Broadcasting Union Ancienne Route, Grand Saconnex Geneva, Switzerland
Preface
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Conventions Used This Manual
first time word phrase defined this manual, italicized. following signal naming conventions used throughout this manual:
level-significant signal that true valid when signal
always overbar over name. over name.
edge-significant signal that initiates actions HIGH-to-LOW
transition always overbar word assert means drive signal true active. word deassert means drive signal false inactive. Hexadecimal numbers indicated prefix "0x" before number-for example, 0x32CF. Binary numbers indicated subscripted following number-for example, 0011.0010.1100.11112. Operations registers referred using binary numbers Output signal levels referred designations HIGH LOW. Example: XCTR0 register force XCTR_OUT0 HIGH.
Preface
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Preface
Rev. letter Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
Chapter Introduction
This chapter introduces L64704 Satellite Decoder from Logic. L64704 designed specifically meet needs satellite broadcast digital sections this chapter are:
Section 1.1, "General Description," provides overview architecture L64704 Satellite Decoder.
Section 1.2, "Typical Application," describes L64704 used
typical satellite decoder system.
Section 1.3, "Features Summary," summarizes main features
L64704.
General Description
L64704 Satellite Decoder contains main blocks: BPSK/QPSK Demodulator Concatenated decoder. BPSK/QPSK module performs binary quadrature phase-shift keying (BPSK/QPSK) demodulation, method extracting digital signal from phase-modulated analog signal. BPSK/QPSK module designed specifically satellite broadcast digital receiver, compliant with European digital video broadcast (DVB) standard (DTVB 1110 Rev. Decoder pipeline complete concatenated Forward Error Correction decoder that utilizes Viterbi inner code Reed-Solomon outer code. decoding pipeline also contains necessary synchronization, deinterleaving, scrambling functions complete decoding solution. L64704 compliant with specifications "Baseline Modulation/Channel Coding System" Digital Video Broadcast
(DVB) Association. Logic fabricates L64704 using LCB500K, 3.3-volt, 0.5-micron, HCMOS process technology. L64704 provides maximum integration flexibility system designers minimum cost. number external components required build system minimal; only dual operational amplifier passive resistors capacitors needed implementation clock carrier loop filters. Figure shows block diagram L64704.
Figure L64704 Block Diagram
CLK_VCO Clock Synchronizer Carrier Synchronizer
CAR_VCO
Control
BPSK/QPSK Demodulator
DEMI
2/T, 3/T, Channel Input from Satellite Offset Estimator
Decimation Filter
Matched Filter
Output Control
DEMQ
Microcontroller Data Address External Microcontroller Interface
Microcontroller Data Address
CO[7:0] Channel Output (MPEG-2 Transport Stream)
Descrambler
Reed Solomon Decoder
Convolutional Interleaver/ Deinterleaver
Reed Solomon Syncronizer
Viterbi Decoder
Decoder Pipeline
Viterbi Syncronizer
Introduction
Typical Application
Figure Set-Top Decoder Block Diagram
typical application L64704 satellite digital reception according 1110 Rev. standard. Figure shows L64704 Satellite Decoder typical Satellite Receiver Set-Top Decoder box.
Optional DRAM 256K Figure details [7:0] Tuner L64704
Optional Decryption Engine
Satellite
L64007/ L64008
High-Speed Port
Microcontroller Data Address
VCXO Microcontroller Audio Oversampling Clock NTSC S-Video L-Speaker R-Speaker NTSC Encoder CCIR601 Video L64002/ L64005 Audio Audio PCM-Audio 64/32 Audio/Video
DRAM 256K 256K
Typical Application
Logic offers circuits that make most complex portions logic found Set-Top Decoder box. These circuits include the:
L64704 Satellite Decoder L64007 MPEG-2 Transport Demultiplexer L64002 MPEG-2 Audio/Video Decoder
more information other integrated circuits Set-Top Decoder box, their associated manuals. Figure shows block diagram satellite tuner that includes L64704.
Figure Typical Receiver Block Diagram with L64704
From Channel Output (MPEG-2 Transport Stream)
Gain Control Amplifier
Down Converter
Dual
L64704
Frequency Synthesizer
Loop Filter
Loop Filter
Loop Filter
Microcontroller
receiver block receives microwave channel data from satellite dish, demodulates decodes outputs MPEG-2 transport stream.
Introduction
Features Summary
This section summarizes main features L64704. Subsequent chapters describe these features more detail.
Variable BPSK/QPSK demodulation from 62.5 Mbit/s Matched filter (square root raised cosine filter, roll-off factor 35%) Decimation filters input oversampling ratios 2/T, 3/T, Clock synchronization Carrier synchronization featuring frequency sweep capability
signal acquisition
Power estimation control Internal offset control Programmable Viterbi decoder module rates 1/2, 2/3, 3/4, 5/6, (204/188) Reed-Solomon decoder Auto synchronization Viterbi decoder Programmable synchronization Deinterleaver, Reed-Solomon
Decoder, Descrambler
module flags uncorrectable frames setting ninth
MPEG Transport packet.
Error monitoring channel performance measurements Depth deinterleaver Serial host interface compatible with Logic Serial Control
interface
Power down mode
Figure shows performance graph L64704 Satellite Decoder.
Features Summary
Figure Concatenated Decoding Performance L64704
1.00E-03
1.00E-04
1.00E-05
1.00E-06
1.00E-07 Rate Rate Rate
1.00E-08 1.00E-09
1.00E-10
1.00E-11 1.00E-12 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00
Introduction
Chapter L64704 Signal Definitions
This chapter describes signals that comprise L64704 Satellite Decoder's interface other components. This chapter divided into seven sections that describe various buses:
Section 2.1, "Channel Interface," describes input channel
interface L64704.
Section 2.2, "Channel Clock Recovery," lists signals that make
input channel clock recovery circuitry.
Section 2.3, "Channel Data Output Interface," describes signals
that connect channel data outputs MPEG demultiplexer.
Section 2.4, "Phase-Locked Loop Interface," lists signals that
used connect L64704 external Phase-Locked Loop.
Section 2.5, "Carrier Synchronizer Loop Controls," provides list
signals that used synchronize Down Converter circuitry.
Section 2.6, "Microcontroller Interface," shows signals that
used connect L64704 external microcontroller.
Section 2.7, "Control Signals," describes various signals that
necessary operation L64704, into categories above. Figure shows logic symbol L64704.
Figure L64704 Logic Diagram
BCLKOUT CO[7:0] Channel Interface Section RI[5:0] RQ[5:0] Channel Clock Recovery Section CLKVCOP CLKVCON XOIN XOOUT OCLK Phase-Locked Loop Interface Section PCLK PLLAGND PLLVDD PLLVSS IDDTN Control Signals Section RESET XCTR_IN XCTR_OUT[3:0] A[2:0] D[7:0] DTACK HOST_MODE READ SDATA Microcontroller Interface Section CAR_DCLKP CAR_DCLKN CAR_PED[1:0] CAR_VCO1P CAR_VCO1N CAR_VCO2P CAR_VCO2N PWRP SYNC/SCLK Carrier Synchronization Loop Controls Section DVALIDOUT ERROROUT FSTARTOUT Channel Data Output Section
L64704 Signal Definitions
Channel Interface
Channel Interface input path L64704 Satellite Decoder. signal buses RI[5:0] RQ[5:0] streams from satellite tuner circuit. signal discussed Channel Clock Recovery section used strobe data signals. Channel Interface discussed Section 4.2, "Channel Data Input Interface." RI[5:0] RQ[5:0] Channel Data Received Channel data input bus. Channel Data Received Channel data input bus. Input Input
Channel Clock Recovery
Channel Clock Recovery logic logic that recovers clock Channel Interface. Channel Clock recovery discussed Section 5.5, "Channel Clock Recovery." RI/Q Input Clock Input positive, edge-triggered clock that used strobe input data. used anywhere else L64704, does propagate past Channel Interface.
CLK_VCOP/N Clock Loop Control Output These differential signals Positive Negative Sigma Delta modulated output used control Channel Clock frequency. XOIN Crystal Oscillator Input XOIN crystal oscillator external reference clock input. Crystal Oscillator Output XOOUT crystal oscillator output pin.
XOOUT
Channel Interface
Channel Data Output Interface
Channel Data Output Interface output path from L64704. typically connected input Transport Demultiplexer set-top decoder application. Channel Data Output Interface discussed Section 4.3, "Channel Data Output Interface." BCLKOUT Byte Clock Output BCLKOUT output signal strobe that indicates valid data bytes CO[7:0] when L64704 Parallel Channel Output mode. BCLKOUT signal cycles once every valid output data byte used Transport Demultiplexer latch output data from L64704 BCLKOUT rate (rather than OCLK rate). BCLKOUT must disregarded Serial Channel Output mode. Channel Data Output These signals form decoded output data port. Parallel Channel Output mode Group L64704 outputs channel data 8-bit wide parallel data CO[7:0]. Serial Channel Output mode L64704 outputs channel data serial data CO0. latched every byte clock cycle. chronological ordering Serial Channel output mode oldest, newest. Channel Output Enable Input When asserted, enables CO[7:0], ERROROUT, FSTARTOUT pins. DVALIDOUT unaffected operation decoder continues regardless state this pin. Valid Data Output DVALIDOUT indicates that CO[7:0] contains corrected channel data. data valid output when DVALIDOUT HIGH. DVALIDOUT asserted during propagated check bytes. This after FEC_RST register (Group asserted. Error Detection Flag Output L64704 asserts ERROROUT flag uncorrectable errors. L64704 asserts ERROROUT signal beginning frame that contains uncorrectable error, deasserts
CO[7:0]
DVALIDOUT
ERROROUT
L64704 Signal Definitions
frame error condition removed). ERROROUT exactly aligned with output data stream.This HIGH after FEC_RST register (Group asserted. FSTARTOUT Frame Start Output Output L64704 asserts FSTARTOUT during first every frame with valid data Serial Channel Output mode during first byte Parallel Channel Output mode. FSTARTOUT valid only when DVALIDOUT HIGH. This after FEC_RST register (Group asserted.
Phase-Locked Loop Interface
Phase-Locked Loop (PLL) circuitry multiplies Channel Clock Recovery circuit SCLK signal times symbol rate, based Viterbi code rate. output from (PCLK) brought back into L64704 OCLK clock Decoder logic. discussed Section 4.4, "PLL Clock Generation." Input Input This input internal voltage controlled oscillator. normally connected output external timing circuit. Decoder Clock Input positive edge OCLK positive, edge-triggered clock. L64704 internally processes data (Viterbi decoder, Synchronization, Descrambler, Deinterleaver, Reed-Solomon Decoder) based OCLK. data outputs (DVALIDOUT, ERROROUT, FSTARTOUT, CO[7:0]) referenced OCLK. OCLK independent CLK. Clock Output Output L64704's internal clock synthesis module generates clock signal PCLK. driven SCLK internal signal (QPSK symbol clock). clock synthesis module configured generate PCLK rate that appropriate Viterbi code rates specified under standard. Analog Ground Input Analog ground module. This normally connected system ground plane.
OCLK
PCLK
PLLAGND
Phase-Locked Loop Interface
PLLVDD
Power Input Power supply module. This normally connected system power (VDD) plane. Ground Input Power supply module. This normally connected system ground plane.
PLLVSS
Carrier Synchronizer Loop Controls
Carrier Synchronizer Loop controls used synchronize Down Converter circuitry. Carrier Synchronizer Loop controls discussed Section 5.6, "Carrier Synchronizer." CAR_DCLKP/N Prescaler Input Input CAR_DCLK pins differential inputs prescaled (divided) Carrier clock (typically frequency 32). CAR_PED[1:0] Carrier Phase Error Detector Output These pins 2-bit outputs from Phase Error Detector. CAR_PED outputs carrier loop implementation combination with external digital analog converter. should used when operating rates less than Mbaud. CAR_VCO1P/N Carrier Loop Control Output When CAR_OUT_SEL (Group these pins Positive/Negative modulated outputs that control carrier frequency. CAR_VCO1P/N feed external circuit number output decreases carrier frequency. HIGH output increases carrier frequency. high impedance level maintains carrier frequency. When CAR_OUT_SEL these pins carry CAR_PED.2 CAR_PED.3 signals. CAR_VCO2P/N Carrier Loop Control Output When CAR_OUT_SEL (Group these pins Positive/Negative modulated outputs that control carrier frequency. CAR_VCO2P/N feed external circuit number output decreases carrier frequency.
L64704 Signal Definitions
HIGH output increases carrier frequency. high impedance level maintains carrier frequency. When CAR_OUT_SEL these pins carry CAR_PED.4 CAR_PED.5 signals. PWRP Power Control Output power control signal positive modulated output used power control. This signal drive external passive filter that feeds gain control stage. Synchronization Status Flag Output When SYNC/SCLK (Group SYNC/SCLK indicates synchronization status three synchronization modules L64704 (Viterbi Decoder sync, DI/RS sync, Descrambler sync). When HIGH SYNC/SCLK output indicates synchronization been achieved chosen sync module. When LOW, SYNC/SCLK output indicates outof-synchronization condition. When SYNC/SCLK SYNC/SCLK carries SCLK signal that used clock external during baud rate operation. Section 5.6.2.3, "Low Baud Rate Operation" more information.
SYNC/SCLK
Microcontroller Interface
Microcontroller Interface connects L64704 microcontroller. A[2:0] Address Input A[2:0] comprise decoder address bus. address used conjunction with eight-bit data D[7:0], read/write strobe (READ), chip select strobe (CS), address strobe (AS) select, read write internal registers. Address Strobe Input active-LOW address strobe input. L64704 latches address A[2:0] falling edge Chip Select Input active-LOW chip select strobe input. During read cycle, microcontroller must pull access on-chip data registers. controller should
Microcontroller Interface
latch data from L64704 rising edge During write cycle, must prior data being valid from controller L64704. After data minimum setup time, microcontroller takes HIGH strobe data. There minimum write time allow internal synchronization. Setup hold times measured with respect falling edge D[7:0] Data Bidirectional D[7:0] bidirectional data bus; input data when data written chip data output when chip read Parallel Host Interface mode (HOST_MODE HIGH). data lines 3-stated when being read written. When Serial Host Interface mode selected (HOST_MODE LOW), used Serial Clock signal synchronize transfer serial data SDATA pin. remaining seven bits data function slave address. Data Acknowledge Output Data Acknowledge active-LOW output indicating that transaction D[7:0] been completed.
DTACK
HOST_MODE Serial Parallel Host Interface Select Input When HOST_MODE LOW, selects Serial Host Interface mode; when HIGH, selects Parallel Host Interface mode. Interrupt Output L64704 asserts when internal unmasked interrupt flag set. remains asserted long interrupt condition persists interrupt flag masked. Read/Write Strobe Input microcontroller drives READ HIGH indicate that current transaction read from L64704, indicate that write L64704. Serial Host Interface Data Bidirectional This bidirectional data input output when Serial Host Interface mode selected (HOST_MODE LOW).
READ
SDATA
L64704 Signal Definitions
Control Signals
These signals control operation L64704. They associated with particular interface. IDDTN Test Input IDDTN Logic internal test pin. Connect this normal operation. Reset Input This active-HIGH signal resets internal data paths. Reset timing asynchronous device clocks. Reset does affect configuration registers. performs same operation reset bits specified Section 3.6.31, "Group External Output Control Bits Reset Register." Control Input Input XCTR_IN external input control pin. sensed reading corresponding Group register.
RESET
XCTR_IN
XCTR_OUT[3:0] Control Output Pins Output XCTR_OUT[3:0] pins external output control pins. They programming corresponding bits Group register.
Control Signals
2-10
L64704 Signal Definitions
Chapter L64704 Registers
This chapter discusses L64704 internal registers. also provides description internal memory mapping describes access these registers from system interface. This chapter intended primarily system programmers developing software drivers. This chapter contains following sections:
Section 3.1, "L64704 Register Overview," provides overview
registers contained within L64704.
Section 3.2, "Reset Affects Registers," describes
three separate methods resetting L64704 each method affects registers.
Section 3.3, "Group Address Pointer Register," describes
address Address Pointer Register.
Section 3.4, "Group Registers," provides information
System Mode System Status Registers.
Section 3.5, "Group Registers," describes read
Status Registers.
Section 3.6, "Group Registers" provides information programming using L64704's Configuration Registers. This chapter provides complete information these registers, does provide information program registers specific application. Appendix "L64704 Application Notes applications information.
L64704 Register Overview
L64704 registers memory resources divided into five groups: Group through Group Group contain Address Pointer Register. This pointer used address registers Groups Group addresses System Status Register when read System Mode Register when written. Group contains status counters, Group contains configuration registers (See Table 3.1).
Group Function Address Pointer Register, Address Pointer Register, System Mode/Status Registers Status Registers Configuration Registers Reserved Reserved Reserved Page 3-10 3-10 3-11 3-20 3-26
Table Register Overview
Table shows complete Register L64704 Satellite Decoder.
Table Register Group (Sheet Bit(s) Description Address Pointer Register Address Pointer Register System Status Register [7:0] System Mode Register [7:0] System Status Register [15:8] System Mode Register [15:8] Reed-Solomon Corrected Error Count Reed-Solomon Corrected Error Count Reed-Solomon Uncorrected Error Count Reed-Solomon Uncorrected Error Count Viterbi Error Rate Count Byte Viterbi Error Rate Count High Byte Acronym CEC[7:0] CEC[15:8] UEC[7:0] UEC[15:8] VBERC[7:0] VBERC[15:8] Page 3-10 3-10 3-16 3-11 3-16 3-11 3-21 3-21 3-21 3-21 3-22 3-22
L64704 Registers
Table (Cont.) Register Group Bit(s) (Sheet Description Demodulator Signal Noise Ratio External Control Input Measured Frequency, Upper Bits Measured Frequency, Lower Byte Loop Voltage Meter Carrier Frequency Lock Flag Carrier Phase Lock Flag Clock Frequency Lock Flag Stage Synchronization Flag Stage Synchronization Flag Stage Synchronization Flag Input Readback Input Readback Acronym Demod_SNR XCTR_IN CAR_VCOF[13:8] CAR_VCOF[7:0] PWR_LVL[7:0] CAR_LCF CAR_LC CLK_LCF PLL_N[5:0] PLL_S[5:0] PLL_T[4:0] VCR[2:0] SYNC2_MOD PLL_M[1:0] VMDC1[7:0] VMDC2[7:0] VMDC2[23:16] VMBEC[7:0] Sync[7:0] L[1:0] Page 3-22 3-22 3-22 3-23 3-23 3-23 3-23 3-23 3-23 3-23 3-23 3-25 3-26 3-28 3-28 3-29 3-29 3-29 3-30 3-30 3-30 3-30 3-31 3-31 3-31 3-31 3-32 3-32 3-33 3-33
Phase-Locked Loop Config. Param. Phase-Locked Loop Config. Param. Symbol Format QPSK/BPSK Format Select Phase-Locked Loop Config. Param. Viterbi Code Rate Transport Error Indicator Select Select SYNC Modified Algorithm Frequency Range Module Viterbi Maximum Data Count Viterbi Maximum Data Count Viterbi Maximum Data Count High Viterbi Maximum Error Count Synchronization Word Error Rate Monitor Mismatching Bits, Tracking Mode, Sync2
Viterbi Maximum Data Count Middle VMDC2[15:8]
L64704 Register Overview
Table (Cont.) Register Group Bit(s) (Sheet Description BCLKOUT Format Synchronization Status Select Synchronization States, Tracking Mode Symbol Size Viterbi Bypass Mode Descrambler Output Format Output Selector, OS[2:0] Reset Module SYNC/SCLK Selector Functional Outputs 3-stated CLK_LCF_Suppress Timing Error Detector Clock Outputs Polarity Swap Decimation Filter Select PCLK Bypass Power-Down Reference Period Clock Input Nominal Frequency, Upper Input Nominal Frequency, Lower Input Decimation Factor Inputs Reference Power Level Acronym SSS[1:0] SST[1:0] BPS[2:0] OS[2:0] PLL_RESET SYNC/SCLK F_OUT_HiZ CLK_LCF_ Suppress CLK_VCO_SWAP CLK_DR[1:0] PCLK_BP CLK_RP[3:0] CLK_NF[15:8] CLK_NF[7:0] CLK_RATIO[2:0] PWR_REF[7:0] Page 3-34 3-34 3-34 3-34 3-36 3-36 3-36 3-37 3-37 3-37 3-37 3-37 3-37 3-39 3-39 3-39 3-40 3-40 3-40 3-41 3-41 3-41 3-42 3-42 3-43 3-43 3-43
Synchronization States, Acquisition Mode SSA[1:0]
Internal Offset Compensation INT_DC Signals Power Estimation Bandwidth Estimator Threshold Carrier Loop Offset Comp. Value Reference Period Carrier Frequency (CAR_DCLKP/N) Measurement Gain Carrier Loop Filter Term) Gain Carrier Loop Filter Term) PWR_BW[1:0] SNR_THS[7:0] CAR_RP[3:0] CAR_KP[7:0] CAR_KD[7:0] Scale Factor DEMI DEMQ Outputs SCALE[7:0]
CAR_OFFSET[7:0] 3-42
L64704 Registers
Table (Cont.) Register Group Bit(s) (Sheet Description Threshold Carrier Lock Detector Sweep Rate Carrier Sweep Acronym CAR_THSL[7:0] CAR_SWR[7:0] Page 3-44 3-44 3-44 3-44 3-46 3-46 3-46 3-46 3-46 3-46 3-46 3-46 3-46 3-49 3-50 3-50 3-50 3-50 3-51 3-51 3-51
Upper Sweep Limit Carrier Sweeping, CAR_USWL[13:8] Upper Bits Upper Sweep Limit Carrier Sweeping, CAR_USWL[7:0] Lower Byte Lower Sweep Limit Carrier Sweeping, CAR_LSWL[13:8] Upper Bits Lower Sweep Limit Carrier Sweeping, CAR_LSWL[7:0] Lower Byte Swap Carrier Sweep Direction CAR_VCO Swap Outputs Polarity CAR_SWP_SWP
CAR_VCO_SWAP 3-46
CAR_VCO2N/P Outputs Active 3-state CAR_VCO2N/P CAR_VCO1N/P Outputs Active 3-state CAR_VCO1N/P Carrier Loop Output Selector Carrier Phase Error Detector Select Carrier Loop Open Sweep On/Off Carrier Loop Signal Noise Estimator On/Off Constellation Selector Frequency/Phase Lock Detector Length Input Format Selector External Control Output Bits QPSK Demodulator Software Reset Decoder Software Reset CAR_OUT_SEL CAR_PED_SEL CAR_OPEN CAR_SW SNR_EST CON_SEL FP_LOCK_LEN I_FORMAT XTCR[3:0] DEMOD_RST FEC_RST
L64704 Register Overview
Figure shows simplified diagram L64704's register file.
Figure Register-File Structure
Group APR0 APR1 SMR/STS STATUS CONF REGS RESERVED RESERVED RESERVED
Group Status Counters
Group Configuration Register
reduce number memory locations occupied L64704 microcontroller memory, L64704 uses Address Pointer Register (APR). auto-increment feature that simplifies initialization procedure reduces number memory cycles needed read write registers. address pointer auto-increment feature used whenever access Groups L64704 automatically points next register entry after complete access these groups. When configuring reading configuration groups will find easier initially APR0 APR1 zero auto-increment mechanism step through locations within group. example: access PLL_N configuration register (Group first APR0 APR1 writing zero addresses then A[2:0] 1002. Address A[2:0] selects Group groups. Internally, L64704 8-bit architecture. Most registers eight bits wide, while some either 24-bits wide. registers memory-mapped system with 8-bit resolution. When accessing register that wider than bits, must read write three 8-bit sections: least-significant byte (LSB) middlesignificant byte (MB) most-significant byte (MSB). Each 8-bit section assigned specific address, therefore requires individual memory cycle during programming.
L64704 Registers
3.1.1 Parallel Host Mode Register Operations
L64704 addressable through either serial parallel host interface. interface used depends value HOST_MODE (HIGH: Parallel Host Interface mode, LOW: Serial Host Interface mode) when L64704 reset. mode, however, cannot changed once part operation. This section shows steps required read write L64704's registers when Parallel Host Interface mode. Serial Host Interface mode discussed Section 3.1.2, "Programming Using Serial Interface." following diagrams demonstrate read write operation through parallel microprocessor interface. Note: OCLK must throughout initialization process.
Step Issue hard reset chip (Figure 3.2). Wait tWK, OCLK cycles, before next step.
Figure Issue Hard Reset
OCLK
RESET
Step APR0 APR1 zero writing zero addresses (See Figure 3.3).
Figure Initialize APR0 APR1 Zero
D[7:0] A[2:0] READ DTACK
Step Write Configuration registers Group Start from location zero, auto-increment mechanism advance next location with every low-to-high transition
L64704 Register Overview
Because registers were both initialized zero, first location written zero, second location will one, Figure Figure present first write operations required operations described above.
Figure Write Locations Group
D[7:0] A[2:0] READ DTACK
Step also choose read back L64704's configuration. This demonstrated Figure 3.5. APR0 APR1 zero, discussed Step step through configuration locations. READ signal asserted, auto-increment mechanism selects location then location etc.
Figure Read Back Group
D[7:0] A[2:0] READ DTACK
Data valid period tDELD after goes low.
L64704 Registers
3.1.2 Programming Using Serial Interface
Setting HOST_MODE during reset places L64704 Serial Host Interface mode. When L64704 addressed using serial interface, must first programmed with 7-bit slave address before other read write cycles. Appendix "Programming L64704 Using Serial Protocol, contains detailed description protocol used when programming L64704 Serial Host Interface mode.
Reset Affects Registers
There three separate resets available L64704; hardware RESET pin, DEMOD_RST register FEC_RST register (Group 36). Each affects registers differently:
Toggling hardware RESET resets Group
Group registers. Registers Group unaffected.
Setting DEMOD_RST External Output Control Bits
Reset Register (Group affects only bits Group registers that directly concerned with demodulator circuitry.
Setting FEC_RST External Output Control Bits
Reset Register (Group resets System Mode/Status registers (Group bits Group registers that directly concerned with demodulator circuitry. Registers Group unaffected these reset operations. Group registers appear random immediately after power-up, retain their last known value after three reset operations listed above. following steps should followed when resetting L64704:
Issue active HIGH reset pulse RESET pin. Program Configuration (Group registers their proper values. Issue soft reset setting DEMOD_RST FEC_RST
bits (Group 36). These bits self-resetting, have cleared.
Wait amount specified parameter (see Figure 8.4). Start L64704.
Reset Affects Registers
Group Address Pointer Register
Address Pointer Register (APR) 13-bit register that points registers Groups accessed when A[2:0] =0002 0012. Before accessing register location from Group must initialize with address first register entry that going read write. automatically increments after reading writing byte within Group register (A[2:0] 0102, 0112 1002).
Address Pointer, APR[12:0]
consecutive writes required load complete APR. first write Group load eight LSBs, second Group load five MSBs. read well written. Group Data D[7:0]
Unused APR[12:8]
Group Data D[7:0]
APR[7:0]
unused bits these registers reserved internal test procedures future expansion should always zero. access Group register:
Place address lower byte register that need
address into APR.
Read write lower byte register using Group
register address (0x011) Group register address (0x100).
register 16-bit register, just perform another read write
group register address access second byte. increments automatically. When through, will automatically point next register group.
3-10
L64704 Registers
Group Registers
Group contains 16-bit registers; System Mode Register System Status Register. System Mode Register accessed writing Group address, System Status Register accessed reading Group address. Because L64704 8-bit architecture, each 16-bit register accessed 8-bit registers:
STS[15:8] SMR[15:8] STS[7:0] SMR[7:0]
microcontroller accesses these registers setting A[2:0] 0102. access these registers point during Satellite Decoder operation without interrupting internal processing unit. Note: Phase-Locked Loop must locked status signals valid.
3.4.1 System Mode Register (SMR)
16-bit System Mode Register (SMR) write-only register that allows external microcontroller control L64704. Bits [15:8] register enable interrupts Demodulator bits [7:0] register enable interrupts module. Because arranged 8-bit registers, microcontroller must perform consecutive writes register address. lower eight bits must 0x00 before accessing SMR. eight LSBs accessed first. auto-increment mechanism toggles Address Pointer Register after first access that next write goes MSB. only want write upper byte, 0x01 before write operation.
Group Registers
3-11
following register diagram shows organization SMR[15:8]. Descriptions fields follow register diagram. L64704 sets bits SMR[15:8] zero after software hardware reset.
FS_UL_IE FS_LL_IE CF_LLK_IE
CF_LK_IE CP_LLK_IE CP_LK_IE AFC_LLK_IE AFC_LK_IE
FS_UL_IE
Freq. Sweep Upper Limit Reached Interrupt Enable microcontroller sets FS_UL_IE enable interrupt when Frequency Sweep reached upper limit. L64704 always sets FS_UL STS[15:8] when this condition occurs.
FS_UL_IE Definition Disable Interrupt Frequency Sweep Upper Limit Reached Enable Interrupt Frequency Sweep Upper Limit Reached Detect
FS_LL_IE
Freq. Sweep Lower Limit Reached Interrupt Enable microcontroller sets FS_LL_IE enable interrupt when Frequency Sweep reached lower limit. L64704 always sets FS_LL STS[15:8] when this condition occurs.
FS_LL_IE Definition Disable Interrupt Frequency Sweep Lower Limit Reached Detect Enable Interrupt Frequency Sweep Lower Limit Reached Detect
CF_LLK_IE
Carrier Freq. Lock Lost Detect Interrupt Enable microcontroller sets CF_LLK_IE enable interrupt when Carrier Frequency Lock Loss detected (CAR_LCF=0). L64704 always sets CF_LLK STS[15:8] when this condition occurs.
CF_LLK_IE Definition Disable Interrupt Carrier Frequency Lock Loss Detect Enable Interrupt Carrier Frequency Lock Loss Detect
3-12
L64704 Registers
CF_LK_IE
Carrier Frequency Lock Detect Interrupt Enable microcontroller sets CF_LK_IE enable interrupt when Carrier Frequency Lock detected (CAR_LCF=1). L64704 sets CF_LK STS[15:8] when this condition occurs.
CF_LK_IE Definition Disable Carrier Frequency Lock Detect Interrupt Enable Carrier Frequency Lock Detect Interrupt
CP_LLK_IE
Carrier Phase Lock Lost Detect Interrupt Enable microcontroller sets CP_LLK_IE enable interrupt when Carrier Phase Lock Loss detected (CAR_LC L64704 always sets CP_LLK STS[15:8] when this condition occurs.
CP_LLK_IE Definition Disable Interrupt Carrier Phase Lock Loss Detect Enable Interrupt Carrier Phase Lock Loss Detect
CP_LK_IE
Carrier Phase Lock Detect Interrupt Enable microcontroller sets CP_LK_IE enable interrupt when Carrier Phase Lock detected (CAR_LC L64704 always sets CP_LK STS[15:8] when this condition occurs.
CP_LK_IE Definition Disable Interrupt Carrier Phase Lock Detect Enable Interrupt Carrier Phase Lock Detect
AFC_LLK_IE Clock Lock Lost Detect Interrupt Enable microcontroller sets AFC_LLK_IE enable interrupt when Automatic Frequency Controller Lock Loss detected. L64704 always sets AFC_LLK STS[15:8] when this condition occurs.
AFC_LLK_IE Definition Disable Interrupt Lock Lost Detect Enable Interrupt Lock Lost Detect
Group Registers
3-13
AFC_LK_IE
Clock Lock Detect Interrupt Enable microcontroller sets AFC_LK_IE enable interrupt when Automatic Frequency Controller Lock detected. L64704 always sets AFC_LK STS[15:8] when this condition occurs.
AFC_LK_IE Definition Disable Interrupt Lock Detect Enable Interrupt Lock Detect
This register diagram shows organization SMR[7:0]. Descriptions fields follow register diagram. L64704 clears bits zero after software hardware reset.
VBER_IE S3_LS_IE S3_S_IE S2_LS_IE S2_S_IE S1_LS_IE S1_S_IE Reserved
VBER_IE
Viterbi Error Rate Monitor Interrupt Enable microcontroller sets VBER_IE enable interrupt when Viterbi decoder reaches period specified VMDC2 (the period over which Viterbi errors counted). L64704 always sets VBER STS[7:0] when this condition occurs.
VBER_IE Definition Disable Interrupt Viterbi Count Enable Interrupt Viterbi Count
S3_LS_IE
Stage Loss Synchronization Interrupt Enable microcontroller sets S3_LS_IE enable interrupt when Descrambler synchronization lost.
S3_LS_IE Definition Disable Interrupt Stage Loss Synchronization Enable Interrupt Stage Loss Synchronization
3-14
L64704 Registers
S3_S_IE
Stage Synchronization Interrupt Enable microcontroller sets S3_S_IE enable interrupt when Descrambler synchronization established.
S3_S_IE Definition Disable Interrupt Stage Synchronization Enable Interrupt Stage Synchronization
S2_LS_IE
Stage Loss Synchronization Interrupt Enable microcontroller sets S2_LS_IE enable interrupt when Deinterleaver/Reed-Solomon Decoder synchronization lost.
S2_LS_IE Definition Disable Interrupt Stage Loss Synchronization Enable Interrupt Stage Loss Synchronization
S2_S_IE
Stage Synchronization Interrupt Enable microcontroller sets S2_S_IE enable interrupt when Deinterleaver/Reed-Solomon Decoder synchronization established.
S2_S_IE Definition Disable Stage Synchronization Interrupt Enable Stage Synchronization Interrupt
S1_LS_IE
Stage Loss Synchronization Interrupt Enable microcontroller sets S1_LS_IE enable interrupt when Viterbi Decoder synchronization lost.
S1_LS_IE Definition Disable Stage Loss Synchronization Interrupt Enable Stage Loss Synchronization Interrupt
S1_S_IE
Stage Synchronization Interrupt Enable microcontroller sets S1_S_IE enable interrupt when Viterbi Decoder synchronization established.
S1_S_IE Definition Disable Stage Synchronization Interrupt Enable Stage Synchronization Interrupt
Group Registers
3-15
Reserved
Reserved This reserved Logic internal only. should always this
3.4.2 System Status Register (STS)
Register read-only register that provides external microcontroller access status information about L64704. provides information about what event caused generation internal interrupt condition. interrupt status bits regardless enable interrupt bits Register. internal status updated every L64704 OCLK. When microcontroller reads status, current information buffered special purpose 16-bit buffer that locks value until microcontroller read operation. consecutive read operations must done same address both bytes STS. eight MSBs interrupts related Demodulation function L64704, eight LSBs interrupts related Forward Error Correction function L64704. status bits reset after hardware reset. They also reset each time that register byte read; when read eight LSBs, eight interrupts cleared, when read eight MSBs, eight interrupts cleared. register diagram below shows detailed description STS[15:8] register bits:
FS_UL
FS_LL
CF_LLK
CF_LK
CP_LLK
CP_LK
AFC_LLK
AFC_LK
FS_UL
Frequency Sweep Upper Limit Reached L64704 sets this when upper limit Frequency Sweep reached.
FS_UL Definition Frequency Sweep Status Unchanged Frequency Sweep Upper Limit Reached
FS_LL
Frequency Sweep Lower Limit Reached L64704 sets this when lower limit Frequency Sweep reached.
FS_LL Definition Frequency Sweep Status Unchanged Frequency Sweep Lower Limit Reached
3-16
L64704 Registers
CF_LLK
Carrier Frequency Lock Lost L64704 sets this when Carrier Frequency Lock lost.
CF_LLK Definition Carrier Frequency Lock Status Unchanged Carrier Frequency Lock Lost
CF_LK
Carrier Frequency Lock Established L64704 sets this when Carrier Frequency Lock established.
CF_LK Definition Carrier Frequency Lock Status Unchanged Carrier Frequency Lock Established
CP_LLK
Carrier Phase Lock Lost L64704 sets this when Carrier Phase Lock lost.
CP_LLK Definition Carrier Phase Lock Status Unchanged Carrier Phase Lock Lost
CP_LK
Carrier Phase Lock Established L64704 sets this when Carrier Phase Lock established.
CP_LK Definition Carrier Phase Lock Status Unchanged Carrier Phase Lock Established
AFC_LLK
Clock Lock Lost L64704 sets this when Clock Lock lost.
AFC_LLK Definition Clock Lock Status Unchanged Clock Lock Lost
AFC_LK
Clock Lock Established L64704 sets this when Clock Lock established.
AFC_LK Definition Clock Lock Status Unchanged Clock Lock Established
Group Registers
3-17
register diagram below shows detailed description STS[7:0] register bits.
VBER S3_LS S3_S S2_LS S2_S S1_LS S1_S Reserved
VBER
Viterbi Error Rate Flag L64704 sets VBER when period specified VMDC2 (Group APRs reached. also generates interrupt VBER_IE set. L64704 clears VBER zero after reset Group (STS) read.
VBER Definition VMDC2 Period Reached VMDC2 Period Reached
S3_LS
Stage Loss Synchronization Flag L64704 sets S3_LS when Descrambler synchronization module determines that synchronization lost. also generates interrupt S3_LS_IE SMR. L64704 clears S3_LS zero after reset Group (STS) read.
S3_LS Definition Stage Synchronization Status Unchanged Loss Stage Synchronization Detected
S3_S
Stage Synchronization Flag L64704 sets S3_S when Descrambler synchronization module acquires synchronization. also generates interrupt S3_S_IE SMR. L64704 clears S3_S zero after reset Group (STS) read.
S3_S Definition Stage Synchronization Status Unchanged Stage Synchronization Acquired
S2_LS
Stage Loss Synchronization Flag L64704 sets S2_LS when Deinterleaver/ReedSolomon Decoder synchronization module determines that synchronization lost. also generates interrupt
3-18
L64704 Registers
S2_LS_IE SMR. L64704 clears S2_LS zero after reset Group (STS) read.
S2_LS Definition Stage Synchronization Status Unchanged Loss Stage Synchronization Detected
S2_S
Stage Synchronization Flag L64704 sets S2_S when Deinterleaver/ReedSolomon Decoder synchronization module acquires synchronization. also generates interrupt S2_S_IE SMR. L64704 clears S2_S zero after reset Group (STS) read.
S2_S Definition Stage Synchronization Status Unchanged Stage Synchronization Acquired
S1_LS
Stage Loss Synchronization Flag L64704 sets S1_LS when Viterbi Decoder synchronization module determines that synchronization lost. also generates interrupt S1_LS_IE SMR. L64704 clears S1_LS zero after reset Group (STS) read.
S1_LS Definition Stage Synchronization Status Unchanged Loss Stage Synchronization Detected
S1_S
Stage Synchronization Flag L64704 sets S1_S when Viterbi Decoder synchronization module acquired synchronization. also generates interrupt S1_S_IE SMR. L64704 clears S1_S zero after reset Group (STS) read.
S1_S Definition Stage Synchronization Status Unchanged Stage Synchronization Acquired
Reserved
Reserved This reserved Logic internal only. Reading this will give unpredictable results.
Group Registers
3-19
Group Registers
Group consists number internal status registers that used diagnostics performance evaluation purposes. registers updated every OCLK cycle. When microcontroller reads register, current information buffered special purpose buffer that stores value respective register until read operation. L64704 clears bits Group registers zero after software hardware reset. Table shows addresses fields Group registers.
Table Group Register Reserved Reserved Reserved Demod_
Reed-Solomon Corrected Error Count Byte, CEC[7:0] Reed-Solomon Corrected Error Count High Byte, CEC[15:8] Reed-Solomon Uncorrected Error Count Byte, UEC[7:0] Reed-Solomon Uncorrected Error Count High Byte, UEC[15:0] Viterbi Error Rate Count Byte, VBERC[7:0] Viterbi Error Rate Count High Byte, VBERC[15:8] XCTR_IN Measured Carrier Frequency, CAR_VCOF[13:8]
Measured Carrier Frequency, CAR_VCOF[7:0] Loop Voltage Meter, PWR_LVL[7:0] CAR_LCF CAR_LC CLK_LCF
Readback, RI[5:0] Readback, RQ[5:0]
3-20
L64704 Registers
3.5.1 Group Corrected Error Count
When read, this register presents count corrected errors since last reset. When written, register reset zero. 16-bits long, where found counter incremented each time that byte corrected, independent number errors that encountered byte. incremented when block flagged uncorrectable. counter will wrap around when reaches maximum count. Read/Write:
Reset Value: 0x0000
Reed-Solomon Corrected Error Count Byte, CEC[7:0]
Reed-Solomon Corrected Error Count High Byte, CEC[15:8]
3.5.2 Group Uncorrected Error Count
When read, this register presents count uncorrected code words since last reset. When written, register zero. bits long, where found count stops when reaches maximum count (65535), counter reset each time that read. Read/Write:
Reset Value: 0x0000
Reed-Solomon Uncorrected Error Count Byte, UEC[7:0]
Reed-Solomon Uncorrected Error Count High Byte, UEC[15:8]
Group Registers
3-21
3.5.3 Group Viterbi Error Count
When read, this register presents count number Viterbi decoder errors found during time period specified VMDC2 (Group [5:5]). VBERC 16-bits long, where found actual number errors equal four times VBERC. VBERC updated each time that Viterbi error encountered, reset beginning each VMDC2 period. Read/Write:
Reset Value: 0x0000
Viterbi Error Rate Count Byte, VBERC[7:0]
Viterbi Error Rate Count High Byte, VBERC[15:8]
3.5.4 Group Control Input
This register contains Control Input bit(s), Demodulator bit, five upper bits Measured Frequency. Control Input bit(s) Demodulator discussed here, Measured Frequency field CAR_VCOF[13:8], discussed next section. Read/Write:
Reset Value: 0x0000
Demod XCTR_IN _SNR
CAR_VCOF[13:8]
Demod_SNR Demodulator Signal Noise Ratio When read, this gives indication SNR. When bad, this when good, this "bad" above threshold; "good" below threshold. Section 5.6.2.1, "Phase Error Estimator," Figure details. XCTR_IN External Control Input When read, this shows logic level applied External Control Input (XCTR_IN) pin.
3-22
L64704 Registers
3.5.5 Group Measured Frequency
L64704 puts result frequency measurement into this 16-bit register. Both upper lower nibbles must read before L64704 releases this register value. Section 5.6.1.2, "Carrier Frequency Measurement," details L64704 computes this value. Read/Write:
Reset Value: 0x0000
Demod XCTR_IN _SNR
CAR_VCOF[13:8]
CAR_VCOF[7:0]
3.5.6 Group Loop Voltage Meter
L64704 stores loop control voltage this register. Section 5.7.3, "Power Level," equation that relates VAGC PWR_LVL. Read/Write:
Reset Value: 0x00
PWR_LVL[7:0]
3.5.7 Group Carrier Synchronization Status
This register contains Carrier Loop pipeline synchronization status bits. Read/Write: Reset Value: 0x00
CAR_
Reserved
CAR_LC CLK_LCF
Reserved
Reserved Bits [7:6] These bits reserved Logic internal only. When read, they will return indeterminate value.
Group Registers
3-23
CAR_LCF
Carrier Frequency Lock Flag L64704 sets CAR_LCF indicate that carrier frequency lock detector lock.
CAR_LCF Definition Carrier Frequency Lock Detector Lock Carrier Frequency Lock Detector Locked
CAR_LC
Carrier Phase Lock Flag L64704 sets CAR_LC indicate that carrier phase lock detector locked.
CAR_LC Definition Carrier Phase Lock Detector Lock Carrier Phase Lock Detector Locked
CLK_LCF
Clock Frequency Lock Flag L64704 sets CLK_LCF indicate that clock generated control within pull-in range clock recovery loop.
CLK_LCF Definition Clock Frequency Lock Clock Frequency Locked
Stage Synchronization Flag L64704 sets when Descrambler synchronization module synchronization. When this Descrambler module synchronized.
Definition Descrambler Synchronization Descrambler Synchronization
3-24
L64704 Registers
Stage Synchronization Flag L64704 sets when Deinterleaver/ReedSolomon Decoder synchronization module synchronization. When this Deinterleaver/ReedSolomon Decoder synchronized.
Definition Deinterleaver/Reed-Solomon Decoder Synchronization Deinterleaver/Reed-Solomon Decoder Synchronization
Stage Synchronization Flag L64704 sets when Viterbi Decoder synchronization module synchronization. When this Viterbi Decoder synchronized.
Definition Viterbi Decoder Synchronization Viterbi Decoder Synchronization
3.5.8 Group Readback
This register displays value RI[5:0] input bus. Group values only correct when such that ICLK OCLK. Read/Write:
Reset Value: 0x00
Reserved
Reserved
Reserved Bits [7:6] These bits reserved Logic internal only. When read, they will return indeterminate value. Readback [5:0] This register displays value RI[5:0] input bus. (Note that OCLK needs running this feature operate properly).
Group Registers
3-25
3.5.9 Group Readback
This register displays value RQ[5:0] input bus. Group values only correct when such that ICLK OCLK. Read/Write:
Reset Value: 0x00
Reserved
Reserved
Reserved Bits [7:6] These bits reserved Logic internal only. When read, they will return indeterminate value. Readback [5:0] This register displays value RQ[5:0] input bus. (Note that OCLK needs running this feature operate properly).
Group Registers
Most Group registers bits wide while some registers wider bits). accesses done 8-bit widths. Address Pointer Register (APR) used access these registers described Section 3.3, "Group Address Pointer Register." Group registers affected reset. Group registers appear random immediately after power-up, retain their last known value after three reset operations shown 3.2, "Reset Affects Registers." Table shows addresses fields Group registers.
3-26
L64704 Registers
Table Group Register
APR[5:0]
PLL_N[5:0] PLL_S[5:0] PLL_T[4:0] Viterbi Code Rate, VCR[2:0] SYNC2_MOD PLL_M[1:0] Viterbi Data Count, VMDC1[7:0] Viterbi Data Count VMDC2[7:0], Byte Viterbi Data Count VMDC2[15:8], Middle Byte Viterbi Data Count VMDC2[23:16], High Byte Viterbi Maximum Error Count, VMBEC[7:0] Synchronization Word, Sync[7:0] Reserved L[1:0] Sync Status Select, Sync States Acq, Sync States Track, SSS[1:0] [1:0] SST[1:0] BPS[2:0] Output Selector, OS[2:0] PLL_RESET SYNC/ F_OUT_ CLK_LCF_ CLK_VC_ Reserved CLK_DR[1:0] SCLK SUPPRESS SWAP PCLK_BP CLK_RP[3:0] CLK_NF[15:8] CLK_NF[7:0] Reserved CLK_RATIO[2:0] PWR_REF[7:0] Reserved INT_DC PWR_BW[1:0] Scale Factor DEMI, DEMQ, SCALE[7:0]
Estimator Threshold, SNR_THS[7:0] Carrier Loop Offset Compensation, CAR_OFFSET[7:0]
Reserved Carrier Reference Period, CAR_RP[3:0] Carrier Loop Filter Gain Term), CAR_KP[7:0] Carrier Loop Filter Gain Term), CAR_KD[7:0] Carrier Lock Detector Threshold, CAR_THSL[7:0] Carrier Sweep Rate, CAR_SWR[7:0] Reserved Carrier Upper Sweep Limit, CAR_USWL[13:8] Carrier Upper Sweep Limit, CAR_USWL[7:0] Reserved Carrier Lower Sweep Limit, CAR_LSWL[13:8] Carrier Lower Sweep Limit, CAR_LSWL[7:0] CAR_SWP_ CAR_VCO_ CAR_VCO CAR_VCO CAR_OUT_S CAR_PED_ CAR_ CAR_SW SWAP SWAP 2N/P 1N/P OPEN Reserved FP_LOCK_ SNR_EST CON_SEL PWRP I_FORMAT DEMOD_ FEC_ Reserved External Control Output Bits, XCTR[3:0]
Group Registers
3-27
3.6.1 Group Parameter
Configuration Parameter used configure module clock synthesis. Read/Write:
PLL_N[5:0]
PLL_N
Logic internal test bit. must this Logic internal test bit. must this
Configuration Parameter [5:0] PLL_N[5:0] four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information Section 4.4, "PLL Clock Generation."
3.6.2 Group Parameter
Configuration Parameter used configure module clock synthesis. Read/Write:
PLL_S[5:0]
PLL_S
[7:6] Logic internal test bit. must these bits Configuration Parameter [5:0] PLL_S[5:0] parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information Section 4.4, "PLL Clock Generation."
3-28
L64704 Registers
3.6.3 Group Parameter Demodulator Symbol Select
Configuration Parameter used configure module clock synthesis. This register also contains bits configure demodulator select symbol format. Read/Write:
PLL_T[4:0]
Symbol Format indicates format incoming symbol stream. BPSK mode, must zero.
Symbol Format
This must proper operation.
QPSK/BPSK Format Select specify format incoming symbol stream. should systems that input QPSK symbol pair once ICLK cycle. should BPSK input stream only).
Symbol Stream Format QPSK BPSK
PLL_T
Configuration Parameter [4:0] PLL_T[4:0] four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information Section 4.4, "PLL Clock Generation."
Group Registers
3-29
3.6.4 Group Parameter Transport Viterbi Code Rate Select
Configuration Parameter used configure module clock synthesis. This register also contains bits Viterbi Decoder module code rate configure Transport Error Indicator. Read/Write:
Viterbi Code Rate, VCR[2:0]
SYNC2_
PLL_M[1:0]
VCR[2:0]
Viterbi Code Rate [7:5] these bits SELECT code rate Viterbi decoder module L64704. three bits assigned follows:
Data Bits Definition Rate Rate Rate Rate Rate Unused Unused Unused
Transport Error Indicator Select Transport Error Indicator Select activate transport error indicator mechanism. this mode, first following synchronization byte Transport Packet forced HIGH whenever data block found uncorrectable Reed-Solomon decoder. Otherwise remains unchanged. When transport error indicator will time. (See MPEG-2 System Specification H.222, paragraph 2.4.3.2 Transport Stream Packet Layer.) Using feature allows simpler interface Logic L64007 Transport Demultiplexer. more information, Logic L64007 MPEG-2, DVB, TSAT Transport Demultiplexer Technical Manual.
3-30
L64704 Registers
SYNC2_MOD Sync Modified This selects alternate method acquiring Sync should normal operation. PLL_M This must proper operation.
Frequency Range Module [1:0] PLL_M four parameters (PLL_S, PLL_N, PLL_T, PLL_M) that must configure module clock synthesis. more information Section 4.4, "PLL Clock Generation." PLL_M[1:0] tell L64704 frequency range VCO.
Data Bits Range
3.6.5 Group Viterbi Data Count
VMDC1 specifies number valid symbols, divided 256, over which number Viterbi decoded symbol errors counted synchronization. example, value VMDC1[7:0] 0b0000001 specifies data bits. more information Section 7.1.4, "Viterbi Error Rate Monitor." Read/Write:
Viterbi Maximum Data Count
3.6.6 Group Viterbi Data Count
VMDC2 specifies number valid symbols, divided over which number symbol errors Viterbi output data stream counted, after synchronization. symbol error count then displayed VBERC (Group 4:5). value VMDC2 occupies bits arranged three bytes with being least significant being most significant bit. example, value VMDC2[23:0] 0x0000F0 specifies data bits. more information Section 7.1.4, "Viterbi Error Rate Monitor."
Group Registers
3-31
Read/Write:
Viterbi Maximum Data Count Byte, VMDC2[7:0]
Viterbi Maximum Data Count Middle Byte, VMDC2[15:8]
Viterbi Maximum Data Count High Byte, VMDC2[23:16]
3.6.7 Group Viterbi Maximum Error Count
VMBEC specifies maximum number (Viterbi symbol errors/128 that allowed occur within data period VMDC1 (Group achieve Viterbi module synchronization. Whenever symbol error count from internal error counter exceeds value VMBEC, synchronization module concludes that Viterbi decoder module synchronization proceeds adjust phase incoming symbol stream until synchronization reached. example, value VMBEC[7:0] 0b00000011 specifies errors. more information Equation Section 7.1.4, "Viterbi Error Rate Monitor." Read/Write:
Viterbi Maximum Error Count VMBEC[7:0]
3.6.8 Group Synchronization Word
This register contains synchronization word used synchronization module stages three. Within this byte, oldest chronologically, newest. Read/Write:
Synchronization Word[7:0]
3-32
L64704 Registers
3.6.9 Group Monitor Mismatching Bits Sync Tracking Mode
This register used maximum number mismatching bits allowed declare match when comparing data stream reference synchronization word during tracking phase second synchronization stage. Read/Write:
Reserved
L[1:0]
This internal test should normal operation.
Reserved
Reserved Bits [6:2] These bits reserved Logic internal only. Reserved bits should always will produce random results when read. Mismatching Bits, Tracking Mode, Sync [1:0] This field used maximum number mismatching bits allowed declare match when comparing eight bits data stream reference synchronization word during tracking phase second synchronization stage. configured from higher value results smaller probability loss lock random noise, lower value higher probability loss.
Data Bits Number Mismatching Bits Illegal Value
L[1:0]
Group Registers
3-33
3.6.10 Group Synchronization States BCLKOUT Format
This register used select which algorithms will used synchronization modules, which module's synchronization status will shown SYNC output pin. also selects frequency clock that will output BCLKOUT pin. Read/Write:
SSS[1:0]
SSA[1:0]
SST[1:0]
BCLKOUT Format When this BCLKOUT outputs continuous clock waveform with duty cycle OCLK frequency. typically used downstream device that runs byte-clock rather than clock. DVALIDOUT needs observed identify valid data bytes. When this BCLKOUT produces rising edge every valid data output (Serial Output Channel mode). downstream device BCLKOUT data latching strobe without need inspect DVALIDOUT.
Data Bits BCLKOUT Function: Continuous Clock Data Strobe
Operating Mode Serial Output Channel Parallel Output Channel
SSS[1:0]
should this proper operation.
Synchronization Status Select [5:4] observe synchronization status three synchronization modules SYNC output pin: Viterbi decoder synchronization, Deinterleaver/ReedSolomon decoder synchronization, Descrambler synchronization. program field determine
3-34
L64704 Registers
which these three synchronization status bits will propagated SYNC pin.
Data Bits SYNC Connected Viterbi Decoder Synchronization DI/RS Decoder Synchronization Descrambler Synchronization
SSA[1:0]
Synchronization States, Acquisition Mode [3:2] second synchronization module (after Viterbi Decoder, before Deinterleaver module) allows three different state diagrams used acquisition phase. number properly identified synchronization words that will cause "in-synchronization" declared configured from more information Section 6.3, "Reed-Solomon Deinterleaver Synchronization."
Data Bits Number Sync Words Found Acquire
SST[1:0]
Synchronization Status, Tracking Mode [1:0] second synchronization module (after Viterbi decoder before Deinterleaver module) allows two, three, four, five undetected synchronization words before L64704 declares loss sync. more information Section 6.3, "Reed-Solomon Deinterleaver Synchronization."
Data Bits Number Missed Sync Words Loss Lock
Group Registers
3-35
3.6.11 Group Output Control
This register used configure Channel output data path. Read/Write:
BPS[2:0]
OS[2:0]
BPS[2:0]
Symbol Size Viterbi Bypass Mode [7:5] should these bits proper operation. should this proper operation. Descrambler Output Format Writing this sets descrambler output mode:
Data CO[7:0] Channel Output Mode Serial Channel Output Mode Parallel Channel Output Mode
Serial Channel Output mode, decoded data presented every OCLK cycle. Parallel Channel Output mode, byte decoded data presented CO[7:0] every eight OCLK cycles. OS[2:0] Output Selector [2:0] output several major functional blocks observed channel output (CO[7:0] Parallel Channel Output mode, Serial Channel Output mode). detailed description signals observed cases below, Section 4.5, "Data Path Output Configurations."
Data Bits Definition Descrambler Module Output Descrambler Module Synchronization (Sync Output Decoder Output Deinterleaver Module Output Deinterleaver/RS Synchronization (Sync Output Viterbi Decoder Module Output Viterbi Synchronization/Decoder Synchronization (Sync Output
3-36
L64704 Registers
Data Bits Definition BPSK/QPSK Demodulator Output
3.6.12 Group Reset
Writing value generates internal reset pulse module. L64704 ignores data D[7:0] during write this register. should reset module before operation. Reset register (APR cannot read. Read/Write: Write Only
PLL_RESET
3.6.13 Group Clock Loop Control
Clock Loop Control register used clock parameters related Demodulator module carrier synchronization logic. Read/Write:
SYNC/ SCLK
Reserved
F_OUT_ CLK_LCF CLK_VCO Suppress _SWAP
CLK_DR[1:0]
SYNC/SCLK
SYNC Output Select this select signal that want appear SYNC pin:
Output SYNC SCLK When Used Normal Operation Baud Rate Operations
When this SYNC carries signal selected Synchronization Status Select bits SSS[1:0] (Group 11). When this SYNC carries symbol clock demodulator, SCLK, that used clock external during baud rate operation. more information Section 5.6.2.3, "Low Baud Rate Operation."
Group Registers
3-37
Reserved
Reserved Bits These bits reserved Logic internal only. Reserved bits should always will produce random results when read. should this proper operation. Functional Outputs 3-stated this CLK_VCOP/N pins into high impedance condition.
Definition Normal Hi-Z
F_OUT_HiZ
CLK_LCF_Suppress CLK_LCF_Suppress Timing Error Detector this disable Automatic Frequency Controller (AFC). more information Section 5.5.2, "Clock Acquisition Tracking Modes."
Definition Normal Suppressed
CLK_VCO_SWAP Outputs Polarity Swap Program this polarity clock output pins CLK_VCOP/N. more information Section 5.5, "Channel Clock Recovery."
Definition Normal Swapped
CLK_DR[1:0] Decimation Filter Select [1:0] Program Decimation Filter Select field amount decimation, therefore oversampling ratio. more information Section 5.3, "Decimation Filters."
3-38
L64704 Registers
Decimation none Illegal
Oversampling Ratio
3.6.14 Group Clock Loop Control
Clock Loop Control register used clock parameters related Demodulator module Automatic Frequency Control (AFC) external phase-locked loop. also contains power-down control bit. Read/Write:
PCLK_
CLK_RP[3:0]
PCLK_BP
should this proper operation.
PCLK Bypass When this PCLK output carries clock signal generated internal module. When this PCLK presents SCLK output bypasses internal module. block diagram Section 4.1, "Data Control Clocking Schemes." should this proper operation.
Power-Down When Power-Down modules except asynchronous microprocessor interface turned reduce power consumption minimum. data processing occur during Power-Down. When Power-Down elements operate. should apply reset pulse after change Power-Down from (wake-up) before start processing data.
Definition Normal Operation Device Power-Down Mode
Group Registers
3-39
CLK_RP[3:0] Reference Period Clock [3:0] CLK_RP presets four MSBs reference counter. Section 5.5.2, "Clock Acquisition Tracking Modes" details. 3.6.15 Group Nominal Frequency Clock Input counter decrements once each clock edge during reference period. counter's initial value using 16-bit CLK_NF register where MSB, LSB. Section 5.5.2, "Clock Acquisition Tracking Modes" details. Read/Write:
CLK_NF[15:8]
CLK_NF[7:0]
3.6.16 Group Clock Ratio
This register used input decimation factor inputs. Read/Write:
Reserved CLK_RATIO[2:0]
Reserved
Reserved [7:3] These bits reserved Logic internal only. Reserved bits should always will produce random results when read.
CLK_RATIO[2:0] Input Decimation Factor Inputs [2:0] This field sets input decimation factor inputs. more information Section 5.5.1, "Input Decimation."
Definition Decimation Input Every Second Sample Input Every Fourth Sample
3-40
L64704 Registers
Definition Input Every Eighth Sample Input Every Sixteenth Sample Illegal Illegal Illegal
3.6.17 Group Power Reference Level
This register sets reference power level Analog Digital Convertor. details setting this register, Section 5.7.1, "ADC Range Power Reference." Read/Write:
PWR_REF[7:0]
3.6.18 Group Power Estimation Bandwidth Offset
This register used enable internal offset compensation signals power estimation bandwidth. Read/Write:
Reserved
INT_
PWR_BW[1:0]
Reserved
Reserved [7:3] These bits reserved Logic internal only. Reserved bits should always will produce random results when read. Internal Offset Compensation this enable internal offset compensation signals.
Definition Disabled Enabled
INT_DC
Group Registers
3-41
PWR_BW[1:0] Power Estimation Bandwidth [1:0] Program these bits power estimation bandwidth. more information Section 5.7.2, "Power Control Loop."
Symbol Rate (MHz)
3.6.19 Group Scale Factor DEMI DEMQ Outputs
Program these bits scale factor DEMI DEMQ outputs from Demodulator Decoder. relationship between SCALE PWR_REF, Section 5.8, "Output Control." Read/Write:
SCALE[7:0]
3.6.20 Group Estimator Threshold
this register value that phase detector's Signal Noise Ratio (SNR) comparator uses threshold when deciding which gain value use. details, Figure Section 5.6.2, "Carrier Phase Tracking." Read/Write:
SNR_THS[7:0]
3.6.21 Group Carrier Loop Offset Compensation Value
this register establish offset voltage that added subtracted from carrier loop voltage. value stored this register signed integer that ranges from -128 +127. details, Section 5.9.1, "Carrier Loop Offset Compensation."
3-42
L64704 Registers
Read/Write:
CAR_OFFSET[7:0]
3.6.22 Group Carrier Frequency Reference Period
This register used program preset value frequency sweep reference counter. Read/Write:
Reserved
CAR_RP[3:0]
Reserved
Reserved Bits [7:4] These bits reserved Logic internal only. Reserved bits should always will produce random results when read.
CAR_RP[3:0] Reference Period Carrier Frequency (CAR_DCLKP/N pin) Measurement [3:0] Program preset value four MSBs frequency sweep reference counter into this register. value programmed equals 1024 times number crystal (XOIN) clock cycles. Section 5.6.1, "Carrier Acquisition." 3.6.23 Group Carrier Loop Filter Gain Terms) Program CAR_KP CAR_KD with values that parameters carrier recovery loop. CAR_KP restricted values between inclusive. Section 5.6.2.2, "Loop Characteristics" details. Read/Write:
CAR_KP[7:0]
Group Registers
3-43
CAR_KD[7:0]
3.6.24 Group Carrier Lock Detector Threshold
value that program into CAR_THSL determines threshold Carrier Phase Lock Detector. details, Section 5.6.1.5, "Phase Lock Detection." Read/Write:
CAR_THSL[7:0]
3.6.25 Group Carrier Synchronizer Sweep Rate
value that program into this register determines Carrier Synchronizer sweep rate. details, Section 5.6.1.4, "Frequency Sweep Rate." Read/Write:
CAR_SWR[7:0]
3.6.26 Group Carrier Synchronizer Sweep Upper Limit
program CAR_USWL CAR_LSWL registers upper lower limits, respectively, frequency sweep. details, Section 5.6.1.1, "Frequency Sweep Limits." Read/Write:
Reserved
CAR_USWL[13:8]
CAR_USWL[7:0]
3-44
L64704 Registers
Reserved
Reserved Bits [7:6] These bits reserved Logic internal only. Reserved bits should always will produce random results when read.
CAR_USWL[13:0] Carrier Sweep Upper Sweep Limit [5:0], [7:0] Program CAR_USWL register upper limit frequency sweep.
Group Registers
3-45
3.6.27 Group Carrier Synchronizer Sweep Lower Limit
program CAR_USWL CAR_LSWL registers upper lower limits, respectively, frequency sweep. details, Section 5.6.1.1, "Frequency Sweep Limits." Read/Write:
Reserved
CAR_LSWL[13:8]
CAR_LSWL[7:0]
Reserved
Reserved Bits [7:6] These bits reserved Logic internal only. Reserved bits should always will produce random results when read.
CAR_LSWL[13:0] Carrier Sweep Lower Sweep Limit [5:0], [7:0] Program CAR_LSWL register lower limit frequency sweep. 3.6.28 Group Carrier Loop Configuration Register
This register contains various control bits that used configure Carrier Loop Synchronizer Loop logic. more information, Section 5.6, "Carrier Synchronizer."
Read/Write:
CAR_SW
CAR_SWP_ CAR_VCO_ CAR_VCO2 CAR_VCO1 CAR_OUT_ CAR_PED_ CAR_OPEN SWAP SWAP
CAR_SWP_SWAP Swap Carrier Sweep Direction this control whether carrier acquisition frequency sweep direction normal reversed. should toggled whenever carrier sweep reaches limit
3-46
L64704 Registers
without achieving carrier lock, when constellation locked 45°.
Sweep Direction Normal Reversed
CAR_VCO_SWAP Swap Output Polarity this invert polarities CAR_VCOxN/P pins. should toggled whenever carrier sweep reaches limit without achieving carrier lock, when constellation locked 45°.
Polarity Normal Swapped Inverted)
CAR_VCO2N/P Outputs Active 3-state Program this enable disable outputs second Sigma Delta differential pair. rate applications that external DAC, must enable both Sigma-Delta outputs setting Carrier Loop Configuration Register bits [5:4] zero. more information, Section 5.6, "Carrier Synchronizer."
CAR_VCO2N/P Pins Active 3-state
This should always when CAR_OUT_SEL CAR_VCO1N/P Outputs Active 3-state Program this enable disable outputs first Sigma Delta differential pair. rate applications that external DAC, must enable both SigmaDelta outputs setting Carrier Loop Configuration
Group Registers
3-47
Register bits [5:4] zero. more information, Section 5.6, "Carrier Synchronizer."
CAR_VCO1N/P Pins Active 3-state
This should always when CAR_OUT_SEL CAR_OUT_SEL Carrier Loop Output Selector this route Phase Error Detector outputs Carrier Loop output pins instead Sigma-Delta circuit outputs. This allows full range frequencies decoded using external baud rate operation. more information, Section 5.6.2.3, "Low Baud Rate Operation." output assignments when using CAR_OUT_SEL are:
Output Name CAR_PED.0 CAR_PED.1 CAR_VCO1P CAR_VCO2P CAR_VCO1N CAR_VCO2N CAR_OUT_SEL CAR_PED.0 CAR_PED.1 CAR_VCO1P CAR_VCO2P CAR_VCO1N CAR_VCO2N CAR_PED.0 CAR_PED.1 CAR_PED.2 CAR_PED.3 CAR_PED.4 CAR_PED.5
CAR_PED_SEL Carrier Phase Error Detector Select Program this select which phase error estimator will used carrier phase tracking. details, Section 5.6.2, "Carrier Phase Tracking," Figure 5.9.
Estimator Selected Decision Directed Maximum Likelihood (DDML) Non-Data Aided Maximum Likelihood (NDAML)
3-48
L64704 Registers
CAR_OPEN
Carrier Loop Open this force loop false lock condition. more information Section 5.6.1.7, "False Locks."
Definition Enable Carrier Loop Unlock (Disable) Carrier Loop
CAR_SW
Sweep On/off Carrier Loop CAR_SW enable carrier acquisition sweep generator. more information Section 5.6.1, "Carrier Acquisition."
Definition Sweep Sweep
3.6.29 Group
This register reserved Logic internal only. must program bits shown during device initialization. Read/Write:
Reserved
Reserved
[7:5] must these bits normal operation. Reserved Bits [4:0] These bits reserved Logic internal only. Reserved bits should always will produce random results when read.
Group Registers
3-49
3.6.30 Group Decoder Configuration Register
SNR_EST
This resister contains various control bits that used configure L64704 Decoder logic.
Read/Write:
CON_SEL FP_LOCK_ PWRP I_FORMAT
SNR_EST
Estimator On/Off this enable disable Estimator circuit.
Estimator
CON_SEL
Constellation Selector this indicate format input data.
Definition QPSK BPSK
must this normal operation
FP_LOCK_LEN Frequency/Phase Lock Detector Length Program this conjunction with Carrier Threshold field (Group phase lock detector estimation period. details, Section 5.6.1.5, "Phase Lock Detection."
Estimation Period Normal (Long) Short
3-50
L64704 Registers
PWRP
PWRP Signal Invert this invert polarity signal that output PWRP pin.
PWRP Output Normal Inverted
I_FORMAT
must these bits normal operation Input Format Selector Program this tell L64704 format incoming data.
Input Format Offset Binary Format Complement Format
[2:1]
3.6.31 Group External Output Control Bits Reset Register
This register contains control bits external output pins XCTR_OUT[3:0] bits that reset demodulator circuitry. Read/Write:
DEMOD_
FEC_
Reserved
XCTR[3:0]
Reserved
Reserved Bits [7:6] These bits reserved Logic internal only. Reserved bits should always will produce random results when read. External Control Output Bits [5:2] value that this field will appear corresponding external output XCTR_OUT[3:0]. Section 5.9.2, "External Controls," more information.
XCTR[3:0]
Group Registers
3-51
XCTR
Definition Corresponding Output Corresponding Output
DEMOD_RST QPSK Demodulator Software Reset L64704 resets internal datapath control modules QPSK Demodulator portion device when DEMOD_RST decoder module affected. need back complete reset. L64704 issues single reset pulse each time microcontroller writes this bit. When DEMOD_RST set, L64704 resets demodulator processing unit state machines their initial states.
Demod_Reset Definition Reset L64704 Issues Demodulator Reset
FEC_RST
Decoder Software Reset L64704 resets internal datapath control modules portion device when FEC_RST demodulator module affected. need back complete reset. L64704 issues single reset pulse each time microcontroller writes this bit. When FEC_RST set, L64704 resets processing unit state machines their initial states.
FEC_Reset Definition Reset L64704 Issues Reset
3-52
L64704 Registers
Chapter Channel Interfaces Data Control
L64704 interface supports independent interfaces incoming channel data decoded output data. Both interfaces used simultaneously. input interface transfers data from external device L64704. output interface transfers data from L64704 next processing device, typically MPEG-2 transport demultiplexer such Logic's L64007. This chapter contains five sections:
Section 4.1, "Data Control Clocking Schemes," describes
Channel Data Interface signals clock that strobes data into L64704.
Section 4.2, "Channel Data Input Interface," provides timing diagrams
Channel Data input signals.
Section 4.3, "Channel Data Output Interface," provides timing
diagrams Channel Data output signals.
Section 4.4, "PLL Clock Generation," describes Phase-Locked
Loop clock generation circuitry detail.
Section 4.5, "Data Path Output Configurations," shows
program output data path multiplexer carry outputs various stages decoding pipeline.
Data Control Clocking Schemes
L64704 uses input clock signals, OCLK, accommodate number possible configurations channel decoding system. generated external Clock two, three, four times symbol rate. There also internally generated symbol clock, SCLK. OCLK Forward Error Correction clock. relation determined Viterbi puncture rate number samples symbol ADC. on-chip generates desired OCLK frequency outputs PCLK output (see Figure 4.1). should connect PCLK output OCLK input pin.
Figure L64704 Clocking: Internal
L64704 PCLK Selected PCLK OCLK
Demodulator DEMI DEMQ SCLK
PCLK
also generate desired OCLK signal using external (see Figure 4.2). that case PCLK should output symbol rate clock, SCLK. external frequency function Viterbi puncture rate.
Channel Interfaces Data Control
Figure L64704 Clocking: External
L64704 SCLK Selected PCLK OCLK
Demodulator DEMI DEMQ SCLK
PCLK
Figure Figure show several clocking examples. Figure shows case where input data rate data processing rate decoding pipeline. FIFO input FIFO output data streams same rate because extra information (erasures) need added after FIFO. OCLK signals need aligned phase.
Figure Code Rate System
FIFO Input
OCLK FIFO Output Viterbi Data Output
Dn+1 Dn+2 Dn+3
Data Control Clocking Schemes
Figure illustrates case where input data rate data processing rate decoding pipeline. Because depuncturing logic inserts extra symbols (erasures), L64704 transmits symbols from FIFO small bursts higher clock rate (OCLK). After leaving Viterbi Decoder, data stream becomes continuous OCLK rate.
Figure Code Rate System; Different OCLK
FIFO Input
OCLK FIFO Output Viterbi Data Output
Dn+1 Dn+2 Dn+3
Figure shows case which data rate ratios shown maintained, incoming data stream continuous, decoder fixes frequency OCLK twice that CLK. Because decoder reads FIFO OCLK frequency- which greater than Viterbi code rate-the FIFO empties periodically. data pipeline designed handle such internal interruptions data stream without corrupting data that already being processed. consequence, channel output data appears bursts OCLK rate, average maintains data rate imposed Viterbi Decoder. DVALIDOUT signal indicates when valid data CO[7:0] output.
Channel Data Input Interface
Figure Reference Channel Data Input
Figure shows channel data input signals RI[5:0] RQ[5:0] referenced CLK.
RI[5:0], RQ[5:0] Hold Setup
Channel Interfaces Data Control
Channel Data Output Interface
Figure OCLK Reference Channel Data Output
Figure shows channel data output signals CO[7:0], DVALIDOUT, ERROROUT, FSTARTOUT referenced OCLK.
OCLK CO[7:0], DVALIDOUT, ERROROUT, FSTARTOUT, SYNC
Output Delay
Figure shows that data valid output whenever L64704 asserts DVALIDOUT. L64704 deasserts DVALIDOUT when transfers parity data. When L64704 detects uncorrectable error, asserts ERROROUT while transmits both data parity bytes.
Figure FSTARTOUT Related Symbols
CO[7:0] DVALIDOUT FSTARTOUT ERROROUT
Data
Parity
L64704 asserts FSTARTOUT when transfers first first symbol every frame. frame structure does require gap, decoding process does affect bytes.
Clock Generation
data control clocking schemes presented Section 4.1, "Data Control Clocking Schemes," outline requirements generation external clock signals (CLK OCLK) that required L64704. have choose whether provide externally generated clock OCLK input internal clock synthesis. internal selected connecting output (PCLK) OCLK input shown Figure Figure 4.1.
Channel Data Output Interface
Using internal clock feature allows L64704 consume minimum amount power.
Figure Clock Generation
SCLK Internal PCLK Output OCLK Input L64704 Clock Synthesis
Data Input
FIFO
Viterbi Decoder Deinterleaver Reed-Solomon Decoder Descrambler OCLK Domain
Decoded Data Output
SCLK Domain
L64704 contains clock synthesizer derive OCLK from SCLK operating range 62.5 (see Figure 4.9). synthesized clock available PCLK output pin. configured handle clock ratios Viterbi code rates 1/2, 2/3, 3/4, 5/6, 7/8. following four registers must derive appropriate clock frequencies:
PLL_T[4:0], Group PLL_N[5:0], Group PLL_S[5:0], Group PLL_M[1:0], Group
Channel Interfaces Data Control
Table shows ratio SCLK.
Table CLK/SCLK Ratio CLK_RATIO[2:0] CLK_DR[1:0] Ratio Group Group CLK/SCLK
Figure Clock Synthesis
Clock Synthesis 1/(PLL_S) PLL_M (Phase Detector Charge Pump VCO) PCLK Output
SCLK Internal
1/(PLL_N)
1/(PLL_T)
PLLVSS PLLVDD
PLLAGND
ohms
External Loop Filter
recommended values PLL_S, PLL_N, PLL_T, PLL_M cover frequency range from 62.5 PCLK tabulated Table 4.2.
Clock Generation
Table Values PLL_S, PLL_N, PLL_T, PLL_M
Code Rate PLL_S[5:0] PLL_N[5:0] PLL_T[4:0] PLL_M[1:0] SCLK PCLK
70.00 60.00 50.00 40.00 35.00 30.00 25.00 20.00 17.50 15.00 12.50 11.67 10.00 8.75 7.50 6.25 5.00 4.00 3.33 2.86 2.50 2.22 2.00
80.00 70.00 60.00 50.00 40.00 35.00 30.00 25.00 20.00 17.50 15.00 13.33 11.67 10.00 8.75 7.50 6.25 5.00 4.17 3.57 3.12 2.78 2.50
70.00
80.001 70.001 60.00 50.00 40.00 35.00 30.00 25.00 20.00 17.50 15.00 13.33 11.67 10.00 8.75 7.50 6.25 5.00 4.17 3.57 3.12 2.78 2.50
60.00 50.00 40.00 35.00 30.00 25.00 20.00 17.50 15.00 12.50 11.67 10.00 8.75 7.50 6.25 5.00 4.00 3.33 2.86 2.50 2.22 2.00
(Sheet
Channel Interfaces Data Control
Table (Cont.) Values PLL_S, PLL_N, PLL_T, PLL_M
Code Rate PLL_S[5:0] PLL_N[5:0] PLL_T[4:0] PLL_M[1:0] SCLK PCLK
52.50 45.00 37.50 30.00 26.25 22.50 18.75 15.00 6.25 5.00 13.12 11.25 9.38 7.50 4.38 3.75 3.12 2.50 2.08 2.00 46.67 40.00 33.33 26.67 23.33 20.00 16.67 13.33
60.00 52.50 45.00 37.50 30.00 26.25 22.50 18.75 7.50 6.25 15.00 13.12 11.25 9.38 5.00 4.38 3.75 3.12 2.50 2.08 53.33 46.67 40.00 33.33 26.67 23.33 20.00 16.67
70.00
80.001 70.001 60.00 50.00 40.00 35.00 30.00 25.00 10.00 8.33 20.00 17.50 15.00 12.50 6.67 5.83 5.00 4.17 3.33 2.78 80.001 70.001 60.00 50.00 40.00 35.00 30.00 25.00
60.00 50.00 40.00 35.00 30.00 25.00 20.00 8.33 6.67 17.50 15.00 12.50 10.00 5.83 5.00 4.17 3.33 2.78 2.67 70.00
60.00 50.00 40.00 35.00 30.00 25.00 20.00
(Sheet
Clock Generation
Table (Cont.) Values PLL_S, PLL_N, PLL_T, PLL_M
Code Rate PLL_S[5:0] PLL_N[5:0] PLL_T[4:0] PLL_M[1:0] SCLK PCLK
11.67 10.00 8.33 6.67 5.56 5.00 4.17 3.33 2.86 2.38 2.00 42.00 36.00 30.00 24.00 21.00 18.00 15.00 12.00 5.00 4.00 10.50 9.00 7.50 6.00 3.50 3.00 2.50 2.00
13.33 11.67 10.00 8.33 6.67 5.83 5.00 4.17 3.33 2.86 2.38 48.00 42.00 36.00 30.00 24.00 21.00 18.00 15.00 6.00 5.00 12.00 10.50 9.00 7.50 4.00 3.50 3.00 2.50
17.50 15.00 12.50 10.00 8.33 7.50 6.25 5.00 4.29 3.57 3.00 60.00 50.00 40.00 35.00 30.00 25.00 20.00 8.33 6.67 17.50 15.00 12.50 10.00 5.83 5.00 4.17 3.33
20.00 17.50 15.00 12.50 10.00 8.75 7.50 6.25 5.00 4.29 3.57 70.001 60.00 50.00 40.00 35.00 30.00 25.00 10.00 8.33 20.00 17.50 15.00 12.50 6.67 5.83 5.00 4.17
70.001 80.001
(Sheet
4-10
Channel Interfaces Data Control
Table (Cont.) Values PLL_S, PLL_N, PLL_T, PLL_M
Code Rate PLL_S[5:0] PLL_N[5:0] PLL_T[4:0] PLL_M[1:0] SCLK PCLK
40.00 28.57 22.86 20.00 17.14 14.29 11.43 10.00 8.57 7.14 5.00 4.29 3.57 6.67 5.71 3.33 2.86 2.38 2.00
45.71 34.29 28.57 22.86 20.00 17.14 14.29 11.43 10.00 8.57 5.71 5.00 4.29 7.62 6.67 3.81 3.33 2.86 2.38
70.00
80.001 60.00 50.00 40.00 35.00 30.00 25.00 20.00 17.50 15.00 10.00 8.75 7.50 13.33 11.67 6.67 5.83 5.00 4.17
50.00 40.00 35.00 30.00 25.00 20.00 17.50 15.00 12.50 8.75 7.50 6.25 11.67 10.00 5.83 5.00 4.17 3.50
(Sheet Although module generate PCLK frequencies MHz, maximum OCLK frequency limited 62.5 MHz.
Clock Generation
4-11
Data Path Output Configurations
L64704 provides user with mechanism observe output each functional block decoding pipeline. This feature simplifies performance characterization system diagnostics tasks. Figure 4.10 shows functional blocks decoding pipeline. observe outputs from Descrambler, Reed-Solomon Decoder, Viterbi Decoder, Deinterleaver Module QPSK Demodulator through CO[7:0], DVALIDOUT, ERROROUT, FSTARTOUT BCLKOUT output signals. select output, external microcontroller must output selector bits OS[2:0] (Group register enable appropriate functional block output. description OS[2:0] page 3-36 details.
4-12
Channel Interfaces Data Control
Figure 4.10 L64704 Functional Blocks Decoding Pipeline
Data BPSK/QPSK Demodulator OS[2:0] Viterbi Sync/ Decoder Module OS[2:0] Viterbi Decoder Module OS[2:0] Configuration Parameters Decoder Datapath Control Deinterleaver/RS Synchronization Module OS[2:0] Deinterleaver Module OS[2:0] Decoder Module OS[2:0] Descrambler Synchronization Module OS[2:0] Descrambler Module
OS[2:0]
OS[2:0]
4.5.1 Descrambler Output
observe output entire decoding pipeline, ending after Descrambler, setting OS[2:0] bits 0b000. Figure 4.11 Figure 4.12 show Descrambler output waveforms Serial Channel Output Mode Parallel Channel Output Mode respectively.
Data Path Output Configurations
4-13
Figure 4.11 Descrambler Serial Output Waveforms
OCLK FSTARTOUT Message Check Bytes Message
Code Word Length DVALIDOUT ERROROUT
When Output Format (Group (Serial Channel Output Mode), L64704 outputs data serially CO[0]. L64704 outputs data cycle OCLK (see Figure 4.11). L64704 asserts FSTARTOUT cycle that overlaps first message Reed-Solomon code word.
Figure 4.12 Descrambler Parallel Output Format
OCLK FSTARTOUT OCLK Cycles CO[7:0] Byte Byte Byte N-R-1 Check Bytes Message
Message Bytes Code Word Length
BCLKOUT DVALIDOUT ERROROUT
When (Parallel Channel Output Mode), L64704 outputs data byte CO[7:0] every eight OCLK cycles (Figure 4.12). L64704 chronologically orders data Parallel
4-14
Channel Interfaces Data Control
Channel Output Mode, where oldest, newest. FSTARTOUT strobe overlaps first data byte. (Group 11), L64704 provides BCLKOUT additional strobe that rising falling edge valid CO[7:0] data byte. L64704 asserts BCLKOUT middle decoded data bytes, device that receives output from L64704 latch data BCLKOUT rate rather than OCLK rate. BCLKOUT continuous clock output OCLK frequency when cleared, regardless whether data present CO[7:0] bus. 4.5.2 Synchronization Stage Output observe outputs synchronization stage preceding Descrambler setting OS[2:0] bits 0b001. Figure 4.13 shows Synchronization Stage output signals. Signals prefixed "S3_" driven indicated parenthesis below signal name.
Figure 4.13 Synchronization Stage Output Waveforms
OCLK S3_FSTARTOUT (Pin FSTARTOUT) S3_CO[7:0] (Pins CO[7:0]) Message Bytes Check Bytes Message
Code Word Length S3_DVALIDOUT (Pin DVALIDOUT) S3_ERROROUT (Pin ERROROUT)
contrast Descrambler output, CO[7:0] still carries scrambled data. 4.5.3 Reed-Solomon Decoder Output observe outputs Reed-Solomon decoder module setting OS[2:0] bits 0b010. This mode also used want bypass Descrambler entirely. Figure 4.14 shows ReedSolomon Decoder output signals. Signals prefixed "RS_" driven indicated parenthesis below signal name.
Data Path Output Configurations
4-15
Figure 4.14 Reed-Solomon Decoder Output Waveforms
OCLK RS_FSTARTOUT (Pin FSTARTOUT) RS_CO[7:0] (Pins CO[7:0]) Message Bytes Check Bytes Message
Code Word Length RS_DVALIDOUT (Pin DVALIDOUT) RS_ERROROUT (Pin ERROROUT)
4.5.4 Deinterleaver Output
observe output signals from Convolutional Deinterleaver setting OS[2:0] bits 0b011. Figure 4.15 shows Deinterleaver output waveforms. Signals prefixed "DI_" driven indicated parenthesis below signal name.
Figure 4.15 Deinterleaver Output Waveforms
OCLK DI_FSTARTOUT (Pin FSTARTOUT) DI_CO[7:0] (Pins CO[7:0]) Deinterleaver Data DI_DVALIDOUT (Pin DVALIDOUT) S2_INSYNC (Pin ERROROUT)
L64704 uses FSTARTOUT, CO[7:0], DVALIDOUT signals carry corresponding Deinterleaver outputs.
4-16
Channel Interfaces Data Control
4.5.5 Synchronization Stage Output
observe output synchronization stage preceding Deinterleaver setting OS[2:0] bits 0b100. Synchronization Stage detects predefined synchronization word properly align data stream. Figure 4.16 shows waveforms Synchronization Stage output signals. Signals prefixed "S2_" driven indicated parenthesis below signal name.
Figure 4.16 Synchronization Stage Output Waveforms
OCLK S2_FSTARTOUT (Pin FSTARTOUT) S2_CO[7:0] (Pins CO[7:0]) Frame Length S2_DVALIDOUT (Pin DVALIDOUT) S2_INSYNC (Pin ERROROUT)
observe S2_INSYNC signal monitor state second synchronization stage. When L64704 asserts S2_INSYNC, indicates that decoder established frame synchronization. When L64704 deasserts S2_INSYNC, indicates out-of-sync condition. 4.5.6 Viterbi Decoder Output observe outputs Viterbi decoder module setting OS[2:0] bits 0b101. this mode observe decoded data after only inner layer decoding. Figure 4.17 shows waveforms Viterbi Decoder output signals. Signals prefixed "V_" driven indicated parenthesis below signal name.
Data Path Output Configurations
4-17
Figure 4.17 Viterbi Decoder Output Waveforms
OCLK V_BITERR (Pin ERROROUT) V_CO (Pins CO[0]) V_DVALIDOUT (Pin DVALIDOUT)
L64704 outputs decoded Viterbi data stream serially OCLK cycle. V_DVALIDOUT signal indicates whether data valid cycle-by-cycle basis. V_BITERR signal carries information errors found Viterbi output stream. L64704 deasserts V_BITERR, indicates that decoder correctly decoded current data V_CO. 4.5.7 Viterbi Depuncture/ Synchronization Output observe outputs Viterbi synchronization stage associated depuncturing module setting OS[2:0] bits 0b110. Figure 4.18 shows waveforms Viterbi Synchronization/Depuncture module output signals. Signals prefixed "DP_" driven indicated parenthesis below signal name.
Figure 4.18 Viterbi Depuncture/ Synchronization Output Waveforms
OCLK DP_S1_E (Pin CO[7]) DP_S1 (Pins CO[6:4]) DP_S0_E (Pin CO[3]) DP_S0 (Pins CO[2:0]) DP_DVALIDOUT (Pin DVALIDOUT) S1_INSYNC (Pin ERROROUT)
4-18
Channel Interfaces Data Control
this mode, L64704 outputs depunctured Viterbi input data stream. data stream consists symbol streams corresponding erasures flags CO[7:0] shown Figure 4.18. L64704 uses S1_INSYNC signal monitor state Viterbi synchronization stage. When L64704 asserts S1_INSYNC, indicates that Viterbi module synchronization been established. When L64704 deasserts S1_INSYNC, indicates out-of-sync condition. 4.5.8 QPSK Demodulator Output
Figure 4.19 QPSK Demodulator Output Waveforms
DEMOD_SCLK (Pin PCLK) DEMOD_I (Pins CO[7:5]) DEMOD_Q (Pins CO[4:2]) DEMOD_DVALID (Pin CO[1])
observe outputs QPSK Demodulator module setting OS[2:0] bits 0b111. Signals prefixed "DEMOD_" driven indicated parenthesis below signal name. Figure 4.19 shows waveforms QPSK Demodulator module output signals.
this mode, L64704 outputs demodulated QPSK data stream. This data stream consists symbol streams DEMOD_I DEMOD_Q accompanied DEMOD_DVALID.
Data Path Output Configurations
4-19
4-20
Channel Interfaces Data Control
Chapter Demodulator Module Functional Description
This chapter describes function BPSK/QPSK Demodulator module within L64704 divided into following sections:
Section 5.1, "Overview," provides high-level description
Demodulator Module shows fits into set-top decoder.
Section 5.2, Offset Compensation Coupling Output,"
describes L64704's Offset Compensation circuit.
Section 5.3, "Decimation Filters," describes input decimation
filters.
Section 5.4, "Matched Filter," provides information
branch decimation filter.
Section 5.5, "Channel Clock Recovery," provides information
Channel Clock recovery loop.
Section 5.6, "Carrier Synchronizer," describes logic that
necessary implement Carrier Synchronizer circuit.
Section 5.7, "Automatic Gain Control (AGC)," describes L64704's
automatic gain control.
Section 5.8, "Output Control," provides information QPSK
demodulator's output control circuitry.
Section 5.9, "Other Functions," describes remaining circuitry
L64704's BPSK/QPSK Demodulator.
Overview
Demodulator Module connects satellite receiver circuitry set-top recover modulated MPEG-2 transport stream. Figure shows connections between BPSK/QPSK Demodulator associated circuitry.
Figure Demodulator Module Associated Circuitry
Set-Top L64704 Outputs Decoding Pipeline Decimation Matched Filter Filter Section Section Output Control Section
Overview
Gain Control Amplifier
Down Conv.
Dual
Loop Filter
Offset Estimator Section CLKVCOP Channel Clock Sync Section
Loop Filter
Loop Filter
CLKVCON
CARVCOP CARVCON
Carrier Sync Section Control Section
PWRP
Offset Compensation Coupling Output
L64704 provides internal suppression offsets channels. enable this function, PWR_BW bits (Group 20). This feature particularly useful when using integrated front that does provide offset compensation pins that introduces small offsets. external analog digital convertor must produce six-bit samples that reflect 32-positive values 32-negative values shown Figure 5.2. six-bit samples RI[5:0] RQ[5:0] inputs.
Figure Input Quantization with Coupling
RI[5:0], RQ[5:0]
Input
Decimation Filters
L64704 implements switchable decimation filters each branch: 1/2-band filter 2/3-band filter. These filters enable Analog Digital Convertor (ADC) operate oversampling ratio filters generate 2/T-sampled streams from sampled inputs. resulting streams inputs matched filter. configure decimation filters, microcontroller should write following values CLK_DR[1:0] bits Clock Loop Control register (Group APR14):
CLK_DR decimation, CLK_DR decimation 1/2, CLK_DR decimation 2/3,
Offset Compensation Coupling Output
Matched Filter
L64704 implements fixed matched filter branches according standard (square root raised cosine shape with rolloff 0.35). filter operates constant input rate 2/T.
Channel Clock Recovery
Figure illustrates Channel Clock recovery loop. This circuit consists L64704's Clock Synchronizer external analog circuitry. Clock Synchronizer generates loop voltage external from L64704's matched-filtered samples. Clock Synchronizer delivers this voltage balanced CMOS differential output pins CLK_VCON CLK_VCOP. These outputs feed inverting noninverting inputs external operational amplifier that implements loop filter before VCO.
Figure Clock Recovery Loop
L64704 Channel Clock Synchronizer Matched Filter Outputs CLK_VCO_SWAP Register CLK_VCON Loop Filter CLK_VCOP CLK_LCF Converter Timing Error Detector
External Analog Circuitry
XOIN XTAL XOUT
CLK_NF Register CLK_RP Register
SCLK
CLK_LCF_SUPPRESS Register
Dual Converter
Demodulator Module Functional Description
5.5.1 Input Decimation
CLK_RATIO[2:0] bits (Group ratio clock required sample clock L64704. example, input signal 5-Mbaud oversampling ratio then input sample frequency MHz. Under same conditions, possible running specifying CLK_RATIO This corresponds input decimation this case every second sample coming from L64704. This feature allows satellite decoder control program choose reduced range when L64704 must operate over wide range baud rates. Note that setting CLK_RATIO bits does switch decimation filters data path; therefore external filtering must baud rate oversampling ratio selected CLK_DR bits (Group 14).
5.5.2 Clock Acquisition Tracking Modes
Clock Synchronizer operates modes:
Clock Acquisition Tracking
5.5.2.1 Clock Acquisition Mode acquisition mode (indicated CLK_LCF Group Automatic Frequency Controller (AFC) active Timing Error Detector (TED) not. Software disable after Clock Synchronizer completes acquisition timing loop. This prevents system from switching back acquisition mode short interrupt occurs during transmission. Setting CLK_LCF_SUPPRESS (Group disables AFC. control function determines whether clock within pull-in range L64704. clock within pull-in range, CLK_LCF clock slow, then drives positive voltage loop output order generate positive frequency sweep. clock fast, then drives voltage loop output order generate negative frequency sweep.
Channel Clock Recovery
counter decrements once each clock edge during reference period defined below. microcontroller sets counter's initial value using 16-bit CLK_NF register (Group 16:17). counter reached either reference period, clock within pull-in range; therefore sets CLK_LCF declare lock. counter value greater than clock frequency low; therefore drives positive voltage loop output order generate positive frequency sweep. counter value less than clock frequency high; therefore drives voltage loop output order generate negative frequency sweep. reference period determined frequency reference from external crystal. reference period derived preloading reference counter with value CLK_RP register (Group 15). This defines reference period multiples 1024 clock cycles. CLK_RP 4-bit register, whose value ranges from external crystal frequency must less than half clock frequency fVCO. recommended value uncertainty 1024 CLK_RP ensure that clock recovery loop locks when Clock Synchronizer switches from acquisition tracking mode, uncertainty must lower than pull-in range clock recovery loop. CLK_RP MHz, uncertainty approximately kHz. Equation relates parameters described above must satisfied reliable operation.
Equation
CLK_RP 1024 CLK_NF
example, consider following frequency values:
Nominal clock frequency, fVCO External crystal frequency,
Demodulator Module Functional Description
According Equation 5.1, CLK_RP CLK_NF must such that:
Equation
CLK_RP 1024 CLK_NF instance, choose CLK_RP 0xA, then CLK_NF 1024 61440 0xF000. When clock frequency within pull-in range, Clock Synchronizer closes clock recovery loop automatically then enters tracking mode. 5.5.2.2 Tracking Mode tracking mode (indicated CLK_LCF; Group clock recovery loop closed Sigma Delta converter takes input from Timing Error Detector (TED) output rather than output. loop characteristics determined external active filter with parameters RCLK1, RCLK2, CCLK, gain KVCO. natural frequency damping factor loop determined following formulas:
Equation
where denotes number samples symbol least constant equal volts, KVCO expressed rad/s/volt. Table illustrates depends value CLK_DR (Group CLK_RATIO (Group 18).
Equation
Table Function CLK_DR CLK_RATIO
CLK_DR[1:0]
2CLK_RATIO 2CLK_RATIO 2CLK_RATIO
Channel Clock Recovery
Choose natural
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