Datasheet Introduction Logic's L64767 SMATV Encoder highly-integr

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L64767 SMATV Encoder
Datasheet Introduction
Logic's L64767 SMATV Encoder highly-integrated device designed specifically Satellite Master Antenna Television (SMATV) applications. L64767 ideally suited application that requires low-power, highly integrated forward error correction (FEC) transmission encoder. Typical applications include rooftop SMATV systems, cable head-ends, optical networks fiber-deep networks. Figure shows basic SMATV system using L64767. device process input from either MPEG-2 transport encoder, satellite receiver, transmission network. Figure L64767 SMATV System
MPEG-2 Transport Cable Plant Passive Filter Analog
QPSK Satellite Receiver Logic L64704
L64767
Transmission Network
MD97.1
L64767 simplifies design process modulation encoding systems providing built-in signal processing capabilities byte-parallel, power saving architecture. L64767's ease will help system engineers create next generation time-to-volume sensitive digital products. contrast, previous solutions these systems forced system engineers many programmable discrete devices large circuit boards. These products were expensive power-intensive, both which unacceptable today's SMATV applications.
April 1999
Copyright 1995, 1996, 1997 Logic Corporation. rights reserved.
L64767 integrates CoreWare® processing elements that conform specifications described document DTVB1190/DTVC37, Revision Figure shows L64767's major functional blocks. Figure L64767 Functional Blocks
Data Sync/Error Flag Inserter Scrambler Diff. Encoder Mapper 10-bit Nyquist 10-bit Filter
ICLK Sync
Input
Circular FIFO Buffer
Reed8 Solomon Encoder
Convolutional Interleaver
Bytes m-tuple
OCLK Global Control Synchronization Start/Stop Signals Generation
Microprocessor Interface
Test Scan Chain
DATA[7:0] DTACK_N
READ
CS_N
AS_N
MD97.3
CoreWare processing elements L64767 comprise data processing chain device include:
Input synchronizer Circular FIFO buffer Sync/error flag inserter scrambler Reed-Solomon encoder Convolutional interleaver Bytes m-tuple converter Differential encoder mapper Nyquist filter
L64767 SMATV Encoder
addition processing chain, L64767 provides:
Global control synchronization components Microprocessor interface configuring monitoring internal
registers
Test scan chain
L64767 accept byte-parallel bit-serial input provides flexible input synchronization support. automatically search digital video broadcasting (DVB) user-programmable 8-bit sync code. Alternatively, L64767 external frame start signal indicate beginning frame input synchronization. inserting Reed-Solomon (RS) check words into circular FIFO buffer, device also MPEG-2 input stream without gaps, operate packets with gaps check words. length sync words sync blocks user-programmable, sync information reinserted needed. L64767 also provides error indication MPEG-2 transport packet errors. Using this bit, error flags from preceding device properly inserted MPEG-2 transport stream. L64767 process quadrature amplitude modulation (QAM) levels 128, 256. level user-programmable.
L64767 SMATV Encoder
Features
Benefits
SMATV DTVB1190/DTVC37,
Revision compliant
Directly connects Logic's satellite
receiver/FEC
Highly integrated, global
synchronization clock control
Allows low-cost external filters (4-fold
oversampling mode)
4-fold Nyquist filter oversampling Maskable interrupts error
conditions
ambient operation without special
cooling devices
Entire device individual SMATV
CoreWare processing blocks available
Individual module bypass
configuration modes
Easy interface most input sources Continuous data-in, continuous data-out
operation
IEEE 1149.1 JTAG interface testing User-controllable input
synchronization schemes
Input jitter handling Reed-Solomon
insertion 128-word circular FIFO buffer
Low-power low-cost surface
mount package
Mbaud operation Mbits/second serial data
input
Mbytes/second parallel data
input
128, modes Reed-Solomon encoder Frame sync-byte insertion Convolutional data interleaving depth
L64767 SMATV Encoder
Functional Description
This section provides brief description major blocks shown Figure
Input Synchronizer
shown Figure only input synchronizer driven input clock. other processing done based OCLK. OCLK four times symbol clock (SCLK) frequency based oversampling setting Nyquist filter. ICLK limited maximum 62.5 serial input mode parallel input mode. maximum symbol rate handled L64767 Mbaud. Therefore, OCLK limited 2-fold oversampling mode 4-fold oversampling mode. input format L64767 based data format specified MPEG-2 system layer standard relation transport framing structure. requires Reed-Solomon (204,188) protected transport packet consist bytes, including sync byte plus data bytes redundancy bytes. This basic format been adopted V4/MOD-B task force multiprogram satellite standard, group Europe. scrambled data stream, every eight synchronization words complemented (inverted) order define beginning scrambling sequence. descrambled stream contains inverted sync word. This MPEG-2 frame format basic input format L64767 device. device assumes that inserted sync byte chip input only have normal value, inverted one. insert gaps Reed-Solomon check bytes make them available input stream. synchronize input, following:
Send frame start pulse FSTARTIN forcing beginning
each Reed-Solomon code block. Whenever FSTARTIN asserted, L64767 reinserts sync byte into data stream inverts sync word every eight blocks, defined DVB.
L64767 SMATV Encoder
Specify unique sync byte inserted input stream
specified sync length distance Synchronizing L64767 with input pulse will byte block boundaries with pulse. sync byte define reinserted location pulse.
Circular FIFO Buffer
dual-ported implements circular FIFO buffer L64767. circular buffer write pointer driven ICLK, read pointer driven OCLK/4 OCLK/2 2-fold oversampling mode). Since there built-in mechanisms prevent collisions these pointers, must configure follow-up time proper initial setup pointer distance through phase-locked loop (PLL) module L64767. circular FIFO buffer illustrated Figure ensure that read pointer directly opposite write pointer most time properly programming delay values. This approach reduces effect frequency swings that occur during phases unstable input signal. also select smaller distances reduce system delay. Figure Circular Read/Write FIFO Buffer
Write Pointer
Read Pointer
Circular Buffer Words
Zero
MD97.16
initialize circular FIFO buffer, download cycles into read address pointer specify distance between read write pointers. this, specify FIFO delay value. When specifying this value, must Gray code numbers with even parity even number 1s). Both read write pointers Gray code counter-driven. write pointer initialized zero when read counter loaded.
L64767 SMATV Encoder
After initialization, both pointers independently. frequency relationship OCLK ICLK determines read write pointers advance. L64767 asserts FIFOALARM whenever pointers equal. This information also available through FIFO_ALARM_STORE bit.
Sync/Error Flag Inserter Scrambler
specifying sync insertion mode, instruct sync inserter insert sync bytes into data stream. Sync insertion minimizes errors sync bytes (even sync already inserted stream). sync bytes contained stream used synchronization device, regenerated sync bytes conceal single errors sync pattern. When uncorrectable error occurred (ERRORIN signal HIGH), L64767 sets both MPEG-2 transport_error_indicator packet (the most significant second byte packet) ERF_STORE. ERF_STORE check error occurred. also configure L64767 issue interrupt these errors continue processing without interrupt. scrambler module performs energy dispersion data stream. This module operates parallel mode. complete description functional characteristics this module refer standards document DTVB1190/DTVC37, Revision
Reed-Solomon Encoder
Reed-Solomon (RS) codes error correction using redundant check symbols code words. error correction codes systematic operate bytes rather than single-bit data streams. codes expressed, convention, numbers. first indicates total code word length (N). second indicates number message bytes (K). difference between these numbers number check bytes.
Convolutional Interleaver
interleaver rearranges ordering sequence symbols deterministic manner. Since interleaver convolutional, requires less memory than conventional RAM-intensive block type interleavers.
L64767 SMATV Encoder
interleaver periodic interleaver with following characteristics:
minimum separation interleaver output symbols
symbols that separated less than symbols interleaver input.
burst errors inserted channel results single
errors deinterleaver output.
Bytes m-tuple Converter
bytes m-tuples converter organizes bytes into symbols (tuples) bits. process data stream, L64767 feeds converter packets eight bytes together with valid signal from general control unit. order conversion process starts with oldest byte first (see document DTVB1190/DTVC37, Revision details).
Differential Encoder Mapper
This block performs differential encoding mapping QAM, specified document DTVB1190/DTVC37, Revision
Nyquist Filter
Nyquist filter shapes signals compliance. This filter implements square root raised cosine filtering function with roll factor 15%, specified DTVB1190/DTVC37, Revision other non-DVB filtering functions downloading appropriate filter coefficients. precision internal computations width output data suitable QAM. filter interpolates input data factor four that filter output data rate four times filter input data rate. specify interpolation factor (oversampling) using configuration register.
L64767 SMATV Encoder
Global Control Synchronization Module
L64767's clocking scheme uses independent clock signals (ICLK, OCLK) control incoming data, internal data processing, decoded output data. These clocks provide timing circular FIFO buffers that read write data. Data FIFO input latched with respect valid rising edges ICLK. Data FIFO output read with respect valid rising edge OCLK. FIFO control unit coordinates operation these asynchronous ports issues appropriate control signals. proper operation FIFO control unit, must ensure that OCLK frequency-locked ICLK. global control circuitry L64767 governs entire data path from MPEG-2 input source, through processing chain, final output from device. Global control ensures that output data stream continuous gaps between symbols), assuming that incoming data rate constant. output clock OCLK L64767 externally derived from input clock ICLK, kept sync through phase-locked loop (PLL) module locked appropriate ICLK versus OCLK ratio. Short term variations frequency offset handled 128-byte circular FIFO buffer. Other variations controlled external module. check overrun errors using FIFO collision detection feature. This provides immediate output when collision detected sends interrupt-generating event microprocessor interface.
Microprocessor Interface
L64767 bidirectional microprocessor interface that allows write read back from internal registers. During normal operation, L64767 requires interaction with microprocessor. However, must configure registers after reset operation guarantee that device will function properly. default operational mode L64767 used DVB-compliant operation QAM, four-fold oversampling. However, chip supports modes operation from QAM.
L64767 SMATV Encoder
internal registers configure through microprocessor define primary operational modes L64767. These modes configurations include following, among many others:
Input synchronization mode (whether lock synchronization sync
bytes input pulses)
Nyquist filter coefficients Delay value proper FIFO initialization
microprocessor interface related microcontrollers 68xxx family. L64767 dedicated supporting high-speed burst modes controllers with continuously asserted CS_N signal interface. L64767 detects error, error indicated output pins L64767 through microprocessor interface. Error indications like FIFOALARM signal helpful debugging troubleshooting.
Test Unit
built-in scan chain executes functionality test. pins SCAN_ENABLE, SCAN_MODE, used this purpose.
Signal Descriptions
This section describes L64767's interface signals. shown Figure these signals grouped into following categories:
Input signals (for example, those from Logic L64704
MPEG-2 MUX)
Output signals (for example, analog modulator) Control signals (including test pins) Microprocessor interface signals
Within each category, signals described alphabetical order signal mnemonic.
L64767 SMATV Encoder
Figure L64767 Signals
Microprocessor Interface DTACK_N DATA[7:0]
ADR[3:0]
INT_N
READ
CS_N
AS_N
FIFOALARM DIN[7:0] FIRSTOUT DVALIDIN FSTARTOUT Input from L64704 MPEG-2 ERRORIN FSTARTIN ICLK SMAENC_Q[9:0] SSTARTIN SYNCOK L64767 SMATV Encoder SCLK SMAENC_I[9:0] Output Analog Modulator
Control Test Signals
TESTPINS[6:0]
OCLK
PLL_OUT_CS
PLL_OUT_EX
PLL_OUT_LO
RESET
MD97.118
Input Signals
This section describes input signals L64767 from another device such Logic L64704 MPEG-2 MUX. DIN[7:0] Parallel/Serial Data Input This level-sensitive, 8-bit data parallel serial data input. Serial data DIN[0]. Data sampled rising edge ICLK.
L64767 SMATV Encoder
DVALIDIN
Clock Enable Input Input This active HIGH, level-sensitive data signal. When HIGH, L64767 accepts data from DIN[7:0] continuous basis. When LOW, L64767 halts data input internal FIFO buffer other data processing blocks. input from DIN[7:0] pins accepted. Error Detection Flag Input This active HIGH, level-sensitive data signal. When uncorrectable error occurs, ERRORIN HIGH. L64767 checks status ERRORIN first frame. error occurred, ERRORIN status copied MPEG-2 error indication required. External Sync Frame Start Input This active HIGH, level-sensitive data signal. Driving FSTARTIN HIGH marks beginning MPEG-2 transport packet. incoming bitstream contains unique synchronization words, must this indicate frame start. Synchronization with FSTARTIN forced into chip flywheel stabilized. sync insertion mode programmed, L64767 regenerates sync information inserts into data stream programmed microprocessor interface. Input Clock Input This positive, edge-triggered input clock. L64767 samples inputs DIN[7:0], DVALIDIN, ERRORIN, FSTARTIN, SSTARTIN ICLK's rising edge. ICLK either byte clock clock, depending programming SERIN (bit Register Sync Sequence Start Input This active HIGH signal that marks beginning new, fully reset sequence. signal's falling edge evaluated, internal sequences (inverted sync, scrambler, interleaver, differential encoder) restarted with next block start. SSTARTIN never asserted, internal sequences free after reset. This internal pull-down resistor.
ERRORIN
FSTARTIN
ICLK
SSTARTIN
L64767 SMATV Encoder
Output Signals
This section describes output signals from L64767 another device such analog modulator. FIFOALARM FIFO Collision Detected Output This alarm signal indicates FIFO control detected equal pointers read write access. collision probably caused unlocked external PLL-VCO circuitry. signal synchronized with SCLK-driven flip-flops output. First Block Sequence Output This signal occurs together with FSTARTOUT indicates head sync block, which just reset internal sequences, controlled SSTARTIN. FIRSTOUT acceptance SSTARTIN falling edge delayed internal processing modules.
FIRSTOUT
FSTARTOUT Frame Start Output FSTARTOUT driven HIGH during first symbol every sync frame. width FSTARTOUT reflects number bytes inserted parameter. one-cycle width indicates additionally inserted gaps. width means check bytes have been inserted. FSTARTOUT applied only synchronization word detection mode. synchronization forced FSTARTIN pulses, FSTARTOUT constantly LOW. SCLK Symbol Clock Output SCLK clock output signal that synchronous symbols bytes processed internally.
SMAENC_I[9:0] Symbol Modulation Output These signals provide 10-bit digital values digital filter output conversion analog modulation. SMAENC_Q[9:0] Symbol Modulation Output These signals provide 10-bit digital values digital filter output conversion analog modulation.
L64767 SMATV Encoder
SYNCOK
SYNC Detection/Phase Monitoring Output internal sync mode, when this signal HIGH, indicates correct lock input sync sequence, number track steps required synchronization fulfilled. synchronization forced FSTARTIN pulses, SYNCOK constantly LOW.
Control Signals
This section describes control signals L64767. OCLK Output Processing Clock Input This positive edge-triggered clock signal. L64767 internally processes data (through scrambler, interleaver, Reed-Solomon encoder) based fraction OCLK. Data outputs FSTARTOUT) referenced OCLK. OCLK independent ICLK.
PLL_OUT_CS Current Source Output This signal 4.5-mA charge pump output from phase/frequency detector. comparator frequencyand phase-sensitive. This signal normally 3-state level, drives positive negative current required. Depending configuration, current source inverted. PLL_OUT_EX Phase Sensitive EXOR Comparator Output This signal output from EXOR phase comparator. PLL_OUT_LO Phase Sensitive Lock Detector Output This signal output from lock detector. RESET Reset Input This level-sensitive data signal. resets internal data paths. Reset timing asynchronous device clocks does interfere with active clock edges ICLK OCLK reproducible output values. Reset affects configuration registers filter coefficients, which must downloaded again after reset.
L64767 SMATV Encoder
Test Signals
eight signals described below control functions such chip-level, full scan tests, JTAG tests, internal tests. Five pins (TCK, TDI, TDO, TMS, TRST) used JTAG tests. other three pins SCAN_ENABLE, SCAN_MODE, (test output enable). Note that L64767 normal functional mode when SCAN_ENABLE, SCAN_MODE, TCK, TDI, TMS, T_N, TRST left unconnected. SCAN_ENABLE Scan Enable Input This level-sensitive data signal with pull-down resistor. When HIGH, this signal enables scan chain shift. default normal operation, SCAN_ENABLE LOW. SCAN_MODE Scan Mode Input This level-sensitive signal with pull-down resistor. When this signal HIGH, chip switched scan test mode. default normal operation, SCAN_MODE LOW. Test Mode Clock Input When HIGH, this rising falling edge signal JTAG test mode clock. default normal operational mode, LOW. Test Data Input Input When HIGH, this level-sensitive signal provides JTAG data input. default normal operational mode, LOW. Test Data This JTAG data output. Output
Test Mode Select Input When HIGH, this level-sensitive signal enables JTAG test mode. default normal operational mode, LOW. Test Output Enable Input This active signal with pull-up resistor that disables test mode when LOW. switches 3-stated buffers high-impedance mode test device selection common bus. default normal operation, HIGH.
L64767 SMATV Encoder
TRST
JTAG Test Reset Input When HIGH, this level-sensitive data signal resets JTAG unit. default normal operational mode, TRST LOW.
Microprocessor Interface Signals
This section describes microprocessor interface signals L64767. ADR[3:0] Address Internal Registers Input This level-sensitive, 4-bit address L64767 uses along with 8-bit data DATA[7:0], read/write strobe (READ), chip select strobe (CS_N), address strobe (AS_N) read write internal registers. address lines used select among internal registers. Address Strobe Input This active address strobe input signal. latches address ADR[3:0] falling edge. Chip Select Input This active chip select strobe input signal. During read cycle, CS_N must access on-chip data registers. controller latch data from L64767 with rising edge CS_N. During write cycle, CS_N must active prior data being valid from controller L64767. After data minimum setup time, CS_N HIGH will strobe data. There minimum write time allow internal synchronization. Data [7:0] Bidirectional This level-sensitive data signal. bidirectional data used input when writing data chip, output when chip read. When being read written, data lines 3-stated. Data Acknowledge Output This active output signal indicating that transaction data completed.
AS_N
CS_N
DATA[7:0]
DTACK_N
L64767 SMATV Encoder
INT_N
Interrupt Request Output L64767 drives INT_N when interrupt enabled interrupt condition occurs. INT_N open drain output, requiring external pull-up resistor operation. Read/Write Strobe Input This level-sensitive data signal active write strobe input signal. microprocessor must drive this signal write L64767's registers, must drive HIGH read from them.
READ
Specifications
This section presents electrical, timing, pinout, packaging specifications L64767.
Electrical Requirements
This section lists electrical requirements L64767. tables this section specify electrical requirements L64767 encoder.
Table provides L64767's absolute maximum electrical
temperature ratings.
Table provides L64767's recommended operating conditions. Table lists L64767's characteristics.
Table Absolute Maximum Ratings
Symbol TSTG Parameter supply Input voltage input current Storage temperature range (plastic) Limits1 -0.3 -0.3 +0.3 +125 Unit
Referenced VSS.
L64767 SMATV Encoder
Table Recommended Operating Conditions
Symbol Parameter supply Ambient temperature Limits +4.75 +5.25 Unit
values Table note that L64767 produced with Logic's LCB300K HCMOS process, which characterized 0.6-micron drawn gate-length (0.45-micron effective channel length). Values table specified ambient temperature over specified range. actual product characterization L64767 available time this printing. Table Operating Characteristics
Symbol Parameter Voltage input LOW, Voltage input HIGH, Voltage input LOW, CMOS Voltage input HIGH, CMOS Voltage output HIGH Voltage output Current 3-state leakage with pull-down Current input leakage Current input leakage with pull-up Current input leakage with pull-down Quiescent supply current Dynamic supply current -4.0 Max, VOUT Max, Max, Max, ICLK 62.5 MHz, OCLK 31.25 MHz, -220 Condition1 Units
Power dissipation
Specified ambient temperature over specified range.
L64767 SMATV Encoder
Timing
This section presents L64767 timing information, which simulated using microprocessor. numbers column Table refer timing parameters shown timing diagrams that follow. parameters this table apply 4.75 5.25 output load actual product characterization L64767 available time this printing. Table L64767 Timing Parameters
31/62 Parameter tCYCLE tPWH tPWL tI_CYCLE tI_PWH tI_PWL tI_S tI_H tRWH Description Clock Cycle OCLK Clock Pulse Width HIGH OCLK Clock Pulse Width OCLK Clock Cycle ICLK Clock Pulse Width HIGH ICLK Clock Pulse Width ICLK Input Setup Time ICLK Input Hold ICLK Output Delay from OCLK Reset Pulse Width HIGH Wake-up time after RESET, used initialization during microprocessor configuration access READ Setup Before CS_N ADR[3:0] Setup Before AS_N 1024 2244 Unit ICLK cycles with DVALIDIN HIGH OCLK cycles
tSURCS tSUA
(Sheet
L64767 SMATV Encoder
Table
(Cont.) L64767 Timing Parameters
31/62
Parameter tHLDA tDCSDTL tHLDD
Description ADR[3:0] Hold After AS_N CS_N DTACK_N Write Data Hold After CS_N HIGH
tCYCLE tCYCLE
tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
Unit
tCYCLE_CS Minimum CS_N Width tHLDRCS tWRREC tDCSDTH tDELZL tDELD tDELLZ tSUD tTDLY READ Hold After CS_N HIGH Write Recovery Time CS_N HIGH DTACK_N HIGH CS_N Data Driven CS_N Data Valid CS_N HIGH Data 3-State Data Setup Before CS_N Change Delay from
(Sheet
Figure L64767 Synchronous Timing
OCLK ICLK Inputs Outputs
MD97.33
L64767 SMATV Encoder
Figure L64767 Read Cycle
CS_N DATA[7:0] Valid
AS_N ADR[3:0]
Valid
READ DTACK_N
MD97.34
Figure L64767 Write Cycle
CS_N DATA[7:0] Valid
AS_N ADR[3:0]
Valid
READ DTACK_N
MD97.35
L64767 SMATV Encoder
Figure L64767 RESET Timing Diagram
RESET
MD97.36
Figure L64767 3-State Delay Timing
DATA[7:0] SMAENC_I[9:0] SMAENC_Q[9:0]
Pinout Packaging
Figure shows signal pins L64767 SMATV encoder. shows location, number, signal each 100-pin MQUAD package. This pinout followed mechanical dimensions L64767's package.
L64767 SMATV Encoder
SMAENC_I0 SMAENC_I1 SMAENC_I2 SMAENC_I3 SMAENC_I4 SMAENC_I5 SMAENC_I6 SMAENC_I7 SMAENC_I8 SMAENC_I9 SMAENC_Q0 SMAENC_Q1 SMAENC_Q2 SMAENC_Q3 SMAENC_Q4 SMAENC_Q5 SMAENC_Q6 SMAENC_Q7 SMAENC_Q8 SMAENC_Q9
97.L64767.WEa
DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 CS_N READ AS_N ADR3 ADR2 ADR1 ADR0 DATA7 SCAN_ENABLE DIN0 DIN1 SCAN_MODE DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 ICLK DVALIDIN RESET ERRORIN FSTARTIN SSTARTIN TRST PLL_OUT_CS
Figure 100-Pin MQUAD Pinout
L64767 SMATV Encoder
View
PLL_OUT_EX PLL_OUT_LO FIRSTOUT FSTARTOUT FIFOALARM SCLK OCLK DTACK_N INT_N SYNCOK
Mechanical Dimensions
Figure provides packaging information 100-pin MQUAD (WE, RECTANGULAR) L64767 chip. Figure 100-Pin MQUAD Mechanical Drawing (Cavity
board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
MD97.WE-1
L64767 SMATV Encoder
Figure (Cont.) 100-Pin MQUAD Mechanical Drawing (Cavity
board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
MD97.WE-2
L64767 SMATV Encoder
L64767 Descriptions
This section describes signal pins L64767 SMATV encoder. Table summarizes pins L64767. table provides signal types both output input pins, drive capacity outputs. summary followed Table list, which relates signal each number 100-pin MQUAD package. Table L64767 Description Summary
Drive (mA)
Mnemonic DIN[7:0] DVALIDIN ERRORIN FSTARTIN ICLK SSTARTIN FIFOALARM FIRSTOUT FSTARTOUT SCLK SMAENC_I[9:0] SMAENC_Q[9:0] SYNCOK OCLK PLL_OUT_CS PLL_OUT_EX
Description Parallel/Serial Data Clock Enable Input Error Detection Flag External Sync Frame Start Input Clock Sync Sequence Start FIFO Collision Detected First Block Sequence Frame Start Symbol Clock Symbol Modulation Symbol Modulation Sync Detection/Phase Monitoring Output Processing Clock Current Source Phase Sensitive EXOR Comparator
Type Input Input Input Input Input Input with pull-down Output Output Output Output 3-State Output 3-State Output Output Input 3-state Current Source Output
Active HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH 3-state HIGH
(Sheet
L64767 SMATV Encoder
Table
(Cont.) L64767 Description Summary
Drive (mA)
Mnemonic PLL_OUT_LO RESET SCAN_ENABLE SCAN_MODE TRST ADR[3:0] AS_N CS_N DATA[7:0] DTACK_N INT_N READ (Sheet
Description Phase Sensitive Lock Detector Reset Scan Enable Scan Mode Test Mode Clock Test Data Input Test Data Test Mode Select Test Output Enable JTAG Test Reset Address Internal Registers Address Strobe Chip Select Data [7:0] Data Acknowledge Interrupt Request Read/Write Strobe
Type Output Input Input with pull-down Input with pull-down Input with pull-down Input with pull-down Output Input with pull-down Input with pull-up Input with pull-down Input Input Input Bidirectional Output Open Drain, driving Input
Active HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH
L64767 SMATV Encoder
Table List 100-pin MQUAD
Signal SMAENC_I0 SMAENC_I1 SMAENC_I2 SMAENC_I3 SMAENC_I4 SMAENC_I5 SMAENC_I6 SMAENC_I7 SMAENC_I8 SMAENC_I9 SMAENC_Q0 SMAENC_Q1 SMAENC_Q2 SMAENC_Q3 SMAENC_Q4 SMAENC_Q5 SMAENC_Q6 Signal SMAENC_Q7 SMAENC_Q8 SMAENC_Q9 SYNCOK INT_N DTACK_N OCLK SCLK FIFOALARM FSTARTOUT FIRSTOUT PLL_OUT_LO PLL_OUT_EX Signal PLL_OUT_CS TRST SSTARTIN FSTARTIN ERRORIN RESET DVALIDIN ICLK DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 SCAN_MODE DIN1 DIN0 Signal SCAN_ENABLE DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 CS_N READ AS_N ADR3 ADR2 ADR1 ADR0
L64767 SMATV Encoder
Notes
L64767 SMATV Encoder
Notes
L64767 SMATV Encoder
Notes
L64767 SMATV Encoder
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Datasheet Introduction Logic's L64767 SMATV Encoder highly-integr

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