AS7C3512 AS7C3512L voltage CMOS SRAM Preliminary information Feat

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AS7C3512 AS7C3512L voltage CMOS SRAM Preliminary information Feat

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High Performance 3.3V CMOS SRAM
AS7C3512 AS7C3512L
voltage CMOS SRAM Preliminary information Features
Organization: 65,536 words bits Single ±0.3V power supply tolerant specification High speed 12/15/20/25/35 address access time 3/4/5/6/8 output enable access time Very power consumption Active: max, cycle Standby: max, CMOS max, CMOS I/O, version 2.0V data retention Equal access cycle times Easy memory expansion with CE1, inputs TTL-compatible, three-state Ideal cache portable computing power reduction during idle mode 32-pin JEDEC standard packages PDIP protection >2000 volts Latch-up current >200
Logic block diagram
Input buffer
arrangement
DIP,
decoder
Array (524,288)
Sense
I/O0 Column decoder Control circuit
Selection guide
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current
Shaded areas contain advance information.
7C3512-12
7C3512-15
7C3512-20
7C3512-25
AS7C3512
I/O7
I/O0 I/O1 I/O2
I/O7 I/O6 I/O5 I/O4 I/O3
7C3512-35
Unit
ALLIANCE SEMICONDUCTOR
AS7C3512 AS7C3512L Functional description
AS7C3512 3.3V high performance CMOS 524,288-bit Static Random Access Memory (SRAM) organized 65,536 words bits. designed memory applications requiring fast data access voltage, including PentiumTM, PowerPCTM, portable computing. Alliance's advanced circuit design process techniques permit 3.3V operation without sacrificing performance operating margins. device enters standby mode when HIGH LOW. CMOS standby mode consumes (1.8 version). Normal operation offers power reduction after initial access, resulting significant power savings during idle, suspend, stretch mode. Both versions AS7C3512 offer 2.0V data retention. Equal address access cycle times (tAA, tRC, tWC) 12/15/20/25/35 with output enable access times (tOE) 3/4/5/6/8 ideal high performance applications. active high chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. write cycle accomplished asserting write enable (WE) both chip enables (CE1, CE2). Data input pins I/O0-I/O7 written rising edge (write cycle active-to-inactive edge (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting output enable (OE) both chip enables (CE1, CE2), with write enable (WE) HIGH. chip drives pins with data word referenced input address. When either chip enable output enable inactive, write enable active, output drivers stay high-impedance mode. chip inputs outputs TTL-compatible, tolerant. Operation from single 3.3±0.3V supply. AS7C3512 packaged high volume industry standard packages.
Absolute maximum ratings
Parameter Power supply voltage relative Input voltage relative Power dissipation Storage temperature (plastic) Temperature under bias output current Symbol Tstg Tbias Iout -0.5 -0.5 +4.6 +6.0 +150 Unit
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Truth table
Data High High High Dout Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable Read Write
Key: Don't Care, LOW, HIGH
AS7C3512 AS7C3512L Recommended operating conditions
Parameter Supply voltage Input voltage Symbol -0.5 +70°C) Unit
-2.0V pulse width less than tRC/2.
operating characteristics1
Parameter Input leakage current Output leakage current Operating power supply current Standby power supply current Symbol Test conditions Max, |ILI|
|ILO| Max,
(VCC 3.3±0.3V, +70°C) Unit
VIL,
Vout
VIL, VIH, fmax, Iout VIL, fmax VCC-0.2V 0.2V, 0.2V VCC-0.2V,
ISB1
Output voltage
Shaded areas contain advance information.
Capacitance2
Parameter Input capacitance capacitance Symbol CI/O Signals CE1, CE2,
MHz, Room temperature, 3.3V) Test conditions Vout Unit
AS7C3512 AS7C3512L Read cycle3,9,12
Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change Chip enable (CE1) output Chip enable (CE2) output Chip disable (CE1) output High Chip disable (CE2) output High Output enable output Output disable output High Chip enable power time Chip disable power down time
Shaded areas contain advance information
(VCC 3.3±0.3V, +70°C) Symbol tACE1 tACE2 tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ Unit Notes
Read waveform 13,6,7,9,12
Address Dout
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
Address controlled
Data Valid
Read waveform 23,6,8,9,12
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
controlled
tOLZ
tACE1, tACE2 Dout tCLZ1, tCLZ2 Supply Current
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tOHZ tCHZ1, tCHZ2 Data Valid
AS7C3512 AS7C3512L Write cycle11,12
Parameter Write cycle time Chip enable (CE1) write Chip enable (CE2) write Address setup write Address setup time Write pulse width Address hold from write Data valid write Data hold time Write enable output High Output active from write Symbol tCW1 tCW2 (VCC 3.3±0.3V, +70°C) Unit Notes
Write waveform 110,11,12
Address Dout
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
controlled
Data Valid
Write waveform 210,11,12
Address Dout
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
controlled
tCW1, tCW2
Data Valid
AS7C3512 AS7C3512L Data retention characteristics
Parameter data retention Data retention current Chip deselect data retention time Operation recovery time Input leakage current Symbol ICCDR tCDR Test Conditions 2.0V VCC-0.2V 0.2V VCC-0.2V 0.2V 1200 Unit
Data retention waveform
Data Retention Mode 3.0V tCDR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
2.0V
3.0V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
test conditions
Output load: Figure except tCLZ tCHZ Figure Input pulse level: 3.0V. Figure Input rise fall times: Figure Input output timing reference levels: 1.5V.
+3.3V Dout Thevenin equivalent: Dout +1.72V +3.3V Dout Figure Output Load +3.3V
Figure Input Waveform
*including scope capacitance Figure Output Load tCLZ, tCHZ
Notes
During power-up, pull-up resistor required meet specification. This parameter sampled 100% tested. test conditions, Test Conditions, Figures tCLZ tCHZ specified with Figure Transition measured ±500mV from steady-state voltage. This parameter guaranteed tested. HIGH read cycle. HIGH read cycle. Address valid prior coincident with transition transition HIGH. read cycle timings referenced from last valid address first transitioning address. must HIGH during address transitions. write cycle timings referenced from last valid address first transitioning address. have identical timing.
AS7C3512 AS7C3512L Typical characteristics
Normalized ICC, Supply voltage Normalized access time supply voltage Normalized ICC, Normalized supply current ICC, supply voltage Ambient temperature (°C) Normalized access time ambient temperature Normalized supply current ICC, ambient temperature 3.30V Normalized supply current ISB1 ambient temperature
Normalized ISB1 (log scale)
0.04 Ambient temperature (°C)
Normalized access time
Normalized access time
Normalized supply current cycle frequency 1/tWC
25°C
Ambient temperature (°C) Output sink current output voltage
Normalized
3.3V
3.3V 25°C
Supply voltage Output source current output voltage
Cycle frequency (MHz)
Typical access time change output capacitive loading Change (ns) 3.3V
Output source current (mA)
Output sink current (mA)
3.3V 25°C
3.3V 25°C
1.65 Output voltage
1.65 Output voltage
Capacitance (pF)
1000
AS7C3512 AS7C3512L
Ordering information
Package Access Time Plastic DIP, Plastic SOJ, AS7C3512-12PC AS7C3512L-12PC AS7C3512-12JC AS7C3512L-12JC AS7C3512-15PC AS7C3512L-15PC AS7C3512-15JC AS7C3512L-15JC AS7C3512-20PC AS7C3512L-20PC AS7C3512-20JC AS7C3512L-20JC AS7C3512-25PC AS7C3512L-25PC AS7C3512-25JC AS7C3512L-25JC AS7C3512-35PC AS7C3512L-35PC AS7C3512-35JC AS7C3512L-35JC
Shaded areas contain advance information.
Part numbering system
AS7C SRAM prefix Blank supply 3.3V supply Device number Access time Package: PDIP Commercial temperature range,
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Alliance Semiconductor reserves right make changes this data sheet time improve design supply best product possible. Publication advance information does constitute committment produce supply product described. company cannot assume responsibility circuits shown represent that they free from patent infringement. Alliance products authorized critical components life support devices systems without express written approval president Alliance. ProMotion® Alliance logo registered trademarks Alliance Semiconductor Corporation. other trademarks property their respective holders.
3099 North First Street Printed U.S.A.
Jose, 95134 (408) 383-4900 (408) 383-4999 Copyright 1996 rights reserved.
ALLIANCE SEMICONDUCTOR
www.alsc.com June 1996

AS7C3512 AS7C3512L voltage CMOS SRAM Preliminary information Feat

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