AS7C31024 AS7C31024L voltage CMOS SRAM (Common I/O) Features

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AS7C31024 AS7C31024L voltage CMOS SRAM (Common I/O) Features

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High Performance 3.3V CMOS SRAM
AS7C31024 AS7C31024L
voltage CMOS SRAM (Common I/O) Features
Organization: 131,072 words bits Single ±0.3V power supply tolerant specification High speed 12/15/20/25/35 address access time 3/4/5/6/8 output enable access time Very power consumption Active:270 max, cycle) Standby: max, CMOS max, CMOS I/O, version 2.0V data retention Equal access cycle times Easy memory expansion with CE1, inputs TTL-compatible, three-state Ideal cache, modem, portable computing power reduction during idle mode 32-pin JEDEC standard packages PDIP TSOP protection >2000 volts Latch-up current >200
Logic block diagram
Input buffer
arrangement
TSOP
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
DIP,
I/O7 decoder
Array (1,048,576)
I/O0
Column decoder
Selection guide
Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current
Shaded areas contain advance information.
7C31024-12
7C31024-15
7C31024-20
Control circuit
I/O0 I/O1 I/O2
I/O7 I/O6 I/O5 I/O4 I/O3
AS7C31024
7C31024-25
7C31024-35
AS7C31024
Sense
Unit
ALLIANCE SEMICONDUCTOR
AS7C31024
Functional description
AS7C31024 3.3V high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) organized 131,072 words bits. designed memory applications requiring fast data access voltage, including Pentium PowerPCTM, portable computing. Alliance's advanced circuit design process techniques permit 3.3V operation without sacrificing performance operating margins. device enters standby mode when HIGH LOW. CMOS standby mode consumes (3.6mW version). Normal operation offers power reduction after initial access, resulting significant power savings during idle, suspend, stretch mode. Both versions AS7C31024 offer 2.0V data retention. Equal address access cycle times (tAA, tRC, tWC) 12/15/20/25/35 with output enable access times (tOE) 3/4/5/6/8 ideal high performance applications. active high chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. write cycle accomplished asserting write enable (WE) both chip enables (CE1, CE2). Data input pins I/O0-I/O7 written rising edge (write cycle active-to-inactive edge (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting output enable (OE) both chip enables (CE1, CE2), with write enable (WE) HIGH. chip drives pins with data word referenced input address. When either chip enable output enable inactive, write enable active, output drivers stay high-impedance mode. chip inputs outputs TTL-compatible, tolerant. Operation from single 3.3±0.3V supply. AS7C31024 packaged high volume industry standard packages.
Absolute maximum ratings
Parameter Power supply voltage relative Input voltage relative Power dissipation Storage temperature (plastic) Temperature under bias output current Symbol Tstg Tbias Iout -0.5 -0.5 +4.6 +6.0 +150 Unit
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability
Truth table
Data High High High Dout Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable Read Write
Key: Don't Care, LOW, HIGH
AS7C31024
Recommended operating conditions
Parameter Supply voltage Input voltage
-2.0V pulse width less than tRC/2.
+70°C Symbol -0.5 Unit
operating characteristics1
Symbol Test Conditions Max, |ILI| VIL, Output |ILO| Max, leakage current Vout Operating VIL, VIH, power supply fmax, Iout current VIL, fmax Standby power supply VCC-0.2V 0.2V, current ISB1 0.2V VCC-0.2V, Output voltage Parameter Input leakage current
3.3±0.3V, +70°C Unit
Capacitance2
Parameter Input capacitance capacitance Symbol CI/O
MHz, Room temperature, 3.3V Signals Test Conditions CE1, CE2, Vout Unit
AS7C31024 Read cycle3,9,12
Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output Hold from address change output HIGH output HIGH output High output High output HIGH output High Power time Power down time
Shaded areas contain advance information.
(VCC 3.3±0.3V, +70°C) Symbol tACE1 tACE2 tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ Unit Notes
Read waveform 13,6,7,9,12
Address Dout
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
Address controlled
Data Valid
Read waveform 23,6,8,9,12
tRC1 AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA tOLZ
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
controlled
tOHZ
tACE1, tACE2 Dout tCLZ1, tCLZ2 Current supply Data Valid
tCHZ1, tCHZ2
AS7C31024 Write cycle11,12
Parameter Write cycle Time Chip enable (CE1) write Chip enable (CE2) write Address setup write Address setup time Write pulse width Address hold from write Data valid write Data hold time Write enable output High Output active from write Symbol tCW1 tCW2
(VCC 3.3±0.3V, +70°C) Unit Notes
Write waveform 110,11,12
Address Dout
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
controlled
Data Valid
Write waveform 210,11,12
Address
controlled
tCW1, tCW2
Dout
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
Data Valid
AS7C31024
Data retention characteristics
Parameter data retention Data retention current Chip enable data retention time Operation recovery time Input leakage current Symbol ICCDR tCDR Test Conditions 2.0V VCC-0.2V 0.2V VCC-0.2V 0.2V 2500 Unit
Data retention waveform
Data retention mode 3.0V tCDR AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
2.0V
3.0V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AS7C31024-07
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
test conditions
Output load: Figure except tCLZ tCHZ Figure Input pulse level: 3.0V. Figure Input rise fall times: Figure Input output timing reference levels: 1.5V.
+3.3V Dout +3.3V Dout Figure Output load Thevenin equivalent: Dout +1.72V +3.3V
*including scope capacitance
Figure Input waveform
Figure Output load tCLZ, tCHZ
Notes
During power-up, pull-up resistor required meet specification. This parameter sampled 100% tested. test conditions, Test Conditions, Figures tCLZ tCHZ specified with Figure Transition measured ±500mV from steady-state voltage. This parameter guaranteed tested. HIGH read cycle. HIGH read cycle. Address valid prior coincident with transition LOW. read cycle timings referenced from last valid address first transitioning address. must HIGH during address transitions. write cycle timings referenced from last valid address first transitioning address. have identical timing.
AS7C31024
Typical characteristics
Normalized ICC, Supply voltage Normalized access time supply voltage Normalized ICC, Normalized supply current ICC, supply voltage Ambient temperature (°C) Normalized access time ambient temperature Normalized supply current ICC, ambient temperature 3.30V Normalized supply current ISB1 ambient temperature
Normalized ISB1 (log scale)
0.04 Ambient temperature (°C)
Normalized access time
Normalized access time
Normalized supply current cycle frequency 1/tWC
25°C
Ambient temperature (°C) Output sink current output voltage
Normalized
3.3V
3.3V 25°C
Supply voltage Output source current output voltage
Cycle frequency (MHz)
Typical access time change output capacitive loading Change (ns) 3.3V
Output source current (mA)
Output sink current (mA)
3.3V 25°C
3.3V 25°C
1.65 Output voltage
1.65 Output voltage
Capacitance (pF)
1000
AS7C31024
Ordering information
Package Access Time Plastic DIP, Plastic SOJ, TSOP 8x20 AS7C31024-12PC AS7C31024L-12PC AS7C31024-12JC AS7C31024L-12JC AS7C31024-12TC AS7C31024L-12TC AS7C31024-15PC AS7C31024L-15PC AS7C31024-15JC AS7C31024L-15JC AS7C31024-15TC AS7C31024L-15TC AS7C31024-20PC AS7C31024L-20PC AS7C31024-20JC AS7C31024L-20JC AS7C31024-20TC AS7C31024L-20TC AS7C31024-25PC AS7C31024L-25PC AS7C31024-25JC AS7C31024L-25JC AS7C31024-25TC AS7C31024L-25TC AS7C31024-35PC AS7C31024L-35PC AS7C31024-35JC AS7C31024L-35JC AS7C31024-35TC AS7C31024L-35TC
Part numbering system
AS7C SRAM prefix
DOMESTIC REPS ALABAMA
Concord Component (205) 772-8883
Blank supply KANSAS 3.3V supply
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1024 Device number JERSEY
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South Electro Sales ARKANSAS Representatives, distributors, sales offices Electro Tech (317) 921-5000 Southern States Marketing
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SALES OFFICES HEADQUARTERS
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Alliance Semiconductor reserves right make changes this data sheet time improve design supply best product possible. Publication advance information does constitute committment produce supply product described. company cannot assume responsibility circuits shown represent that they free from patent infringement. Alliance products authorized critical components life support devices systems without express written approval president Alliance. ProMotion® Alliance logo registered trademarks Alliance Semiconductor Corporation. other trademarks property their respective holders.
3099 North First Street Printed U.S.A.
Jose, 95134 (408) 383-4900 (408) 383-4999 Copyright 1996 rights reserved.
ALLIANCE SEMICONDUCTOR
www.alsc.com June 1996

AS7C31024 AS7C31024L voltage CMOS SRAM (Common I/O) Features

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