SCBS186C JANUARY 1991 REVISED JUNE 1996 description These oc

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SCBS186C JANUARY 1991 REVISED JUNE 1996 description These oc

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SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS186C JANUARY 1991 REVISED JUNE 1996
description
These octal transparent D-type latches with 3-state outputs designed specifically driving highly capacitive relatively low-impedance loads. They particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers.
State-of-the-Art EPIC-BBiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Drive Outputs (-32-mA IOH, 64-mA IOL) Protection Exceeds 2000 MIL-STD-883C, Method 3015; Exceeds Using Machine Model Package Options Include Plastic Small-Outline (DW) Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Plastic Ceramic DIPs, Ceramic Flat Packages
SN54ABT533 PACKAGE SN74ABT533A PACKAGE (TOP VIEW)
SN54ABT533 PACKAGE (TOP VIEW)
When latch-enable (LE) input high, outputs follow complements data inputs. When taken low, outputs latched inverse levels inputs. SN54ABT533 SN74ABT533A provide inverted data outputs. buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latches. Previously stored data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. SN74ABT533A available TI's shrink small-outline package (DB), which provides same count functionality standard small-outline packages less than half printed-circuit-board area. SN54ABT533 characterized operation over full military temperature range -55°C 125°C. SN74ABT533A characterized operation from -40°C 85°C.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC-B trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS186C JANUARY 1991 REVISED JUNE 1996
FUNCTION TABLE (each latch) INPUTS OUTPUT
logic symbol
logic diagram (positive logic)
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS186C JANUARY 1991 REVISED JUNE 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high state power-off state, -0.5 Current into output state, SN54ABT533 SN74ABT533A Input clamp current, Output clamp current, Maximum power dissipation 55°C still air) (see Note package package package Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero. more information, refer Package Thermal Considerations application note Advanced BiCMOS Technology Data Book.
recommended operating conditions (see Note
SN54ABT533 Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate SN74ABT533A UNIT ns/V
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS186C JANUARY 1991 REVISED JUNE 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER IOZH IOZL Ioff ICEX TEST CONDITIONS Outputs high Outputs high input Other inputs Outputs Outputs disabled Outputs enabled Outputs disabled Control inputs -140 0.55 0.55* ±150 -180 -180 0.55 0.55 ±150 -180 25°C -1.2 SN54ABT533 -1.2 SN74ABT533A -1.2 UNIT
products compliant MIL-PRF-38535, this parameter does apply. typical values more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure1)
SN54ABT533 25°C Pulse duration, high Setup time, data before Hold time, data after Data high Data high UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS186C JANUARY 1991 REVISED JUNE 1996
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure1)
SN74ABT533A 25°C Pulse duration, high Setup time, data before Hold time, data after Data high Data high UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN54ABT533 PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
SN74ABT533A PARAMETER FROM (INPUT) (OUTPUT) 25°C tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABT533, SN74ABT533A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SCBS186C JANUARY 1991 REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note TEST Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES
Input
tPLH tPHL tPHL tPLH
Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH
tPLZ tPHZ
Output
Output
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

SCBS186C JANUARY 1991 REVISED JUNE 1996 description These oc

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