PRELIMINARY IDT71F432 Uses IDT's Fusion Memory technology speed g

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PRELIMINARY IDT71F432 Uses IDT's Fusion Memory technology speed g

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Fusion MemorySYNCHRONOUS PIPELINED CACHE
PRELIMINARY IDT71F432
Uses IDT's Fusion Memory technology speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write 3-1-1-1-1-1-1-1. extended pipelined operation Refresh overhead consumes less than 0.5% cycles Pinout superset industry standard PBSRAM Interchangeable with PBSRAM designs Compatible with MoSys MCachedevices operating standby power consumption power standard PBSRAM Packaged JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP)
DESCRIPTION:
IDT71F432 CacheRAMis high-performance, lowpower replacement standard pipelined burst SRAM (PBSRAM) cache applications. 71F432 built using IDT's Fusion Memory technology, which combines
performance SRAM with cost structure DRAM. fundamentally compatible with standard PBSRAM, with additional features accommodate internal DRAM operation memory. These additional features defined that 71F432 compatible system controllers properly implemented boards work transparently with either 71F432 PBSRAM cache memory applications. Four pins, identified Connect (NC) standard PBSRAM specifications, used support 71F432 operation. These pins host W/R#, RESET# proprietary functions labeled When using standard PBSRAM, these pins have effect associated functions 71F432-compatible chipset activated. 71F432 supports PBSRAM operating modes, including burst read (3-1-1-1), burst write (3-1-1-1) pipelined burst read write (3-1-1-1-1-1.). with DRAM devices, refresh required. memory accessible during refresh interval. System performance reduction refresh negligible less than 0.5%. nearly invisibly, using either on-chip circuitry circuitry chip used with memory device. performance penalty typically less than 0.5%. does performance Fusion Memory cache RAMs compare with synchronous burst SRAMS? Fusion Memory devices equal performance SRAMs they designed replace. Fusion Memory PBSRAMs interchangeable? system designed Fusion Memory cache RAMs standard PBSRAMs instead. What difference between MoSys MCacheand IDT's Fusion Memory? MCache MoSys' trademark their cache memory devices. Fusion Memory IDT's trademark underlying technology. will technology other products besides cache RAMs. IDT71F432 MoSys' MCache devices interchangeable.
ABOUT IDT'S Fusion Memory TECHNOLOGY:
What Fusion Memory? Fusion Memory kind memory technology that combines high performance ease-of-use SRAM with manufacturing costs DRAM. What advantages Fusion Memory? Fusion memory products about much power SRAMs they built dice that about size. smaller size only makes them lower cost, also means that higher levels integration possible than with SRAM. Fusion Memory chips much smaller than SRAM? Traditional SRAM uses four transistors make each memory cell. Fusion Memory uses only transistor each memory cell, memory array itself only about size SRAM. Fusion Memory same Dynamic Memory? exactly. While both Fusion Memory DRAMs single-transistor dynamic cells storage, Fusion Memories much different designs surrounding circuitry, such address drivers, sense amps, control circuitry. This gives Fusion Memory performance level that much higher than DRAM. Fusion Memory uses dynamic storage, there refresh cycles? Yes, refresh control handled automatically
Fusion Memory
SRAM
Performance
DRAM
logo registered trademark Fusion Memory CacheRAM trademarks Integrated Device Technology Pentium trademark Intel Corp. Fusion MemoryMCache trademark MoSys, Inc.
Cost
Provides SRAM Performance DRAM Cost
COMMERCIAL TEMPERATURE RANGE
©1996
1996
DSC-3555/2
IDT71F432 32Kx32 PIPELINED FUSION MEMORY CACHE
COMMERCIAL TEMPERATURE RANGE
256KB CACHE BLOCK DIAGRAM
PROCESSOR
D[63:32] ADS# W/R# BE#[8:5] RESET# A[17:3] D[31:0] ADS# W/R# BE#[4:1] A[17:3]
SRAM CHIPSET CACHE CONTROLLER
ADSC# ADV# BWE# CS1#
IDT71F432
32Kx32
RESET#
IDT71F432
32Kx32
DESCRIPTION SUMMARY
SYMBOL CS0, CS1# BWE# BW1#, BW2#, BW3#, BW4# ADV# ADSC# ADSP# I/O31-I/O0 DESCRIPTION Address Inputs Chip Enable Chip Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Data Input/Output TYPE Input Input Input Input Input Input Input Input Input Input Input NUMBER 100, RESET# W/R# VDD5 Reserved LBO# (burst order) Reserved (sleep) Host Reset Signal Host W/R# Function Function Power 3.3V Power Ground Input Input Special Special
3555
IDT71F432 32Kx32 PIPELINED FUSION MEMORY CACHE
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD5 VTERM TBIAS TSTG IOUT Rating VDD5 Voltage with Respect Voltage with Respect Terminal Voltage with Respect Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation Output Current Com'l. -0.5 VDD+0.5 +125 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Symbol VDD5 Parameter Supply Voltage Supply Voltage Supply Voltage Input High Voltage Input Voltage Min. Typ. 4.75 3.135 -0.3
Max. Unit 5.25
VDD+0.3
NOTES: 3555 Power sequencing. VDD5 must times, including during power (max.) must observed times, including during power (min.) -1.0V pulse width less than tCYC/2, once cycle.
NOTE: 3555 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE (VDD 3.3V +10/-5%, VDD5
Symbol |ILI| |ILO| Parameter Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Test Condition Max., Outputs disabled, VOUT VDD, Max. 5mA, Min. -5mA, Min.
3555
Min.
Max.
Unit
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(1, (VDD 3.3V +10/-5%, VDD5
Symbol Parameter Operating Supply Current Idle Supply Current Clock Stopped Supply Current Test Condition Device Selected, VLD, Outputs Open, Max., VDD5 Max., fMAX Device Selected, ADSP#, ADSC#, GW#, BW#s, ADV# VHD, Other Inputs VHD, Outputs Open, VDD, VDD5 Max., fMAX VHD, Outputs Open, Max., VDD5 Max., Supply 3.3V Supply Unit
ISB1
3555
NOTES: values maximum guaranteed values. 0.2V, 0.2V
IDT71F432 32Kx32 PIPELINED FUSION MEMORY CACHE
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS
(VDD 3.3V +10/-5%, 70°C)
Symbol tCYC tCH(1)
Parameter Clock Frequency Clock Cycle Time Clock High Pulse Width Clock Pulse Width Clock High Valid Data Clock High Data Change Clock High Output Active Clock High Data High-Z Output Enable Access Time Output Enable Data Active Output Enable High Data High-Z Input Setup Time Input Hold Time
IDT71F432S75 Min. Max. 13.3
IDT71F432S66 Min. Max. 66.7
Unit
3555
Clock Parameters
Output Parameters
tCDC tCLZ(2) tCHZ(2) tOLZ(2) tOHZ(2) tSxx tHxx
Hold Times
NOTES: Measured HIGH above 2.0V below 0.8V. Transition measured ±200mV from steady-state.
TIMING WAVEFORMS
tCYC tSxx Inputs
(except OE#)
tHxx
tCLZ I/O[31:0]
output
tCDC
tCHZ
tOLZ
tOHZ
IDT71F432 32Kx32 PIPELINED FUSION MEMORY CACHE
COMMERCIAL TEMPERATURE RANGE
CONFIGURATION
BW4# BW3# BW2# BW1# CS1# BWE# ADSC# ADSP# ADV#
I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VDD5 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31
PK100-1
14mm 20mm 1.4mm body 1.6mm total height 0.65mm pitch
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 VDD5 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
ORDERING INFORMATION
71F432 Device Type Power Speed Package Speed
RESET# W/R#
VIEW TQFP

PRELIMINARY IDT71F432 Uses IDT's Fusion Memory technology speed g

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