SCLS326 MARCH 1996 Members Texas Instruments Widebus Family Opera

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SCLS326 MARCH 1996 Members Texas Instruments Widebus Family Opera

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SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS326 MARCH 1996
Members Texas Instruments Widebus Family Operating Range 5.5-V EPIC(Enhanced-Performance Implanted CMOS) Process Distributed Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN54AHC16240 PACKAGE SN74AHC16240 PACKAGE (TOP VIEW)
description
'AHC16240 16-bit buffers line drivers designed specifically improve both performance density 3-state memory address drivers, clock drivers, bus-oriented receivers transmitters. These devices used four 4-bit buffers, 8-bit buffers, 16-bit buffer. These devices provide inverting outputs symmetrical active-low outputenable (OE) inputs. SN74AHC16240 available TI's shrink small-outline package (DL), which provides twice count functionality standard small-outline packages same printedcircuit-board area.
SN54AHC16240 characterized operation over full military temperature range -55°C 125°C. SN74AHC16240 characterized operation from -40°C 85°C.
FUNCTION TABLE (each 4-bit buffer) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC Widebus trademarks Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS326 MARCH 1996
logic symbol
PRODUCT PREVIEW
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS326 MARCH 1996
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through each Maximum power dissipation 55°C still air) (see Note package Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils.
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS326 MARCH 1996
recommended operating conditions (see Note
SN54AHC16240 Supply voltage High-level voltage High input Low-level input voltage Input voltage Output voltage High-level output current High ±0.3 ±0.5 Low-level output current ±0.3 ±0.5 ±0.3 ±0.5 3.85 1.65 SN74AHC16240 3.85 1.65 UNIT
ns/V
PRODUCT PREVIEW
Dt/Dv
Input transition rise fall rate
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS Data inputs Control inputs GND, (OE) GND, 25°C 2.58 3.94 0.36 0.36 ±0.1 ±0.1 ±0.25 SN54AHC16240 2.48 ±2.5 SN74AHC16240 2.48 0.44 0.44 ±2.5 UNIT
parameter includes input leakage current.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS326 MARCH 1996
switching characteristics over recommended operating ±0.3 (unless otherwise noted) (see Figure
PARAMETER tPLH* tPHL* tPZH* tPZL* tPHZ* tPLZ* tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C 10.3 10.3 10.6 10.6 11.5 11.5 14.1 14.1
free-air
temperature
SN74AHC16240 12.5 12.5 12.5 12.5 12.5 12.5
range,
UNIT
SN54AHC16240 12.5 12.5 12.5 12.5 12.5 12.5
switching characteristics over recommended operating ±0.5 (unless otherwise noted) (see Figure
PARAMETER tPLH* tPHL* tPZH* tPZL* tPHZ* tPLZ* tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 25°C
free-air
temperature
SN74AHC16240 10.5 10.5 10.5 10.5
range,
UNIT
SN54AHC16240 10.5 10.5 10.5 10.5
products compliant MIL-PRF-38535, this parameter ensured production tested.
output-skew characteristics, (see Note
SN74AHC16240 PARAMETER ±0.3 ±0.5 25°C UNIT
tsk(o)
Output skew
NOTE Characteristics determined during product characterization ensured design.
POST OFFICE 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
products compliant MIL-PRF-38535, this parameter ensured production tested.
SN54AHC16240, SN74AHC16240 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCLS326 MARCH 1996
noise characteristics, 25°C (see Note
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic Quiet output, minimum dynamic Quiet output, minimum dynamic High-level dynamic input voltage SN74AHC16240 -0.6 UNIT
VIL(D) Low-level dynamic input voltage NOTE Characteristics determined during product characterization ensured design surface-mount packages only.
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load, UNIT
PARAMETER MEASUREMENT INFORMATION
PRODUCT PREVIEW
From Output Under Test (see Note LOAD CIRCUIT Output Control (low-level enabling) tPZL Output Waveform (see Note tPZH Output Waveform (see Note Open
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
Open
Input tPLH In-Phase Output tPHL Out-of-Phase Output VOLTAGE WAVEFORMS DELAY TIMES tPHL tPLH
tPLZ tPHZ
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated

SCLS326 MARCH 1996 Members Texas Instruments Widebus Family Opera

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