Latch-up Model Preventing Latch-up Level Transceivers Genera

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Latch-up Model Preventing Latch-up Level Transceivers Genera

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Latch-up Model
Preventing Latch-up Level Transceivers
General Description
purpose this application note familiarize designers Level CMOS transceivers. Level devices designed meet, exceed absolute maximum specifications Silicon Controlled Rectifier latch-up. latch-up CMOS devices condition that cause maximum specifications exceeded. This application note provides necessary design considerations avoid latch-up. Following these design guidelines will: Avoid exceeding maximum transceiver ratings Simplify application maintenance Reduce latch-up related downtime systems Improve System reliability
Application Overview
Once triggered, latch-up condition turns parasitic internal CMOS circuits that creates resistance path from ground. resulting internal high currents damage devices. Modeled cross coupled transistor, basic trigger mechanisms; forces current into gate other places large voltage between anode cathode. When forward biasing diode, current injected into base turns this transistor collector current (beta times base current) flows into base This causes amplified beta back into base where current again amplified. beta both transistors greater than current gain continues until transistors saturate triggered. Once regenerative condition occurs, large anode current flows. remains after gate current removed, enough anode current flows sustain latch-up. case large voltages anode cathode, trigger condition occur even current applied gate. forward blocking state small leakage current present will trigger SCR. voltage increased allow significant leakage current, then could trigger. beta must greater than latch condition occur. There number scenarios that cause trigger occur inputs outputs (latch condition) including insertion removal circuit card from powered system. effectively controlled (either when integrated system level) designers must have clear understanding causes latch-up.
Design Guidelines
circuit card design includes "hot-swapping" capability, insure that power reaches devices (transceivers, PALs, etc.) before applying voltages input output pins (i.e., power ground pins make contact before input output pins). With multiple power supplies feed same device, arrange pins supplies connect ascending order. Thus, circuit card requires pins should connect first, pins next finally pins. event, before voltage pins make contact, ground should connect first insure that positive supplies pull negative supplies visa versa.
Latch-Up Model
Anode Gate (G2) Gate (G1) Cathode Gate (G1) Gate
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Latch-up Model
When devices drive other devices separate boards aware that large amounts local decoupling cause power supply ramps slower some boards than others. Insure that voltages input/output pins exceed supply voltage. Clamping circuits needed reduce input voltage. Insure that input current does exceed absolute maximum rating this expected, current limiting necessary prevent latching condition. Never allow output driver drive another output driver applications redundancy (Figure This accomplished only break before make connection drivers observed. These drivers high current drivers, capable exceeding triggering currents necessary latch condition.
Figure Applications Redundancy
Operational Transceiver Card
Redundancy Transceiver Card Backplane
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Latch-up Model Preventing Latch-up Level Transceivers Genera

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