Appendix QDIF File Format QuickLogic Data Interchange Format (QDI

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Appendix QDIF File Format QuickLogic Data Interchange Format (QDI

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Appendix QDIF File Format
Appendix QDIF File Format
QuickLogic Data Interchange Format (QDIF) been fully specified implemented. QDIF provides open access framework SpDE additional user third-party tools SpDE single ASCII file format which serves read write interface other systems. While there many sections QDIF format, netlist portion QDIF very simple; only netlist portion QDIF needs created SpDE going used place route.
Sections
Library section-the library describes each gate type used netlist terms implemented pASIC macro cell. example, input gate used several places user's design, implementation gate pASIC macro cell described here once. Logical section-the logical section describes each instance gates described Library section, these gates interconnected. there three gates user's design, each will described here, along with information about nets connected them.
These sections need created SpDE read netlist.
Syntax
netlist sections describe design terms ofgates, nets, terms, cells, ports. gate: instance logic gate, such gate multiplexer. Gates often referred symbols instances schematics. term: terminal gate. Terminals connection points gates nets. Terminals often referred aspins symbols schematics. net: nets interconnect gates, usually referred wires schematics. cell: cells pASIC part. Cells locations physical part where gates implemented. Types cells include BIDIR, INPUT, CLOCK cells, LOGIC cells which fill interior chip. port: ports inputs outputs cells physical chip. library section describes gate types terms implementation cells. This done defining which ports associated with which terms gate. Appendix
QuickTools Users Guide
Identifiers
Identifiers (Net names, Instance names) must begin with alpha character. This followed printable ASCII characters from 0x21 through 0x7e Space, newline token separators. Identifiers case sensitive limited characters length. comment character available. input from comment character newline ignored.
Keywords
syntax keywords give structure. Keywords either case. However, requirement here somewhat different from programming language where user identifiers cannot conflict with keywords. cannot restrict user choice names design objects such gates, terminals, nets, etc. meet this need, keyword acceptable object name. syntax carefully designed there ambiguities.
Supply Nets
Supply nets restricted reserved names "VCC" "GND".
Object Count
syntax includes count objects before objects themselves appear. This allows readers operate efficiently single pass. Writers have traverse data twice order supply this information.
Example
Figure 22-1 simple circuit illustrate post-layout QDIF file. Instance names shown above each macro, names shown above each net.
Figure 22-1: Circuit QDIF Example
Appendix
Appendix QDIF File Format
This line tells parser which version syntax use. QDIF This line tells SpDE which part use. file p8x12A This line tells parser which package part left out, default package will used. package pl68 tools section describes which tools have been run. "design" tool represents netlister. 3000 means compatibility with release SpDE, although SpDE will read netlists back version 1.0. tools design 3000 This library section, which describes types gates library QDIF number gate types, terminals gates, ports gates must pre-declared. gates terms ports gate OUTPAD cell BIDIR term port port term port term port term gate OR2I0 cell LOGIC term port port port port port port port port port port term port port port port port port port port term port term port term port gate AND2I0 cell LOGIC term port term port port port term port term port term port gate INPAD cell BIDIR term port term port port term port term port This section describes gate instances nets user's design. logical QDIF Again, total gate counts must pre-declared gates nets Cell pre-placements written "cell <cell name>. Cell names pads IO<pin number> syntax, accept grid arrays, which <column letter><row number> syntax. Logic cell locations <column letter><row number> syntax well (i.e. H2). gate INP1 master INPAD cell IO11 gate INP2 master INPAD cell IO13 gate INP3 master INPAD cell IO14 gate INP4 master INPAD cell IO10 gate AND1 master AND2I0 gate AND2 master AND2I0 gate master OR2I0 gate OUT1 master OUTPAD cell IO12 Writing nets optional when user does directly them.
Appendix
QuickTools Users Guide
IN_1 gate AND1 term gate INP1 term IN_2 gate AND1 term gate INP2 term IN_3 gate AND2 term gate INP3 term IN_4 gate AND2 term gate INP4 term gate term gate AND1 term gate term gate AND2 term OUT_1 gate OUT1 term gate term direction input gate INP1 term direction input gate INP2 term direction input gate INP3 term direction input gate INP4 term direction output gate OUT1 term
Appendix

Appendix QDIF File Format QuickLogic Data Interchange Format (QDI

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