Appendix Error Messages This appendix reference SpDE messages. er

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Appendix Error Messages
Appendix Error Messages
This appendix reference SpDE messages. error messages after different actions using QuickLogictools. Export QuickLogic from Hierarchy Navigator'sProcess menu: Refer section this appendix titledExport Design Verifier. Import from SpDE's File menu: Refer section this appendix titledImport Design Verifier. Import Verilog from SpDE's File menu (Synplify-Lite Verilog Synthesis): Refer Synplify-Lite Documentation numbered error messages from QuickLogic tools: Refer section this appendix titledSpDE Tool Errors. Error Messages from other QuickLogic supported design tools: Refer supplemental documentation design tool.
Appendix
QuickTools Users Guide
SpDE Design Verifier
Design Verifier, which runs when design loaded into SpDE, presents Notes, Warnings, Errors interactive list box.
Notes
Notes intended bring situation designer's attention. situation probably problem, should verified nevertheless.
Note: Gate used, being removed This message will occur gate that does have output tied other logic. Note this tends have "ripple" effect. Once gate removed, this also cause gate driving removed. This eliminate gates design some cases. solution make sure that gates your design, attach output logic output pads (OUTPADs). This note ignored expect logic removed (such when counter used design, only bits used).
Warnings
Warnings serve alert designer problematic situation, commonly associated with real problem.
Warning: Exceeded recommended limit high-drive nets pASIC device family, recommended more than high-drive pads (HDPADs), because these types inputs must routed high-drive wires, which limited resource. This error also occur when three HDPADs used, both outputs used each (each high-drive active high active output), because this makes total "high-drive nets". Keep mind that also using high-drive nets when high-drive outputs CKTPAD (the CKTPAD high-drive outputs, clock network output). must more than 4HDPADs your design, recomment putting buffer immediately following output your HDPADs because this will limit fanout high-drive wire improving routability. Note: High-drive wires also used when "double-buffer". This when buffers tied parallel higher drive capability. This legal only pASIC family devices.
Appendix
Appendix Error Messages
Warning: Gate cannot have fixed placement only types gates which have fixed placement flip-flop cells, cells. Warning: Gate converted compatible cell Verifier converted CKPAD HDPAD, vice-versa. This done match type number selected pad. many HDPADs CKPADs were used, than more them were converted other type. Warning: "<>" (gate drives reset, disabling ATVG some devices, restricts ATVG tool when certain HDPADs tied flip-flop's reset input. This will affect programming yield noticeable way. However, ATVG will report coverage. ATVG only used test devices that have been potentially damaged. (for example, board damaged, desire test QuickLogic device affected). Warning: "<>" (gate paralleled, disabling ATVG pASIC family devices, legal more HDPADs parallel. However, certain combinations parallel HDPADs restrict ATVG tool. This will affect programming yield noticeable way. However, ATVG will report coverage. ATVG only used test devices that have been potentially damaged. (For example, board damaged, desire test QuickLogic device affected). Warning: Incompatible inputs moved from This error occurs when driven clock network driver clock also driving logic. Warning: drives inputs specified gate that drives destinations. this output net, make sure that attach output (OUTPAD). Warning: high fanout This warning issued indicate which nets have high fanout input (I/O) pads your design. Verifier designed default show warning when fanout above This does indicate error your design. However, using buffering techniques indicated Design Techniques Chapter User's Guide) will probably able improve speed specified net. desire replace INPAD with high drive (HDPAD).
Appendix
QuickTools Users Guide
Warning: high input fanout This warning issued indicate which nets have high fanout high-drive pads your design. Verifier designed default show warning when fanout above This does indicate error your design. However, using buffering techniques indicated Design Techniques Chapter User's Guide) will probably able improve speed specified net. Warning: should have arrival This message indicates that arrival time attribute been added which input. Arrival time attributes appropriate only input nets. Warning: should have departure This message indicates that departure time attribute been added which output. Departure time attributes appropriate only output nets. Warning: high logic cell fanout This warning issued indicate which nets have high fanout your design. Verifier designed default show warning when fanout above This does indicate error your design. However, using buffering techniques indicated Design Techniques Chapter User's Guide) will probably able improve speed specified net.
Errors
Errors flag genuine error conditions which will prevent parts from being programmed. However, tools still experimental purposes examination.
Error: Gate floating input gate with instance name specified more inputs which driven from other logic. This case where been left without connection schematic. inputs avoid this error. Error: driven multiple pads illegal drive from more pads. this done intentionally, look carefully names attached your input output pads, make sure that none pads accidentally tied together with same net.
Appendix
Appendix Error Messages
Error: fanout drivers strong internal wire current when more than highdrive pads parallel, cannot drive less than loads within chip. want less than loads, then downgrade your driver HD2PAD high-drive pads parallel). Error: driver There your design that driven gate. This because have forgotten input pads your inputs. This also have happened done with your design. unused inputs avoid this error. Error: Missing enable terminal this error occurs, please contact QuickLogic technical Hotline.
Fatal Errors
Fatal errors flag serious error conditions which will prevent tools from being run.
Fatal Error: Clock multiple drivers specified clock more than driver, which illegal. Only driver clock network allowed. Fatal Error: Gate type illegally connected port custom defined macro with specified name been created incorrectly. There specific rules defining create custom logic cell macro. Refer Macro Library Chapter User's Guide details. gate name specified custom macro, macro supplied QuickLogic, contact technical Hotline. Fatal Error: Design File: Term gate this error occurs, please contact QuickLogic technical Hotline. Fatal Error: Gate drives output specified instance connected GND, which illegal. Fatal Error: Gate should placed clock cell instance name specified corresponds gate that must placed clock locations. Clock pads placed high-drive (input-only) locations, locations, logic cell locations.
Appendix
QuickTools Users Guide
Fatal Error: Gate type illegally connected port custom defined macro with specified name been created incorrectly. There specific rules defining create custom logic cell macro. Refer Macro Library Chapter User's Guide details. gate name specified custom macro, macro supplied QuickLogic, contact technical Hotline. Fatal Error: Gate type illegally connected port custom defined macro with specified name been created incorrectly. There specific rules defining create custom logic cell macro. Refer Macro Library Chapter User's Guide details. gate name specified custom macro, macro supplied QuickLogic, contact technical Hotline. Fatal Error: Dual drive gate illegally connected This refers double-buffer configuration your design. gates have been tied parallel (their inputs outputs tied together), there error wiring. Check your design. intend create double-buffer your design, then look specified gate your design check wiring around Fatal Error: Gate illegally connected outputs This refers double-buffer configuration your design. gates have been tied parallel (their inputs outputs tied together), there error wiring. Check your design. intend create double-buffer your design, then look specified gate your design check wiring around intended make custom doublebuffer, check rules double-buffering Design Techniques chapter User's Guide. Fatal Error: Terms gate ill-defined this error occurs, please contact QuickLogic technical Hotline. Fatal Error: design gates! Verifier removed gates design. Make sure design contains pads. Fatal Error: Design File: Term this error occurs, please contact QuickLogic technical Hotline. Fatal Error: Gate placed incompatible cell placement attribute specified gate legal this gate. Make sure none pads this design have logic cell placements, also make sure none gates design have placements.
Appendix
Appendix Error Messages
Fatal Error: Gates placed same cell instances specified have identical fixed-placement attributes. Change both fixed placement attributes that gates placed different locations device. Fatal Error: Gates illegally paralleled specified instances have outputs that drive same net. Paralleled gates allowed only gates identical, placed same logic cell. Fatal Error: High-drive drives global clock buffer high-drive specified connected input global clock buffer, which illegal pASIC devices. simple workaround high-drive drive logic buffer (BUFF), which, turn, drives global clock buffer. Fatal Error: High-drive opposing pads corner This rare condition. problem that high drive nets have limited routing connections. High drive nets nets which driven HDPADs, CKTPADs, double-buffers (two identical buffers gates tied parallel). illegal high-drive drive output pads their tri-state enables) corner device. Change driver high-drive net, move position. driver HDPAD CKTPAD, inserting buffer design before driving output pads. Fatal Error: driven more than high-drive pASIC device specified connected outputs high-drive pads (inputonly pads). Paralleling high-drive input pads illegal pASIC devices. Fatal Error: pre-placed opposite side High-Drive (HDPAD) driving output directly tri-state enable output pad), that output cannot placed opposite side chip HDPAD. This routing limitation high-drive wires. must have pinout already defined, then inserting buffer output HDPAD, outputs driven directly from high-drive pad, from buffer. Fatal Error: uses array clock drive logic inputs specified driven Array Clock input pad, drives combinatorial inputs more logic cells. resolve this problem, possibly Global Clock input pad, Global Clock buffer, high-drive pad. Note that Global Clock nets only feed "F1" logic input logic cell. Router section User's Guide more details regarding legal Global Clock connections.
Appendix
QuickTools Users Guide
Fatal Error: uses array clock drive logic inputs Global Clock specified drives logic cell inputs other than "F1" input, which illegal pASIC devices. resolve this problem, "F1" input when possible, other cases, connect Global Clock "F1" input F-fragment create buffer capable driving logic input. Fatal Error: driven more than logic outputs specified driven more than drivers. more than drivers allowed internal net. this done intentionally, check connections this name carefully your design find possible design error. Fatal Error: driven multiple sources specified driven more than drivers. more than drivers allowed internal net. this done intentionally, check connections this name carefully your design find possible design error. your intention double-buffer this net, aware that this legal only pASIC devices, there specific rules double-buffer (refer Design Techniques chapter User's Guide). Fatal Error: both sides specified connected both input output pad. different name each side pad. Fatal Error: must pre-placed This error given because driving output, tri-state, bi-directional pads directly form high-drive net. High-drive nets driven HDPADs, CKTPADs, double-buffers (two identical buffers gates tied parallel). When drive outputs tri-state enables outputs) directly with high-drive nets, need manually placement output pads. Make sure that placement fixed that output pads driven same high-drive opposite sides chip illegal condition). Fatal Error: Programming cell used this error occurs, please contact QuickLogic technical Hotline. Fatal Error: Terms ill-defined this error occurs, please contact QuickLogic technical Hotline. Fatal Error: Used bi-directional pads with available number bi-directional (I/O) pads required this design greater than number pads available this device-package combination. Either remove some pads from design, device-package combination with more I/O's.
Appendix
Appendix Error Messages
Fatal Error: Used clock pads with available number clock pads required this design greater than number clock pads available this device-package combination. Either remove some clock signals from this design, device with more clock pads, high-drive pads some these signals. Fatal Error: Used flip-flops with available number flip-flops required this design exceeds number available flip-flops this device. Remove some flip-flops from design, larger device. Fatal Error: Used input-only clock pads with available number input-only (high-drive) clock pads required this design exceeds number available input-only clock pads available this device. Either remove some these signals from design, move some signals pads. Fatal Error: Used global clock networks number Global Clock networks required this design exceeds number available Global Clock networks available this device. Either move some these signals other routing resources, remove them from design, device with more Global Clock networks. Fatal Error: design does pass database check! this error occurs, please contact QuickLogic technical Hotline.
Appendix
QuickTools Users Guide
SpDE Tool Errors
SpDE reports user errors using anError dialog box. These errors represent design system errors which fixed user. tables below organized tool code; first letters error code indicate tool. XX-(starting with letters)
xx0100 xx0199 Memory SpDE requested more memory than Windows currently available. closing other applications re-run SpDE. still problem, re-starting windows. Many memory problems solved creating larger Windows swap file (see Virtual Memory section System Requirements appendix). Windows offers very efficient memory management-refer Microsoft Windows User's Guide complete details.
CH-Chip file QDIF file converter load design files)
CH0001 CH0002 Error loading binary file: <filename>. Cannot save QDIF file: <filename>. converter software having trouble loading source design saving destination. This could full disk, lack write read access files.
DB-The SpDE Database module
DB0001 DB0002 Invalid Package Type invalid package type been chosen QuickLogic chip chosen. Refer QuickLogic documentation design entry package using valid package types.
ED-EDIF Netlist reader
ED0002 ED0003 Syntax error line <line number> line <line number> EDIF file, illegal syntax been used.
Appendix
Appendix Error Messages
ED0004 ED0005 ED0006
Integer '<integer>' large line <line number> Integer '<integer>' large line <line number> Integer '<integer>' range line <line number> line <line number> EDIF file, number <integer> allowed range. Invalid symbol '<symbol>' line <line number> EDIF file contains string <symbol> with invalid character line <line number>. Unexpected file EDIF file ended pre-maturely. This usually because error that occurs during creation EDIF file. Expected line <line number> open parentheses expected (but found) EDIF file line <line number> order comply with EDIF syntax.
ED0007
ED0008
ED0009
EQ-QuickBoolean Netlister
EQxxxx QuickBoolean Error Design Entry QuickBoolean chapter complete error messages QuickBoolean tool
ET-EDIF Netlist Reader (EDIF SpDE Translator)
ET0006 Package type specified unknown: <package> package specified EDIF file which SpDE does recognize. Refer QuickLogic documentation your design entry tool valid package types. Package incorrect bonding used EDIF file which does exist bonded out) selected package. Either number package type incorrect.
ET0007
Appendix
QuickTools Users Guide
ET0012
Device name specified: Using default. Part Package attributes were present EDIF file. Refer your third party interface documentation details including these attributes.
GP-Graphing Package
GP0001 GP0002 Error opening clipboard Error opening picture Grapher could properly open picture clipboard with Windows calls. re-booting your computer. Error closing picture Error closing clipboard Grapher could properly close picture clipboard with Windows calls. re-booting your computer. Error putting picture onto clipboard Grapher could complete operation copying graph clipboard. memory, Windows could unstable. re-booting.
GP0003 GP0005
GP0004
JE-LOF Netlister
JE0001 Could open file <filename> <Filename> specified user either does exist does have read attribute. support part <part> device used current design (<part>) currently supported Netlister. Contact QuickLogic details.
JE0002
LS-Load Save Files
LS0001 LS0004 Could open binary file <filename>. <Filename> specified user either does exist does have read attribute. LS0002 LS0005 Wrong part file version file <file>.
version specified part file exists SpDE data directory. Check your WIN.INI file insure that ini-path entry [SpDE] section been properly set.
Appendix
Appendix Error Messages
LS0003 LS0006
Unknown part name <part>. part specified design file does exist does have associated part file. Check your WIN.INI file insure that ini-path entry been properly set.
LS0007 0010
Part File Errors These errors will occur SpDE cannot find current, valid part file. this error occurs, want re-install SpDE.
LS0011
Unknown package type: <package> package specified QDIF file which SpDE does recognize. Refer QuickLogic documentation your design entry tool valid package types. <Error> approximately line <line number> parsing error <Error> occurred while reading line <line number> QDIF file.
LS0200
PA-Path Analyzer
PA000x Clipboard Errors These errors indicate that Path Analyzer could Windows clipboard properly. re-booting your computer.
PK-Packer (Level Optimizer)
PK0000 PK0001 PK0002 PK0003 Cannot pack many logic cells many HDPADS (input-only pads) used many pads used many CKPADS (clock pads) used design requires more specified resources than available selected pASIC device. fewer specified components select larger device.
Appendix
QuickTools Users Guide
PK0004
Illegal fixed location cell been assigned incompatible location. example, high-drive placed bi-directional pin. Consult device reference appendix move fixed placement appropriate location.
PR-Programmer Interface
PR0000 PR0029 Programmer Initialization Errors programmer could properly initialize test pASIC(s) being programmed. part could incorrectly inserted socket, damaged, wrong part type, already programmed. This could also improperly configured serial port, serial port which 100% compatible, wrong socket adapter. PR0030 PR0079 port communication errors port could fully initialized. Verify that correct port been selected that cable properly attached. problem persists, there problem with serial port serial card configuration. PR008x Signature Programming Error signature bits could programmed successfully device programmer. This probably part. this error occurs more than part, then your programmer could damaged.
QS-QDIF Schematic Conversion
QS0000 Unable open <file> Schematic Generator unable access indicated file. file exist, directory have read permission. Can't load <file> Could load QDIF file. file corrupt valid QDIF file.
QS0001
Appendix
Appendix Error Messages
QS0002
Unable close <file> Schematic Generator unable access indicated file. disk space directory have write permission.
RT-Router
RT0000 RT0002 Could complete routing Could complete hi-drive routing router does have enough resources complete routing. case hi-drive routing, refer Router chapter Special Routing Cases section. Otherwise, re-placing after changing placer seed.
Appendix
QuickTools Users Guide
RT0003
express wires channel <x><y>. Re-run placer with another seed. Router requires more express wires than available specified channel. This problem most often caused excess signals attached high-drive input pads, many double-buffers. described Router chapter, employing four fewer signals tandem with these pads guarantees routability these signals.
SD-SDF Writer
SD0001 Cannot open file: <filename> writer open file that needs create. This could full disk, write-protected file directory.
SP-SpDE
SP0004 SPDE.INI read-only does exist. SpDE could find initialization file spde.ini saving defaults. This could mean that file been erased that file read-only.
SQ-Sequencer
SQ0000 Sequencer could complete. Re-run Router with different seed. Sequencer could determine order which program Via-Links part after routing attempts Rerunning Placer with different seed will correct problem.
UI-User Interface
UI0001 There (are) <number> dll(s) SpDE's path SpDE detected DLL's (.DLL) that needs directory that current SpDE directory. Contact QuickLogic. Cannot convert chip file <filename> SpDE could convert chosen chip (.CHP) file latest version. Possibly non-chip file, chip file from very version SpDE been selected. Unable complete command "<command>" successfully SpDE tried execute command <command> without success.
UI0002
UI0003
Appendix
Appendix Error Messages
UI0004
Invalid directory: <directory> chosen directory cannot accessed. This happen chosen directory drive that been "joined" network directory. Also, directory exist. Can't change specified directory chosen directory cannot changed properly. This will happen chosen directory drive that been "joined" network directory. SPDE.INI read only. Cannot save options
UI0005
UI0006 UI0023 UI0024
SpDE could read and/or modify SPDE.INI file. Make sure this file read-only directory. also check win.ini file under [SpDE] that ini-path points directory where this file exists. (.spderc home directory users) UI0008 PKZIP.EXE found path file cannot properly compressed unless PKZIP version 1.01 path. Either PKZIP path, file manually using PKZIP 1.01. Unable command: <command> Reason: <reason> SpDE could Windows application because <reason>. This could indicate improper configuration. printer connected SpDE could detect printer device under windows. Check printer setup Windows Control Panel. Printer SpDE could print default device. Check printer setup Windows Control Panel. File <filename> from later version SpDE. have chosen open file that created from later version SpDE than running currently. intend this, check configuration, re-install latest SpDE tools. Unable convert <filename> SpDE could properly convert <filename> current version SpDE. Contact QuickLogic help.
UI0009
UI0010
UI0011
UI0015
UI0016
Appendix
QuickTools Users Guide
UI0017
Can't initialize gang programmers have configuration problem with gang programmers, problem with your serial card. Programmer chapter more information. gang programmers found Check make sure gang programmers connected, plugged that correct port been chosen. automatic place route tools were Check Place Route option settings. have chosen Tools after tools have already been run. wish iterate: change seeds Tools Options, then re-run tools with Selected Tools. Cannot process SPDE.INI file SPDE.INI file been corrupted. Contact QuickLogic.
UI0018
UI0019
UI0020 UI0021
UI0022
Error opening report file <filename> SpDE could open report file created. This could happen were memory load chosen editor, chosen editor could loaded properly. Change chosen editor from View-Preferences. Cannot load QDIF file <filename> error detected while reading QDIF file. file have syntax error (see QDIF appendix QDIF syntax), file have been damaged. Ini-path found win.ini. Using c:\pasic\spde\data SpDE expects find variable ini-path under heading [SpDE] win.ini file. installation program will this automatically. Check win.ini file, re-install SpDE. Save Error error detected while trying save file. This caused write-protect violation insufficient disk space.
UI0034
UI0037
UI005x
Appendix
Appendix Error Messages
UI006x
Load Error error detected while trying load file. This caused choosing wrong file type load, trying load file without read attribute.
VE-SpDE Physical Viewer
VE0007 VE0010 VE0012 Value must between <min> <max>
value have entered allowable range. Enter value between <min> <max>. VE0009 VE0011 (unsigned) integer value value have entered does represent proper integer value. SpDE expecting unsigned integer, make sure number positive. Always make sure integers have decimal points.
VG-Verilog Netlister
VG0001 Error: Cannot open file: <filename> Verilog netlister cannot open output file trying create. This could full disk read-only directory.
VL-ViewLogic Netlister
VL0000 VL0004 VL0006 Error: Cannot open file <filename>
ViewLogic netlister could access specified file. Check ViewLogic environment variables, write access specified directory, existence specified file. VL0005 VL0007 Cannot write file: <filename> ViewLogic Netlister could write specified file. Check available disk space write permission specified directory file.
Internal Errors
These errors indicated messageInternal Error, Win32s Error, Internal Error, Fatal Error accompanied their usually cryptic nature. These errors should Appendix
QuickTools Users Guide occur-they indicate inconsistency SpDE's data structures. these errors encountered, record text error pletely contact QuickLogic Corporation.
Memory Errors
tools cannot execute properly, error message like "Unable toolname, check path", error message with reference being memory then probably running many applications Windows. Close unnecessary applications again. After memory error occurs, best save your work re-start Windows. When memory error occurs, tool close properly leave Windows somewhat unstable state. memory because improper Virtual Memory Settings. Check Tutorial Chapter section Virtual Memory more details.
Appendix
Appendix Error Messages
Appendix

Appendix Error Messages This appendix reference SpDE messages. er

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