µPD16662 240-OUTPUT COLUMN (SEGMENT) DRIVER WITH DESCRIPTION
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INTEGRATED CIRCUIT
µPD16662
240-OUTPUT COLUMN (SEGMENT) DRIVER WITH
DESCRIPTION
µPD16662 column (segment) driver with internal drive full-dot LCD. Equipped with output pins display bits, this driver display four gray levels selected from level palette. using this combination with µPD16667, pixels pixels displayed.
FEATURES
Internal display bits Logic voltage Duty Number outputs Display 1/160 pins Four gray levels (selectable from 25-level palette)
Memory management Packed pixel method Supports 8-/16-bit data
ORDERING INFORMATION
Part Number Package (TAB)
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production.
Document S12738EJ1V0DS00 (1st edition) Date Published July 1998 CP(K) Printed Japan
1997
µPD16662
NAME
Classification CPUIF Name D0-D15 A0-A16 UBEB BMODE REFRHB TEST RESETB DOFFB OSC1 OSC2 FRMB PULSE DOUTB Y1-Y240 VCC1 VCC2
Note
Function
Data bus: pins Address bus: bits Chip select Read signal Write signal Upper byte enable Ready signal ("H": ready) Specifies layout position (No. Specifies layout position (No. Specifies liquid crystal panel layout position Master/slave selection ("H": master mode) Data selection ("H" bits, bits) Self-diagnosis reset Test ("H" test mode, with pull-down buffer) Reset signal Display input signal External resistor oscillator External resistor oscillator Column drive signal output, input) Frame signal output, input) 25-level pulse modulation clock driver drive level select signal (first line) driver drive level select signal (second line) Display output signal Liquid crystal drive output Ground (two pins, three 3.3-V pins) power 3.3-V Power Liquid crystal drive analog power Liquid crystal drive analog power Liquid crystal drive analog power
Control signals
Liquid crystal drive Power
Note 3.3-V pins through D15, through A16, CSB, OEB, WEB, UBEB, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, RESETB, DOFFB, TEST, pins STB, FRMB, DOUTB, PULSE
µPD16662
BLOCK DIAGRAM
PL0, TEST Address input control Address management circuit Arbiter bits
A0-A16 Control CSB, WEB, UBEB BMODE D0-D15
Data control
REFRHB RESETB STOP OSC1 oscillator OSC2 DOFFB Liquid crystal timing generation 3.3-V operation PULSE FRMB Self-diagnosis circuit Level shifter 5.0-V operation
Data latch
Gray level generation circuit
Data latch
Internal timing generation Gray level control
3.3-V operation
5.0-V operation
Liquid crystal drive circuit outputs
PULSE
FRMB
DOUTB
Y240
µPD16662
BLOCK FUNCTION
Address management circuit This circuit converts addresses from system through into addresses corresponding memory internal RAM. using this function four µPD16662 modules, addresses pixels managed, making easy construct liquid crystal display system. Addresses 1FFF0H through 1FFFFH allocated gray level palette register, four gray levels selected from 25-level palette. Arbiter This circuit arbitrates conflicts between access system reading driver. This static bits (single port). Data control This circuit controls data transfer direction depending whether system reads writes
µPD16662.
data width changed between bits BMODE pin. Gray level generation circuit This circuit offers levels means frame interpolation pulse width modulation. Internal timing generation This circuit generates internal timing signals each block from FRMB signals. oscillator This oscillator generates clock that serves reference frame frequency master mode. frame frequency 1/2592 oscillation frequency this oscillator. example, where frame frequency oscillation frequency 181.44 kHz. Because this oscillator on-chip capacitor, necessary oscillation frequency adjusted using external resistor. Oscillation stopped slave mode. Liquid crystal timing generation This circuit generates FRMB (frame signal), (column drive signal strobe), PULSE (25- level pulse modulation clock) signals master mode. Gray level control This circuit implements 4-gray level display. (10) Data latch This circuit reads data pixels from latches (11) Data latch This circuit latches data pixels synchronization with signal.
µPD16662
(12) Level shifter level shifter converts operating voltage internal circuit (3.3 into voltage liquid crystal driver circuit driver interface (13) This decoder that decodes gray level display data liquid crystal drive voltages (14) Liquid crystal drive circuit This circuit selects liquid crystal drive voltage corresponding gray level display data display signal (DOFFB), generate liquid crystal application voltage. (15) Self-diagnosis circuit operation timing master chip that slave chip differ external noise, this circuit automatically detects difference generates refresh signal column drivers.
MEMORY
Address 00000H 0A000H 13F78H 1FFF0H 1FFFFH
Description Display data Nos.
Display data Nos.
Vacant
Gray level palette register
µPD16662
Address Image (example half-VGA size configuration)
through specify column direction. Y240 Address incrementing direction through specify line direction. L160 Address incrementing direction L160 Y240 Y240 Y240
µPD16662
DATA
byte data ordering data little endian, common with most Intel buses. 16-bit data (BMODE Byte access
00000H Address incrementing direction 00002H 00004H 00001H 00003H 00005H
Word access
00000H Address incrementing direction 00002H 00004H
system accesses µPD16662 word (16-bit) byte (8-bit) units, UBEB (upper byte enable) specify whether bytes through bytes through have valid data.
UBEB
MODE
D0-D7 selected Read Hi-z Dout Hi-z Dout Hi-z Hi-z D8-D15 Hi-z Dout Dout Hi-z Hi-z Hi-z
Write
Output Disable
Don't care
Hi-z High impedance
µPD16662
8-bit data (BMODE
00000H Address incrementing direction 00001H 00002H
MODE
D0-D7 selected Read Write Output disable Hi-z Dout Hi-z D8-D15 Note Note Note Note
Don't care
Hi-z High impedance Note Leave through open because they internally pulled down.
µPD16662
RELATION BETWEEN DATA BITS PIXELS
Because µPD16662 displays four gray levels, pixel consists bits. consists pixels pixels word) using packed pixel method. BMODE Byte (8-bit) access
Pixel Pixel 00000H Pixel Pixel Pixel Pixel 00001H Pixel Pixel
BMODE
Pixel Pixel 00000H Pixel Pixel Pixel Pixel 00001H Pixel Pixel
Liquid crystal Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel panel 00000H 00001H 00002H 00003H
Word (16-bit) access
Pixel Pixel Pixel Pixel 00000H Pixel Pixel Pixel Pixel
Liquid crystal Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel panel 00000H 00000H 00001H 00002H 00002H 00003H Liquid crystal Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel panel
µPD16662
GRAY LEVEL CONTROL
gray level control µPD16662 offers 25-level palette means frame interpolation pulse width modulation. From this palette, four gray levels selected registered gray level palette register.
GRAY LEVEL PALETTE REGISTER
gray level palette register selects four gray levels from levels advance. This register allocated 1FFF0H through 1FFFFH, relation with gray level data shown below. Also shown below initial values assigned each address. gray level palette register each layout position column driver (No. that determined PL1.
Gray Level Data (Display Data) Dn+1
Note
Address
1FFF0H 1FFF1H
Layout Position
Initial Value
00000B 01000B 10000B 11000B 00000B 01000B 10000B 11000B 00000B 01000B 10000B 11000B 00000B 01000B 10000B 11000B
Note
1FFF2H 1FFF3H 1FFF4H 1FFF5H
1FFF6H 1FFF7H 1FFF8H 1FFF9H
1FFFAH 1FFFBH 1FFFCH 1FFFDH
1FFFEH 1FFFFH
Note
µPD16662
RELATION BETWEEN GRAY LEVELS GRAY LEVEL PALETTE DATA
relation between gray levels gray level palette data gray level palette register follows:
Gray Level Palette Data Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level Gray level
PMODE
Remark
µPD16662
LAYOUT ADDRESS MANAGEMENT
Addresses managed that four µPD16662s used organize liquid crystal display 1/2VGA (320 pixels). Four modules connected same with CSB, WEB, pins shared. system treats screenful liquid crystal display memory area, does have decode more than LSI. Specify using determine layout LSIs, determine direction (vertical horizontal) liquid crystal display using pin.
µPD16662
Horizontally long address half size
Specified through Specified through L159 L160 09E00 09F00 0A000 0A100 L159 L160 13E00 13F00 Y233 Y240 13E3A 13F3A 13E3C 13F3C Y233 Y240 00000 00100 09E3A 09F3A 0A03A 0A13A 09E3C 09F3C 0A03C 0A13C 13E76 13F76 Y240 Y233 0003A 0013A 0003C 0013C 09E76 09F76 0A076 0A176 Y240 Y233 00076 00176
Specified through
00076 0003C 0003A 0013C 0013A 00176
00000 00100
Vertically long address half size
Specified through
09E76 09F76 0A076 0A176
09E3C 09E3A 09F3C 09F3A 0A03C 0A03A 0A13C 0A13A
09E00 09F00 0A000 0A100
13E76 13F76
13E3C 13E3A 13F3C 13F3A
13E00 13F00
µPD16662
µPD16662
INTERFACE
Function (ready) internal single-port RAM. kept waiting that access from does conflict with reading driver. Timing
A0-16, UBEB
OEB/WEB Hi-z Hi-z
Wait status
Ready status Access time
Connection uses three-state buffer. more than used, pins each wired together connected external pull-up resistor.
Ready input
Pull-up resistor Column driver
Column driver
µPD16662
Access timing Display data read timing
UBEB
Hi-z Hi-z Dout Hi-z Hi-z
Display data write timing
UBEB
Hi-z Hi-z
Gray level palette data write timing
UBEB
Hi-z
µPD16662
LIQUID CRYSTAL TIMING GENERATION
Reset status reset, internal counter cleared After reset status cleared, display function held frame cycles, even DOFFB "H".
RESETB FRMB
DOUTB
Internal status Display Display
µPD16662
Liquid crystal timing generation circuit master mode making high, FRMB generated timing with duty factor 1/60. Driver drive voltage select signals generated driver. FRMB generated times frame. generated times frame times frame. FRMB signal generation
OSC1 PULSE
FRMB
Frame
signal generation
µPD16662
SELF-DIAGNOSIS FUNCTION
This function checks whether timing each column driver different from that others external noise. slave chip compares internally generated with master chip. discrepancy found, refresh signal transmitted column drivers. reception refresh signal, internal reset effected, timing initialized. this time, display turned while REFRHB frame cycles. Discrepancy between monitored rising edge FRMB once frame.
(master) Discrepancy (master) (slave) (slave)
Discrepancy
REFRHB Initialization Initialization
Block Configuration (slave side)
RESETB Internal reset
REFRHB Self-diagnosis circuit
Internal signal Internal signal
µPD16662
SYSTEM CONFIGURATION EXAMPLE
Here example using liquid crystal panel half-VGA size (480 pixels, horizontally long) using four
µPD16662s drivers.
each column driver pins. each column driver low. column drivers master others slaves. master column driver supplies signals slave column drivers drivers. resistor oscillation connected OSC1 OSC2 pins master. These pins slaves left open. signals from system through D15, through A16, CSB, OEB, WEB, UBEB, RDY, RESETB, DOFFB) connected parallel with column drivers. pull-up resistor connected pin. TEST used test open connected when system constructed.
DOFFB RESETB Control (CSB, OEB, WEB, UBEB)
OSC1
PULSE FRMB DOFFB REFRHB
driver
Master
OSC2
Slave Y240
Y240
Scan direction Scan direction
driver
Y240 Slave
Y240 Slave
µPD16662
CHIP POWER-UP SEQUENCE
recommended apply power following sequence: VCC2 VCC1 input VDD, sure apply drive voltages end.
VCC2
VCC1
more
Input A16, CSB, OEB, WEB, UBEB, D15, DOFFB) RESETB
VCC2 more longer
VDDnote
VEEnote
more
Note have turned same time. Caution Turn power chip sequence reverse above.
µPD16662
EXAMPLE CONNECTION INTERNAL SCHOTTKY BARRIER DIODE MODULE REINFORCE POWER
(Use Schottky barrier diodes with less.)
VCC1
Diodes enclosed dotted line above figure must connected when other than (GND).
µPD16662
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings +25°C)
Parameter Supply voltage Supply voltage Input/output voltage Input/output voltage Input/output voltage Operating temperature Storage temperature Symbol VCC1 VCC2 VI/O1 VI/O2 VI/O3 Tstg Ratings -0.5 +6.5 -0.5 +4.5 -0.5 VCC1 -0.5 VCC2 -0.5 VCC1 +125 Unit Note Note Note Note Note Note Remark
Notes signals (FRMB, STB, DOUTB, PULSE) 3.3-V signals (MS, DIR, PL1, through A16, CSB, OEB, WEB, UBEB, RDY, through D15, RESETB, OSC1, OSC2, DOFFB, TEST1, BMODE, REFRHB) Liquid crystal power (V0, through Y240) Recommend Operating Conditions +70°C,
Parameter Supply voltage Supply voltage Input voltage Input voltage input voltage input voltage External resistor Symbol VCC1 VCC2 ROSC MIN. T,B,D TYP. MAX. VCC1 VCC2 VCC1 T,B,D Unit Note Note Remark
Notes signals (FRMB, STB, PULSE) 3.3-V signals (MS, DIR, PL1, through A16, CSB, OEB, WEB, UBEB, RDY, through D15, RESETB, OSC1, OSC2, DOFFB, TEST1, BMODE, REFRHB)
µPD16662
Characteristics (Unless otherwise specified, VCC1 VCC2 +70°C)
Parameter High-level input voltage (1), VCC1 Low-level input voltage (1), VCC1 High-level input voltage (2), VCC2 Low-level input voltage (2), VCC2 High-level input voltage (2), VCC2 Low-level input voltage (2), VCC2 High-level output voltage (1), VCC1 Low-level output voltage (1), VCC1 High-level output voltage (2), VCC1 Low-level output voltage (2), VCC1 High-level output voltage (3), VCC2 Low-level output voltage (3), VCC2 Input leakage current Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VCC1 VCC2 VCC2 VCC2 VCC2 MIN. VCC1 VCC1 TYP. MAX. Unit Note Note Note Note Note Note Note Remark
VOL1 VOH2 VCC1
Note Note
VOL2 VOH3 VCC2
Note Note Note
VOL3
Other than TEST pin, VCC2
Note
Input leakage current Display operating current consumption Display operating current consumption Display operating current consumption Display operating current consumption Liquid crystal deiver output resistance
IMAS1
Pull down (TEST pin), VCC2 Master, VCC1 Note
IMAS2
Master, VCC2
Note
ISLV1
Slave, VCC1
Note
ISLV2
Slave, VCC2
Note
Note
Notes signal (FRMB, STB, PULSE) 3.3-V signal (MS, DIR, PL1, through A16, CSB, OEB, WEB, UBEB, RDY, through D15, RESETB, DOFFB, TEST1, BMODE) DOUTB REFRHB through RDY, OSC2 pins Frame frequency: output: load, accessed through D15, through A16, UBEB GND, CSB, OEB, VCC2) Resistance between pins (any when load current (ION flows through through Y240.
µPD16662
Characteristics Display Data Transfer Timing Master mode (Unless otherwise specified, VCC1 VCC2 +70°C, frame frequency: (fOSC 181.44 kHz), output load:
Parameter clock cycle time high-level width low-level width rise time fall time FRMB delay time FRMB delay time Symbol tCYC tCWH tCWL tPSF tPFS MIN. TYP. 16/fOSC 8/fOSC 8/fOSC MAX. Unit Remark
tCYC
tCWL (output)
tCWH
VCC1 VCC1 tPSF FRMB (output) tPFS tPSF tPFS VCC1 VCC1
µPD16662
Slave mode (Unless otherwise specified, VCC1 VCC2 +70°C)
Parameter clock cycle time high-level width low-level width rise time fall time FRMB setup time FRMB hold time Symbol tcyc tCWH tCWL TSFR tHFR MIN. TYP. MAX. Unit Remark
tCYC
tCWL (input)
tCWH
VCC1 VCC1 tSFR FRMB (input) tHFR tSFR tHFR VCC1 VCC1
µPD16662
Parameters common master/slave (Unless otherwise specified, VCC1 VCC2 +70°C)
Parameter Output delay time (L1, DOUTB) Output delay time through Y240) Symbol tDOUT1 tDOUT2 MIN. TYP. MAX. Unit Remark output load output load
(output)
VCC1
tDOUT1 DOUTB
tDOUT1 VCC1
tDOUT2
tDOUT2
Y240
µPD16662
Characteristics Drawing Access Timing (Unless otherwise specified, VCC1 VCC2 +70°C, frame frequency: (fOSC 181.44 kHz))
Parameter OEB/WEB recovery time Address setup time Address hold time output delay time float time Ready status time (without conflict) Ready status time (with conflict) Data access time (read cycle) Data float time (read cycle) time (read cycle) time (read cycle) Write pulse width (write cycle Write pulse width (write cycle Data setup time (write cycles Data hold time (write cycles time (write cycles time (write cycles Reset pulse width time time Symbol tRYR tRYZ tRYF1 tRYF2 tACS tCSOE tOECS tWP1 tWP2 tCSWE tWECS tWRES tRDOE tRDWE Note Note MIN. 1200 TYP. MAX. Unit Note Note Note Note Note Note Note Remark
Notes Load circuit
VCC2
Load circuit
VCC2
display affected time from rising long. recommended that tRDOE tRDWE 1000 less.
µPD16662
OEB/WEB recovery time
VCC2 VCC2
OEB/WEB
Read cycle
UBEB VCC2 VCC2
VCC2 tCSOE tRDOE tOECS VCC2 VCC2 tRYR tRYF VCC2 Hi-z tACS Hi-z VCC2 VCC2 tRYZ VCC2
µPD16662
Write cycle writing display data)
UBEB VCC2 VCC2
VCC2
tCSWE
tRDOE
tWECS VCC2 VCC2
tRYR Hi-z VCC2
tRYF
tRYZ VCC2 tWP1 Hi-z
VCC2 VCC2
Write cycle writing gray level palette)
UBEB VCC2 VCC2
VCC2
tCSWE
tWECS VCC2 VCC2 tWP2
Hi-z
VCC2 VCC2
µPD16662
Reset pulse width power application
tWRES RESETB VCC2
VCC2
With power stabilized
RESETB
VCC2 tWRES
Characteristics Oscillation (VCC2 +70°C)
Parameter Oscillation frequency Frame frequency Symbol fOSC MIN. 61.7 TYP. 73.3 MAX. 84.9 Unit Remark External resistor: External resistor:
RELATION BETWEEN OSCILLATION FREQUENCY, FRAME FREQUENCY, FREQUENCY
relation between oscillation frequency, frame frequency, frequency follows: Frame frequency Oscillation frequency
frequency
Oscillation frequency
µPD16662
Reference
Semiconductor Device Reliability/Quality Control System (C10983E) Semiconductor Device Mounting Technology Manual TCP, Package (C10535E) (MF-232)
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
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