Release Notes Simulation M68HC08AZ60 RELEASE NOTES SIMULATION M68

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Release Notes Simulation M68HC08AZ60 RELEASE NOTES SIMULATION M68

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Release Notes Simulation 68HC08ASZ60
Release Notes Simulation M68HC08AZ60
RELEASE NOTES SIMULATION M68HC08AZ60 V5.3 List Features.2 List fixed Bugs List known Bugs.2 Simulated Parts HC08AZ60
Release Notes Simulation 68HC08ASZ60
RELEASE NOTES SIMULATION M68HC08AZ60 V5.3
List Features
List fixed Bugs
List known Bugs
Simulated Parts HC08AZ60
Ports general-purpose ports simulated. simulate outer world, there each port memory mapped register, which contains value corresponding port pins. name these registers "PortXVal" where letter corresponding port e.g. "PortAVal". each "PortXVal" register, exists each available separate memory mapped registers "PortXBitY", where letter corresponding port number e.g. "PortABit0". "PortXBitY" register zero, means that correspending "PortXVal" register cleared, otherwise set. Registers: PTA, PTB, PTC, PTD, PTE, PTF, PTG, PTH: Port Data Registers, simulated DDRA, DDRB, DDRC, DDRD, DDRE, DDRF, DDRG, DDRH: Data Direction Registers, simulated
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Release Notes Simulation 68HC08ASZ60 PortXVal: memory mapped register port PortXBitY: memory mapped register port
Clock Generator Module (CGM) Clock Generator Module generates base clock signal, CGMOUT, from which system clocks derived. CGMOUT based either crystal clock, CGMXCLK, divided phase-locked loop (PLL) clock, CGMVCLK, divided two. simulated cycles based CGMOUT clock divided two. clock some Components based CGMXCLK which operates frequency crystal. reach that time behaviour these components correct relation simulated cycles, module also simulated. Registers: PCTL: This Control Register PLL. funtionality PLLF flag simulated therefore interrupt will generated. PLLIE PLLF PLLON Interrupt Enable Bit, simulated. Flag Bit, simulated Bit, simulated Base Clock Select Bit, simulated unimplemented, reads
PBWC: bandwidth Control Register, internal functionality simulated therefore flags PBWC register have function. AUTO LOCK Automatic Bandwidth Control Bit, simulated. Lock Indicator Bit, simulated Acquisition Mode Bit, simulated Crystal Loss Detect Bit, simulated
PPG: programming register, upper four bits contains frequency multiplier. lower bits contains hardware center-of-range linear multiplier have specific function simulation. Multiplier Select Bits (MUL7.4), simulated Range Select (VRS7.4), simulated
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Release Notes Simulation 68HC08ASZ60
Analog-to-Digital Converter (ADC) This device contains analog-to-digital converter with multiplexedinputs which shares functionality with port overrides port logic forcing that input ADC. That means that corresponding virtual "PortXVal" register write access port data register. read access from port data register will return latched value "DDRX" set. DDRX cleared corresponding used ADC, zero returned. Registers: This memory mapped registers will serve control "pins" ATD0.ATD14 which share pins with Port Port Each register used apply "analog value" bit) corresponding "ATD0.ATD14". Reading from "ATD0.ATD14" will return actual value this side-effects). ADSCR: Status Control Register, values 011111 (0x0f 11111 (0x1F) CH0.4 bits effect simulation. COCO AIEN ADCO conversion complete bit, simulated interrupt enable bit, simulated continous conversion bit, simulated channel select bits, simulated
ADR: Data Register, simulated ADICLK: Input Clock Register. usage external clock also simulated, that means ADICLK controls external clock CGMXCLK frequency used input clock. ADIV clock prescaler bits, simulated ADICLK simulated write effect, reads always zero
Serial Peripheral Interface (SPI) This device serial peripheral interface which shares pinswith port Slave Select functionality pin) simulated. simulated delay time between write SPDR start transmission half single time (only Master mode). Slave mode, transmission started after write access memory
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Release Notes Simulation 68HC08ASZ60 mapped "SPIValue" register. Because serial clock frequency second device configured, frequency value configured Slave. overrides port logic forcing that input/output SPI. That means that corresponding virtual "PortEVal" register write access port data register. Registers: SPCR: Control Register SPRIE SPMSTR CPOL CPHA SPWOM SPTIE Receiver Interrupt Enable Bit, simulated Master Bit, simulated simulated simulated simulated Enable Bit, simulated Transmit Interrupt Enable Bit, simulated
SPSCR: Status Control Register SPRF Receiver Full Bit, simulated ERRIE Error Interrupt Enable Bit, simulated OVRF Overflow Bit, simulated MODF simulated SPTE Transmitter Empty Bit, simulated MODFEN simulated Baudrate Select Bits, simulated
SPDR: Data Register, simulated SPIValue: This memory mapped register simulates outer world, that means data register second device.
Serial Communication Interface (SCI) This device contains Serial Communications Interface which shares pinswith port overrides port logic forcing that input/output SCI. That means that corresponding virtual "PortEVal" register write access port data register. memory mapped registers "SCIInput/SCIInputH" "SerialInput" serve send characters Module. memory mapped registers "SCIOutput/SCIOutputH" "SerialOutput" contain characters sent from
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Release Notes Simulation 68HC08ASZ60 Module. Registers: SCC1: Control Register LOOPS ENSCI TXINV WAKE ILTY Loop Mode Select Bit, simulated Enable Bit, simulated Transmitter Inversion Bit, simulated physical data) Mode, characters, simulated Wakeup Condition, currently supported Idle Line Type Bit, simulated Parity Enable Bit, simulated Parity Bit, Odd/Even, simulated
SCC2: Control Register SCTIE TCIE SCRIE ILIE Transmitter Interrupt Enable Bit, simulated Transmission Complete Interrupt Enable Bit, simulated Reciever Interrupt Enable Bit, simulated Idle Line Interrupt Enable Bit, simulated Transmitter Enable Bit, simulated Receiver Enable Bit, simulated Receiver Wakeup Bit, simulated Send Break Bit, simulated
SCC3: Control Register Received (ninth received character), when receiving characers, copy Reset effect Transmitted (ninth transmitted character), Reset effect Reserved, reads zero ORIE Receiver Overrun Interrupt Enable Bit, simulated NEIE Receiver Noise Error Interrupt Enable Bit, simulated FEIE Receiver Framing Error Interrupt Enable Bit, simulated PEIE Receiver Parity Error Interrupt Enable Bit, simulated SCS1: Status Register SCTE Tansmitter Empty Bit, simulated
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Release Notes Simulation 68HC08ASZ60 SCRF IDLE Transmission Complete Bit, simulated Reseiver Full Bit, simulated Receiver Idle Bit, simulated Receiver Overrun Bit, simulated Receiver Noise Flag Bit, simulated Receiver Framing Error Bit, simulated Receiver Parity Error Bit, simulated
SCS2: Status Register Unimplemented, reads zero Break Flag Bit, simulated Reception Progress Flag Bit; because physical transmission takes place, flag only reset when receiver dedects idle character.
SCDR: Data Register, simulated SCBR: Baud Rate Register SCP1,0 SCR2.0 Unimplemented, reads zero Baud Rate Prescaler Bits, simulated Reserved, reads zero Baud Rate Select Bits, simulated
SCIInput: This memory mapped register will serve send character SCI. This value will received from read through read access SCDR. ninth taken from SCIInputH register. read access SCIInput specified meaning. character send SCIInputH: This memory mapped register will serve send character SCI. contains ninth bit. This register must written before SCIInput register. read access SCIInputH specified meaning. unused ninth send
SCIOutput: This memory mapped register will serve receive character which sent from SCI. value received SCIOutput triggered through write access SCDR.
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Release Notes Simulation 68HC08ASZ60 ninth written SCIOutputH register. write access SCIOutput specified meaning. character send from
SCIOutputH: This memory mapped register will serve receive character which sent from SCI. contains ninth bit. write access SCIOutput specified meaning. unused ninth send from
SerialInput: This memory mapped register alias SCIInput egister serve connect terminal window. ninth supported. read access SerialInput specified meaning. data from terminal window
SerialOutput: This memory mapped register alias SCIOutput egister serve connect terminal window. ninth supported. write access SerialOutput specified meaning. data sent from terminal window
Modulo Timer (TIM) This device contains modulo timer. This timer operate free-running counter modulo up-counter. Registers: TSC: Timer Status Control Register TOIE TSTOP TRST Overflow Flag Bit, simulated Overflow Interrupt Enable Bit, simulated Stop Bit, simulated Reset Bit, simulated unused Prescaler Select Bits, simulated
TCNTH: Counter Register High, simulated
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Release Notes Simulation 68HC08ASZ60
TCNTL: Counter Register Low, simulated TMODH: Modulo Register High, simulated TMODL: Modulo Register Low, simulated
Timer Interface (TIMA) This component contains channel timer interface that provides timing reference with input capture, output compare pulse width modulation functions. input capture function, TIMA shares pins with general purpose ports simulate falling/raising edge input capture function, corresponding bits memory mapped register PortEVal PortFVal must used. channel Registers: TASC: Timer Status Control register TOIE TSTOP TRST Overflow Flag Bit, simulated Overflow Interrupt Enable Bit, simulated Stop Bit, simulated Reset Bit, simulated unused Prescaler Select Bits, simulated
TACNTH: TIMA Counter Register High, simulated TACNTL: TIMA Counter Register Low, simulated TAMODH: TIMA Modulo Register High, simulated TAMODL: TIMA Modulo Register Low, simulated TASCx: TIMA Channel Status Control Register
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Release Notes Simulation 68HC08ASZ60 CHxF HxIE LSxB LSxA HxMAX hannel Flag Bit, simulated hannel Interrupt Enable Bit, simulated Select simulated Select simulated dge/Level Select Bits, simulated dge/Level Select Bits, simulated Toggle Overflow Bit, simulated Channel Maximum Duty Cycle Bit, simulated
TACHxH: Timer Channel Register High, simulated TACHxL: Timer Channel Register Low, simulated Timer Interface (TIMB) This device contains channel timer interface that provides timing reference with input capture, output compare pulse width modulation functions. input capture function, TIMB shares pins with general purpose port simulate falling/raising edge input capture function, corresponding bits memory mapped register PortFVal must used. channel Registers: TBSC: Timer Status Control Register TOIE TSTOP TRST Overflow Flag Bit, simulated Overflow Interrupt Enable Bit, simulated Stop Bit, simulated Reset Bit, simulated unused Prescaler Select Bits, simulated
TBCNTH: TIMB Counter Register High, simulated TBCNTL: TIMB Counter Register Low, simulated TBMODH: TIMB Modulo Register High, simulated TBMODL: TIMB Modulo Register Low, simulated
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Release Notes Simulation 68HC08ASZ60
TBSCx: TIMB Channel Status Control Register CHxF Channel Flag Bit, simulated ChxIE Channel Interrupt Enable Bit, simulated MS0B Mode Select simulated MsxA Mode Select simulated ELSxB Edge/Level Select Bits, simulated ELSxA Edge/Level Select Bits, simulated TOVx Toggle Overflow Bit, simulated CHxMAX Channel Maximum Duty Cycle Bit, simulated
TBCHxH: Timer Channel Register High, simulated TBCHxL: Timer Channel Register Low, simulated
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Release Notes Simulation M68HC08AZ60 RELEASE NOTES SIMULATION M68

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