ATV5000 Application Example: Controller This application note sho

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ATV5000 Application Example: Controller This application note sho

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CMOS
ATV5000 Application Example: Controller
This application note shows ATV5000 complex programmable logic device used implement simple Controller. includes description controller function implementation using ATV5000. ABELsource code included reference, also available from factory floppy disk. Direct Memory Access (DMA) controller peripheral device used system perform block data transfers between memories devices. generates addresses control necessary perform Figure Internal Block Diagram transfer. controller improves system performance transferring data directly between devices instead using CPU. ATV5000 high-density programmable logic device, featuring logic cells flip-flops. This application takes advantage buried registers store increment decrement addresses word count. counters easily implemented with minimal logic using T-type registers. high count easily accommodate 16-bit bi-directional data address buses.
Programmable Logic Device Application Note
DATA
DATA
ADDR
ADDR
DEST ADDR
WORD COUNT
CONTROL STATE MACHINE
DREQ DACK HOLD HLDA M/IO
COMMAND
0482A
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Controller Description
controller used transfer blocks data between system memory other memory devices. Figure shows basic block diagram controller. interface consists address bus, data bus, some control signals. These signals used load initialization data into controller registers. When controller granted control buses, same signals used transfer data. This example uses i386type control signals. Figure shows this controller would used system. transfer initiated when loads starting source destination addresses, word count, control word into controller registers. external device asserts request signal request DMA. controller then requests control system buses control signals. When grants request, controller acknowledges request starts DMA. data read data then latched written back out. source address destination address multiplexed onto address during read cycle write cycle. system control signals used controller control signals memory device. controller transfers requested number words then relinquishes control. cycle timing shown Figure
Figure System Block Diagram
DATA
ADDRESS M/IO
MEMORY DEVICES
DACK DREQ
HOLD HLDA
CONTROLLER
Figure Timing
READ DREQ DACK HOLD HLDA M/IO, ADDR DATA DONE SRC. SRC. DEST. DEST. SRC. SRC. DEST. DEST. WRITE READ WRITE
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CMOS
ATV5000 Description
ATV5000 68-pin high-density programmable logic device, which features pins eight input-only pins. Each associated with logic macrocell (see Figures Each macrocell input latch, flip-flops, product terms which split into three separate terms, output enable term. driven with either combinatorial registered output. Each flip-flop clock term, asynchronous reset term, asynchronous preset term, configured either D-type T-type flip-flop. addition, there buried logic cells (see Figure Each buried logic cell configured registered combinatorial. registered, each flip-flop clock term, asynchronous reset term, synchronous preset term, configured D-type T-type flip-flop. ATV5000 divided into four quadrants with macrocells buried logic cells each (see Figure universal routes signals four quadrants, regional routes signals within each quadrant. regional buses contain true false feedback signals from each register, from buried logic cells, from eight input-only pins. universal contains regional inputs plus true false signals from each pin.
Figure Logic Cell, Buried Registers, Combinatorial Cell
Figure Logic Cell with Combinatorial Terms, Register Cell
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Figure Logic
Figure Buried Logic Cells
SELECT
LCKn
LOGIC CELL
SELECT
FROM LOGIC CELL
CLOCK OPTION D1/T1
Figure ATV5000 Block Diagram
REGISTER CLOCK LATCH CLOCK PINS 4-15,17 REGISTER CLOCK LATCH CLOCK PINS 52,53,55-65
QUADRANT CELLS
REGIONAL
REGIONAL
QUADRANT CELLS
REGISTER CLOCK LATCH CLOCK PINS 18,19,21-31
BURIED LOGIC CELLS
UNIVERSAL
BURIED LOGIC CELLS
REGISTER CLOCK LATCH CLOCK
CELLS
CELLS
PINS 38-49,51
BURIED LOGIC CELLS QUADRANT
BURIED LOGIC CELLS QUADRANT
REGIONAL
INPUT PINS 1,2,32,34,35, 36,66,68
REGIONAL
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CMOS
Controller Implementation
controller consists three basic functions: system interface, internal address word counters, state machine controller.
System Interface
system interface consists 16-bit bi-directional data bus, 16-bit bi-directional address bus, bi-directional control signals, handshaking signals request control. data address buses assigned pins ATV5000. When controls system buses, buses used inputs receive initialization data. When controller controls system buses, buses bi-directional. data tri-stated while source data read registered, then enabled write data destination. address outputs enabled multiplex source destination address onto bus. signals system clock reset signals. signal used clock registers, that data transfers synchronized system clock. selects whether controller being addressed initialization. Both signals assigned input pins ATV5000, that signals available regional buses quadrants. M/IO signals used control activity. initialization, signal enables write bits address decoded select which register accessed. During transfer, M/IO selects source destination device memory signal selects either read write operation. Both signals assigned pins ATV5000, since they used inputs during initialization outputs during cycle. There sets handshaking signals: request acknowledge (DREQ DACK), request acknowledge (HOLD HLDA). DREQ HLDA assigned input pins ATV5000. HOLD DACK signals assigned pins ATV5000, since they signals output controller.
Address Word Counters
counter functions. Loading accomplished XORing output register with load data, causing flip-flop toggle data does match. outputs address registers multiplexed onto address provide source destination addresses transfer. After each transfer, addresses incremented word count decremented. When word count reaches zero, DONE signal sent state machine, indicating that transfer complete. command word decoded used state machine determine what type will performed. data only used state machine, stored buried registers ATV5000. word consists three bits: bits which indicate whether source destination memory devices, third which enables start. After complete, enable reset.
State Machine
address word counters store starting addresses, transfer word count, command word. buried registers ATV5000, since data does need directly output. registers used counters which load then increment decrement. load count functions controlled control signals state machine. registers configured T-type flip-flops, that minimum number product terms required implement
state machine provides internal external control signals transfers. also performs handshaking access requests. Figure shows state diagram this machine. state machine starts reset state where waits initialize DMA. next three states perform handshaking request control start DMA. twostate loop used transfer each word. first state reads source data second state writes destination data. When DONE indicates that complete, state machine branches back reset state wait another request. signal will reset state machine abort DMA. control revoked (HLDA de-asserted) during DMA, state machine relinquishes control, suspends transfers, then completes when control granted again. request removed (DREQ de-asserted) during DMA, controller will terminate wait another request. state bits assigned buried registers ATV5000, since they only used internally. external control signals assigned registered pins ATV5000. internal control signals also assigned registered pins that they back universally ATV5000.
ATV5000 Resource Allocation
goal allocating functions available resources ATV5000 group functions which interface each other into same quadrant. This will minimize number signals
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Figure State Diagram
WAIT ENABLE RESET RESET
WAIT REQUEST
DREQ
RESET
DREQ
DREQ
REQUEST CONTROL
HLDA
HLDA DREQ
HLDA RESET
ISSUE ACKNOW.
SM_IO DM_IO
SM_IO DM_IO DEVICE READ
SM_IO DM_IO MEMORY READ
SM_IO DM_IO
MEMORY READ
DEVICE READ
FROM STATES: RESET STATE
DONE
DONE
DONE
DONE
DEVICE WRITE
MEMORY WRITE
MEMORY WRITE
DEVICE WRITE
FROM STATES: RESET STATE
HLDA
HLDA
HLDA
HLDA
STATE
STATE
STATE
STATE
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CMOS
which must routed universal minimize number universal product terms required each logic function. Within quadrant, pins associated logic assigned first, then remaining buried resources assigned. this application, address data interfaces address word counters would ideally located same quadrant. This would minimize universal routing allow counters buried registers. Since there enough resources each quadrant that much logic, functions must divided into smaller pieces. Figure shows logic this application divided allocated into quadrants. buses counters "bit-sliced" create logic blocks which into each quadrant. counters divided creating stages with look-ahead carry between. first quadrant contains five bits data address buses, five bits each counters, carry from each counter. second quadrant contains next five-bit section third quadrant contains last six-bit section. carry bits routed universal next quadrant. state machine command register allocated fourth quadrant. internal control signals generated state machine routed universal quadrants. Each counters would normally require three universal product terms load count functions, since control signals universal. This would mean that each counters needs terms each logic cell. avoid this, regional load control signal created each quadrant each counters, using buried logic cells. counters universal product terms then become regional product terms, counters only require term. Each address assigned combinatorial pin. Each those logic cells buried registers available, which used address counters. logic cell configuration shown Figure Each data assigned registered pin. Each those logic cells additional buried register available, which used word counter. carry bits counters assigned registered pins they routed universally. four state bits required seven, ten, four, four product terms. order provide seven product terms, first state assigned registered allocated terms. other available register that logic cell assigned state bits which only required four product terms. logic cell configuration shown Figure state which required product terms assigned registered allocated three terms. control signals from state machine (both internal external) were assigned registered cells. other available buried registers those logic cells were assigned remaining state command register bits. This application uses five input pins, pins flipflops. There three input pins left unassigned. Quadrants each have three buried registers three buried logic cells left unassigned. Quadrant buried register three buried logic cells left unassigned. Quadrant three logic cells, four buried registers, buried logic cells left unassigned. equations node assignments used implement design given ABELsource file this application note.
Summary
This example shows ATV5000 used implement complex function. controller design uses many features ATV5000. requires dedicated input pins large number pins. internal counters control buried logic without sacrificing pins. design which presented simplified controller, meant show basic functions. interface timing tailored particular system. design also provides example describe device features using ABELhigh level descriptive language.
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Figure Resource Allocation
QUADRANT
D<4.0> CARRY CARRY
QUADRANT
D<9.5>
A<4.0>
A<9.5>
CARRY CARRY
CARRY CARRY
CONTROL
QUADRANT
QUADRANT
A<15.10>
STATE MACH.
DONE
M/IO HOLD DACK
D<15.10>
HLDA
DREQ
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CMOS
CMOS
ABELSource Code
module DMAC title 'DMA Controller Example ATV5000 Atmel Corporation (408)436-4333 Applications Hotline Wendey Mueller Sept. 1992' DMAC device 'P5000'; CLK,CS_,RST HLDA,DREQ D0,D1,D2,D3 D4,D5,D6,D7 D8,D9,D10,D11 D12,D13,D14,D15 A0,A1,A2,A3 A4,A5,A6,A7 A8,A9,A10,A11 A12,A13,A14,A15 R_W,M_IO HOLD,DACK ST0,ST1 ST2,ST3 EN,SM_IO,DM_IO DMA_EN,BUS_OE CNTEN,LATEN CNT0,CNT1,CNT2,CNT3 CNT4,CNT5,CNT6,CNT7 CNT8,CNT9,CNT10,CNT11 CNT12,CNT13,CNT14,CNT15 SA0,SA1,SA2,SA3 SA4,SA5,SA6,SA7 SA8,SA9,SA10,SA11 SA12,SA13,SA14,SA15 DA0,DA1,DA2,DA3 DA4,DA5,DA6,DA7 DA8,DA9,DA10,DA11 DA12,DA13,DA14,DA15 SCARRY1,SCARRY2 DCARRY1,DCARRY2 CCARRY1,CCARRY2 DONE LDSRC1,LDSRC2,LDSRC3 LDDST1,LDDST2,LDDST3 LDCNT1,LDCNT2,LDCNT3 1,2,32; 34,35; 4,5,6,7 istype 'reg_d,buffer'; 8,18,19,21 istype 'reg_d,buffer'; 22,23,38,39 istype 'reg_d,buffer'; 40,41,42,43 istype 'reg_d,buffer'; 9,10,11,12 istype 'com,buffer'; 13,24,25,26 istype 'com,buffer'; 27,28,44,45 istype 'com,buffer'; 46,47,48,49 istype 'com,buffer'; 55,56 istype 'reg_d,buffer'; 57,58 istype 'reg_d,buffer';
52,53 istype 'reg_d,buffer'; node 160,162 istype 'reg_d,buffer'; node 163,164,165 istype 'reg_d,buffer'; 59,60 istype 'reg_d,buffer'; 61,62 istype 'reg_d,buffer'; node 121,122,123,124 istype 'reg_t,buffer'; node 125,134,135,136 istype 'reg_t,buffer'; node 137,138,147,148 istype 'reg_t,buffer'; node 149,150,151,152 istype 'reg_t,buffer'; node 766,767,768,769 istype 'reg_t,buffer'; node 770,779,780,781 istype 'reg_t,buffer'; node 782,783,793,794 istype 'reg_t,buffer'; node 795,796,797,798 istype 'reg_t,buffer'; node 126,127,128,129 istype 'reg_t,buffer'; node 130,139,140,141 istype 'reg_t,buffer'; node 142,143,153,154 istype 'reg_t,buffer'; node 155,156,157,158 istype 'reg_t,buffer'; 14,29 istype 'reg_d,buffer'; 15,30 istype 'reg_d,buffer'; 17,31 istype 'reg_d,buffer'; istype 'com,buffer'; node 173,179,185 istype 'com,buffer'; node 174,180,186 istype 'com,buffer'; node 175,181,187 istype 'com,buffer';
C,K,X,Z,U,D,H,L .C.,.K.,.X.,.Z.,.U.,.D.,1,0; "CREATE BUSES DATABUS [D15.D0]; "data DATA [D4.D0]; DATB [D9.D5]; DLSB [D7.D0]; ADDR [A15.A0]; ALSB [A7.A0];
DATC [D15.D10];
"address
WRDCNT [CNT15.CNT0]; "word count CNTLSB [CNT7.CNT0]; CNTA [CNT4.CNT0]; CNTB [CNT9.CNT5]; SRCADR [SA15.SA0]; "source address
CNTC [CNT15.CNT10];
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SRCA [SA4.SA0]; SRCB [SA9.SA5]; SRCLSB [SA7.SA0];
SRCC [SA15.SA10];
DSTADR [DA15.DA0]; "destination address DSTA [DA4.DA0]; DSTB [DA9.DA5]; DSTC [DA15.DA10]; DSTLSB [DA7.DA0]; COMMAND [EN,DM_IO,SM_IO]; "command register STMACH [ST3,ST2,ST1,ST0]; "state bits STDATA "state machine outputs "DEFINE STATES [0,0,0,0]; [0,0,0,1]; [0,0,1,0]; [0,0,1,1]; [0,1,0,0]; [0,1,0,1]; [0,1,1,0]; [0,1,1,1]; [1,0,0,0]; [1,0,0,1]; [1,0,1,0]; [1,0,1,1];
"Register select initialization register selected Command register Source address register Destination address register Word count register EQUATIONS M_IO.OE DMA_EN; R_W.OE DMA_EN; "M_IO control outputs during
ADDR (!BUS_OE SRCADR.FB) (BUS_OE DSTADR.FB); ADDR.OE DMA_EN;
"Select source destination address "Address output during
DATABUS.D (DATABUS LATEN) "Clock data input (DATABUS.FB !LATEN); "LATEN true DATABUS.CK !CLK; DATABUS.OE BUS_OE; "Data output destination during COMMAND.D [D2,D1,D0]; "load command register COMMAND.CK !CS_ !A0; COMMAND.AR DONE; LDSRC1 !CS_ "create regional controls LDSRC2 !CS_ "source address counter LDSRC3 !CS_ LDDST1 !CS_ !A0; "create regional controls LDDST2 !CS_ !A0; "destination address counter LDDST3 !CS_ !A0;
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LDCNT1 !CS_ LDCNT2 !CS_ LDCNT3 !CS_ "create regional load controls "word counter
"Source address counter 16-bit up-counter parallel load stages with look-ahead carry between SRCC.T ((SRCC.FB SRCC.FB) CNTEN SCARRY2 SCARRY1 (DATC.FB SRCC.FB) LDSRC3; SRCB.T ((SRCB.FB SRCB.FB) CNTEN SCARRY1 (DATB.FB SRCB.FB) LDSRC2; SRCA.T ((SRCA.FB SRCA.FB) CNTEN (DATA.FB SRCA.FB) LDSRC1; SRCADR.CK CLK; SCARRY1.D (SRCA.FB ^h1E) CNTEN SCARRY1.FB !CNTEN; SCARRY1.CK CLK; SCARRY2.D (SRCB.FB ^h1F) CNTEN SCARRY2.FB !CNTEN; SCARRY2.CK CLK; "count "load "count "load "count "load
"source address stage carry
"source address stage carry
"Destination address counter 16-bit up-counter parallel load stages with look-ahead carry between DSTC.T ((DSTC.FB DSTC.FB) CNTEN DCARRY2 DCARRY1 (DATC.FB DSTC.FB) LDDST3; DSTB.T ((DSTB.FB DSTB.FB) CNTEN DCARRY1 (DATB.FB DSTB.FB) LDDST2; DSTA.T ((DSTA.FB DSTA.FB) CNTEN (DATA.FB DSTA.FB) LDDST1; DSTADR.CK CLK; DCARRY1.D (DSTA.FB ^h1E) CNTEN DCARRY1.FB !CNTEN; DCARRY1.CK CLK; DCARRY2.D (DSTB.FB ^h1F) CNTEN DCARRY2.FB !CNTEN; DCARRY2.CK CLK; "count "load "count "load "count "load
"destination address stage carry
"destination address stage carry
"Word counter 16-bit down-counter parallel load 3-stages with look-ahead carry between CNTC.T ((CNTC.FB CNTC.FB) CNTEN CCARRY2 CCARRY1 (DATC.FB CNTC.FB) LDCNT3; CNTB.T ((CNTB.FB CNTB.FB) CNTEN CCARRY1 (DATB.FB CNTB.FB) LDCNT2; CNTA.T ((CNTA.FB CNTA.FB) CNTEN (DATA.FB CNTA.FB) LDCNT1; WRDCNT.CK CLK; CCARRY1.D (CNTA.FB ^h01) CNTEN CCARRY1.FB !CNTEN; CCARRY1.CK CLK; CCARRY2.D (CNTB.FB ^h00) CNTEN CCARRY2.FB !CNTEN; CCARRY2.CK CLK; "count "load "count "load "count "load
"word count stage carry
"word count stage carry
DONE (CNTC.FB CCARRY1 CCARRY2; "Detects when complete STMACH.CK CLK; STDATA.CK CLK;
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"State Machine Controller "Inputs: "Outputs: STATE_DIAGRAM STMACH STATE "Reset, idle state !RST) THEN enabled, state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE "else, wait enable WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; STATE "DMA enabled, wait request (!EN RST) THEN disabled reset, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (DREQ) THEN requested, state WITH STDATA.D [0,1,0,0,0,0,0,1]; ENDWITH; ELSE "else, wait request WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; STATE (!EN RST) THEN WITH STDATA.D ELSE (!DREQ) THEN WITH STDATA.D ELSE (HLDA) THEN WITH STDATA.D ELSE WITH STDATA.D "DMA requested, issue request disabled reset, return state [0,1,0,0,0,0,0,0]; ENDWITH; request removed, return state [0,1,0,0,0,0,0,0]; ENDWITH; control granted, state [0,1,0,0,0,0,1,1]; ENDWITH; "else, wait control [0,1,0,0,0,0,0,1]; ENDWITH;
STATE "Bus granted, issue acknowledge (!EN RST) THEN disabled reset, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (!DREQ) THEN request removed, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (!HLDA) THEN control revoked, return state WITH STDATA.D [0,1,0,0,0,0,0,1]; ENDWITH; ELSE (SM_IO !DM_IO) THEN "Start DMA: Memory Device WITH STDATA.D [0,1,1,0,1,0,1,1]; ENDWITH; ELSE (!SM_IO DM_IO) THEN "Start DMA: Device Memory WITH STDATA.D [0,1,1,0,0,0,1,1]; ENDWITH; ELSE (SM_IO DM_IO) THEN "Start DMA: Memory Memory WITH STDATA.D [0,1,1,0,1,0,1,1]; ENDWITH; ELSE (!SM_IO !DM_IO) THEN "Start DMA: Device Device WITH STDATA.D [0,1,1,0,0,0,1,1]; ENDWITH; STATE "DMA cycle, memory read (!DREQ RST) THEN request removed reset, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [1,0,1,1,0,1,1,1]; ENDWITH; STATE "DMA cycle, device write (!DREQ DONE) THEN request removed, reset done, "return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (!HLDA) THEN control revoked, return state WITH STDATA.D [0,1,0,0,0,0,0,1]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [0,1,1,0,1,0,1,1]; ENDWITH; STATE "DMA cycle, device read
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CMOS
(!DREQ RST) THEN request removed reset, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [1,0,1,1,1,1,1,1]; ENDWITH; STATE "DMA cycle, memory write (!DREQ DONE) THEN request removed, reset done, "return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (!HLDA) THEN control revoked, return state WITH STDATA.D [0,1,0,0,0,0,0,1]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [0,1,1,0,0,0,1,1]; ENDWITH; STATE "DMA cycle, memory read (!DREQ RST) THEN request removed reset, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [1,0,1,1,1,1,1,1]; ENDWITH; STATE "DMA cycle, memory write (!DREQ DONE) THEN request removed, reset done, "return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (!HLDA) THEN control revoked, return state WITH STDATA.D [0,1,0,0,0,0,0,1]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [0,1,1,0,1,0,1,1]; ENDWITH; STATE S10: "DMA cycle, device read (!DREQ RST) THEN request removed reset, return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [1,0,1,1,0,1,1,1]; ENDWITH; STATE S11: (!DREQ DONE) THEN "DMA cycle, device write request removed, reset done, "return state WITH STDATA.D [0,1,0,0,0,0,0,0]; ENDWITH; ELSE (!HLDA) THEN control revoked, return state WITH STDATA.D [0,1,0,0,0,0,0,1]; ENDWITH; ELSE "else, continue transfer WITH STDATA.D [0,1,1,0,0,0,1,1]; ENDWITH;
"This test vectors initializes source address, destination address, "word count command data. TEST_VECTORS
[SRCLSB,DSTLSB,CNTLSB,COMMAND]) [00A, [00A, 0B0, [00A, 0B0, 003, [00A, 0B0, 003,
"This test vectors performs transfer using addresses word "count which loaded. TEST_VECTORS 0B0, 0B0,
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06B, 0BF, 06B, 0BF, 06B, 0BF, 06B, 0BF,
0B0, 0B0, 0B0, 0B0, 0B1, 0B1, 0B2, 0B2, 0B3, 0B3, 0B4,
0FF,
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CMOS

ATV5000 Application Example: Controller This application note sho

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