ATV2500 Application Example: Video Frame Grabber This application

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ATV2500 Application Example: Video Frame Grabber This application

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ATV2500 Application Example: Video Frame Grabber
This application note shows ATV2500 used incorporate multiple control logic functions into single programmable logic device. design example which used simple NTSC video frame grabber. ATV2500 used generate control addressing frame grabber. application note includes description frame grabber design implementation using ATV2500. ABELsource code ATV2500 included reference also available from applications group floppy disk. macrocell contains flip-flops, product terms which split into three separate terms, output enable. Each flip-flop clock term asynchronous reset term. Groups four eight flip-flops each have common synchronous preset product term. Each macrocell feedback path from from each register. This makes possible bury both registers either combinatorial output input pin. global routes pins register feedbacks every logic cell.
Programmable Logic Device Application Note
ATV2500 Description
ATV2500 high density programmable logic device which features pins input-only pins. Each associated with logic macrocell (see Figures output configured either combinatorial registered. Each Figure ATV2500 Output Logic, Registered
Frame Grabber Design Considerations
basic idea behind frame grabber sample store frame video data. Once data stored, re-displayed, enhanced saved file. this example, input video signal converted with converter stored RAM. display
Figure ATV2500 Output Logic, Combinatorial
S0*S1 S0+S1*S5 D/T1 D/T2 S0*S1
Note:
This diagram shows equivalent logic functions, necessarily actual circuit implementation.
0251B
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buffered data, addresses cycled data converted back video signal through converter.
Video Basics
NTSC (National Television Standards Committee) composite video signal standard used most television video systems North America. signal composed four components: luminance (brightness), chrominance (color), audio synchronization. NTSC video image frame composed scan lines. Each frame actually divided into fields 262.5 scan lines which interlaced. fields start with vertical sync period followed scan lines (see Figure Each scan line consists horizontal sync period, color burst video information (see Figure
Timing
frame grabber samples entire video frame, including horizontal vertical sync periods. Then, order generate video image from stored data, data simply converted back analog signal same rate sampled. refresh rate each field 59.94 (16.683 field), which means refresh rate whole frame 29.97 (33.366 frame). number bits each sample sampling frequency determine resolution reconstructed video image. 8-bit sample size chosen this example since 8-bit converters readily available. 8-bit sample size will allow levels intensity, which plenty purposes this design. order generate reasonable image, sample frequency should least twice NTSC color burst frequency 3.579545 MHz. sample frequency chosen, which little more than twice color burst frequency. total number samples required each frame will 253245 (7.5 16.683
Interface
through output. When button released, data sampled. converted video signal monitored detect vertical sync. Once vertical sync detected, 253245 samples from video input stored. Following sampling, addresses continuously cycled creating frozen image. captured frame will displayed until button depressed again, causing another frame data sampled stored. necessary start sampling during vertical sync period since 253245 samples will contain entire frame. addresses cycled, vertical sync portion video signal will generated every 16.683 However, data were used purpose other than just display, would more convenient have data start known point video signal.
Frame Grabber Implementation
schematic frame grabber shown Figure three basic functions are: conversion, control address generation, storage sampled data. conversions, Samsung KSV3100A selected. both 8-bit converter 10-bit converter, along with necessary pre-amplifier input clamping circuit single device. KSV3100A device connected recommended operating circuit data sheet. system clock used clock both conversions. ATV2500 used implement control addresses frame grabber. functions include vertical sync detector, control state machine address counter. receives mode signal from switch, 8-bit data from converter system clock signal. generates control signals 18-bit address RAM. 256K static module used frame buffer memory. write enable signal from controller allows
user interface consists single button. When button depressed, frame grabber will pass video signal Figure Field Timing
VERTICAL BLANKING INTERVAL
VERTICAL SYNC PULSES
HORIZONTAL SCAN LINE
Figure Horizontal Scan Line
WHITE BLACK SYNC
HORIZONTAL SYNC PERIOD COLOR BURST VIDEO INFORMATION
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converted data stored during sampling. output enable signal used enable/disable onto data bus. External buffers used enable data from output back into when video signal passed through data being sampled. ples. entire vertical sync period times horizontal scan width. Within that period, there pulses around when signal sync level. Each these pulses will correspond about samples. vertical sync detector 7-bit counter which will count every sample with zero value. counts such samples, then detected pulses vertical sync period. counter divided into parts, that maximum number product terms required count four. carry from first stage used enable second stage. counter will increment whenever input data zero. non-zero value will cause counter reset. When count reaches 127, signal asserted.
State Machine
ATV2500 Control Address Functions
ATV2500 used implement control address functions. These include vertical sync detector, control state machine address counter. Figure shows block diagram ATV2500 functions.
Vertical Sync Detector
During horizontal vertical sync periods, signal drops sync level which lower than other portion signal. This level will clamped converter will become zero value when converted. horizontal sync pulse about which will correspond about samFigure Frame Grabber Schematic
state machine generates internal control address generation external control signals RAM. state dia-
D7-0 MODE
ATV2500 ADDR[17.0] A17-0 A/D_OE MODE
256K A17-0 DI7-0 DO7-0
ADOE RAM_OE RAMOE RAM_WE RAMWE
CONTROL DATAIN[7.0]
74244 KSV3100A VIDEO_OUT
D9-0
DAOUT
GATE
74244 AD7-0 VREF ADIN
DACLK ADCLK VIDEO_IN DATAOUT[7.0]
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gram shown Figure When MODE input changes, indicating that frame grabber should sample frame, state machine waits signal. After vertical sync detected, sets control signals write sampled data entire frame. When address counter reaches correct number samples, state machine changes control signals read sampled data. addresses cycled that sampled frame continuously displayed.
Address Counter
shaded boxes indicate resources which used another signal generated same macrocell. empty boxes indicate available resources. this design, four input pins, associated macrocell plus additional buried registers available expansion design changes.
Notes Test Vectors
address counter controlled INCAD control signal from state machine. INCAD signal asserted, address will increment until counter reaches final address correct number samples. When INCAD signal asserted, final address reached, counter resets 18-bit address counter broken into 9-bit stages, that maximum number product terms required each count less than carry from first stage used enable second stage.
Resource Allocation
order test that address counter rolls over correct count, more than 253245 test vectors would required, which exceeds number vectors allowed ABEL. There ways around this problem. first method register preload function PLASIM. counter preloaded with count near maximum count, then allowed roll over. However, since JEDSIMdoes support preload function JEDEC file checked. Another method change terminal count value smaller value, that counter would reach terminal
address counters registered pins ATV2500. MSBs each stage counter have more than eight product terms, they require entire macrocell. LSBs each stage less than eight product terms, buried register available each those macrocells (see Figure control bits generated state machine combinatorial outputs with less than four product terms, buried registers available each those macrocells (see Figure state bits vertical sync detect counter bits assigned available buried registers. Assignment pins only dependent board layout, since there signal routing limitations ATV2500. Buried logic assigned available resources. Table shows worksheet used allocate logic functions this application ATV2500 resources. Figure ATV2500 Function Block Diagram
DATAIN[7.0] VERTICAL SYNC DETECT
Figure Controller State Diagram
POWER-UP
1100 LIVE VIDEO (RESET) ELSE MODE
1100 WAIT SYNC ELSE VERTSYNC
CONTROL STATE MACHINE
RAM_WE RAM_OE A/D_DE
0101 SAMPLE ELSE
MODE
ENDFR INCAD
ADDRTC
ADDRESS COUNTER
1011 DISPLAY ELSE
ADDR[17.0]
MODE
Note:
Outputs: RAMWE, RAMOE, ADOE, INCAD
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count fewer vectors. Since equations altered, this method could only used ABELsimulation. third method register synchronous presets load counter. This method that used this design. registers which preset allocated same ATV2500 synchronous preset groups. spare input (PRELD) used control preset test vectors. Using this method, vectors also used programmer. vice. ATV2500 ideal this application since enough inputs accept control data signals, necessary I/Os generate addresses control. ability combine separate terms each macrocell allows maximum usage available resources. functions which require large numbers product terms have split into smaller pieces. functions which require fewer numbers product terms waste entire macrocell. leftover buried logic those macrocells used control state machine vertical sync detector.
Summary
this example, address control functions greatly simplified using single complex programmable logic
Table ATV2500 ABEL Pin/Node Assignment Worksheet Example Input
SignaI
MODE
Input
SignaI
(PRELD)
SignaI
RAMWE RAMOE ADOE INCAD
SignaI
SYNC0 SYNC1 SYNC2 SYNC3 SYNCARRY SYNC4 SYNC5 SYNC6 ENDFR ADCARRY
SignaI
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ABELSource Code
module CONTROL title 'Application example ATV2500 Frame Grabber Controller Atmel Corporation (408)436-4333 Applications Hotline Wendey Mueller January 1992' CONTROL device 'P2500'; CLK,MODE D0,D1,D2,D3 D4,D5,D6,D7 A0,A1,A2,A3,A4 A5,A6,A7,A8,A9 A10,A11,A12,A13,A14 A15,A16,A17 RAMWE,RAMOE ADOE,INCAD ADCARRY,SYNCARRY ENDFR ST0,ST1 SYNC0,SYNC1,SYNC2 SYNC3,SYNC4,SYNC5 SYNC6 1,2; "system clock mode signal from button 17,18,19,20; "digitized video signal from 21,22,23,37; 4,5,6,7,8 istype 'reg,buffer'; "RAM address outputs 9,13,14,11,15 istype 'reg,buffer'; 12,24,25,16,26 istype 'reg,buffer'; 27,28,29 istype 'reg,buffer'; 32,33 istype 'com,buffer'; "RAM control signals 34,35 istype 'com,buffer'; "address counter control istype 'com,buffer'; "vertical sync detected 52,45 istype 'reg,buffer'; "counter carry signals istype 'reg,buffer'; "end frame detected 59,60 istype 'reg,buffer'; "state bits 41,42,43 istype 'reg,buffer'; 44,46,49 istype 'reg,buffer'; "vertical sync detect istype 'reg,buffer'; "counter
node node node node node node
"Use spare input preset signal testing counter PRELD
C,X,Z,H,L,P .C.,.X.,.Z.,1,0,.P.; "Create buses DATA ADDR ADDRA ADDRB SYNC SYNCA SYNCB STMACH [D7.D0]; [A17.A0]; [A8.A0]; [A17.A9]; [SYNC6.SYNC0]; [SYNC3.SYNC0]; [SYNC6.SYNC4]; [ST1,ST0]; "data "address counter "address counter "address counter "vertical sync detect counter "vertical sync detect counter "vertical sync detect counter "state bits
"Define states [0,0]; [0,1]; [1,0]; [1,1];
EQUATIONS "256K address counter increment when INCAD true address reached frame, otherwise reset ADDRA.D ((ADDRA.FB INCAD !ENDFR); "LSB stage ADDRA.CK CLK; ADCARRY.D (ADDRA.FB 510); "synchronous carry from stage ADCARRY.CK CLK;
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ADDRB.D ((ADDRB.FB INCAD !ENDFR ADCARRY) "MSB stage (ADDRB.FB INCAD !ENDFR !ADCARRY); ADDRB.CK CLK; ENDFR.D (ADDR.FB 253243); "set ENDFR when address reaches 253243 ENDFR.CK CLK; "Use synchronous preset simplify testing address counter "preloading with value close last address. A17.SP A16.SP A15.SP A14.SP A12.SP A11.SP A10.SP A8.SP PRELD; PRELD; PRELD; PRELD; PRELD; PRELD; PRELD; PRELD;
"Vertical sync detect counter increment data otherwise reset SYNCA.D (SYNCA.FB (DATA "LSB stage SYNCA.CK CLK; SYNCARRY.D (SYNCA.FB 14); "synchronous carry from stage SYNCARRY.CK CLK; SYNCB.D (SYNCB.FB (DATA SYNCARRY SYNCB.FB (DATA !SYNCARRY; SYNCB.CK CLK; "MSB stage
(SYNC.FB 127); "set vertical sync detected count reaches STMACH.CK CLK; "State Machine Controller "Inputs: MODE,VS,ENDFR "Outputs: RAMWE,RAMOE,ADOE,INCAD STATE_DIAGRAM STMACH STATE RAMWE RAMOE ADOE INCAD (MODE) THEN ELSE STATE RAMWE RAMOE ADOE INCAD (VS) THEN ELSE STATE RAMWE RAMOE ADOE "Reset, live video
capture mode, state "else wait mode change "Wait vertical sync signal
"Vertical sync detected, start sampling data "else wait vertical sync "Sample video data
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INCAD (ENDFR) THEN ELSE STATE RAMWE RAMOE ADOE INCAD (!MODE) THEN ELSE @RADIX @CONST ACNT @CONST SCNT
"Frame capture complete "else continue sampling "Display frame data
"Reset, display live video "else continue display frame data
TEST_VECTORS [CLK,MODE,DATA,PRELD] ENDFR]) "check that vertical sync detector resets data start sample display sequence [00, [01, [00, [00, "simulate vertical sync @REPEAT @CONST SCNT SCNT [SCNT,0, [7F, [00, [01, mode 00000,0 00000,0 00000,0 00000,0
00000,0 00000,0 00000,0 00001,0
"state machine detected vertical sync @REPEAT @CONST ACNT ACNT [00, [00, [00,
started sampling.
ACNT, 00100,0 00101,0
"Use preset preload count value near largest address value. [00, 3DD02,0 [00, 3DD03,0 "Allow counter reach largest address roll over. State machine "then changes controls display sampled data. @CONST ACNT 3DD03; @REPEAT @CONST ACNT ACNT [00, ACNT, [00, 3DD3B,0 [00, 3DD3C,1 [00, 00000,0 [00, 00001,0 [00, 00002,0
ABEL, JEDSIM, PLASIMmay registered trademarks oth-
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