BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER merged combination bipol

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER merged combination bipol

Datasheet Thumbnail

Top Searches for this datasheet

BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
merged combination bipolar technology gives these devices interface flexibility beyond reach standard logic buffers power driver arrays. UCN5821A eight-bit CMOS shift register CMOS control circuitry, eight CMOS data latches, eight bipolar current-sinking Darlington output drivers. BiMOS devices have much higher data-input rates than original BiMOS circuits. With logic supply, they will typically operate better than MHz. With supply, significantly higher speeds obtained. CMOS inputs compatible with standard CMOS NMOS logic levels. circuits require appropriate pull-up resistors. using serial data output, drivers cascaded interface applications requiring additional drive lines.
Data Sheet 26185.12A
CLOCK SERIAL DATA LOGIC GROUND LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE POWER GROUND
SHIFT REGISTER
LATCHES
FEATURES
Dwg. PP-026A
Data Input Rate CMOS, NMOS, Compatible Internal Pull-Down Resistors Low-Power CMOS Logic Latches High-Voltage Current-Sink Outputs Automotive Capable
ABSOLUTE MAXIMUM RATINGS 25°C Free-Air Temperature
Output Voltage, VOUT Logic Supply Voltage, Input Voltage Range, -0.3 Continuous Output Current, IOUT Package Power Dissipation, 2.08 Operating Temperature Range, -20°C +85°C Storage Temperature Range, -55°C +150°C
*Derate rate 16.7 mW/°C above +25°C
Caution: CMOS devices have input static protection susceptible damage when exposed extremely high static electrical charges.
Always order complete part number: UCN5821A
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
TYPICAL INPUT CIRCUITS
CLOCK SERIAL DATA LOGIC GROUND
FUNCTIONAL BLOCK DIAGRAM
LOGIC SUPPLY SERIAL DATA STROBE OUTPUT ENABLE (ACTIVE LOW)
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
STROBE OUTPUT ENABLE
BIPOLAR
POWER GROUND
Dwg. FP-013A
Dwg. EP-010-3
CLOCK SERIAL DATA
Number Outputs (IOUT
25°C 100% 100% 100% 100% 100% 100% 100%
Max. Allowable Duty Cycle Ambient Temperature 40°C 50°C 60°C 70°C 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100%
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
7.2K
Dwg. A-14,314
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright 1985, 1995, Allegro MicroSystems, Inc.
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
ELECTRICAL CHARACTERISTICS +25°C, (unless otherwise specified).
Limits Characteristic Output Leakage Current Symbol ICEX VOUT VOUT +70°C Collector-Emitter Saturation Voltage VCE(SAT) IOUT IOUT IOUT Input Voltage VIN(0) VIN(1) Input Resistance Supply Current IDD(ON) Driver Driver Driver IDD(OFF) Drivers OFF, Inputs Drivers OFF, Inputs Test Conditions Min. 10.5 Max. Units
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
CLOCK DATA STROBE
Serial Data present input transferred shift register logic logic transition CLOCK input pulse. succeeding CLOCK pulses, registers shift data information towards SERIAL DATA OUTPUT. SERIAL DATA must appear input prior rising edge CLOCK input waveform. Information present register transferred respective latch when STROBE high (serial-to-parallel conversion). latches will continue accept data long STROBE held high. Applications where latches bypassed (STROBE tied high) will require that ENABLE input high during serial data entry. When ENABLE input high, output buffers disabled (OFF) without affecting information stored latches shift register. With ENABLE input low, outputs controlled state latches.
OUTPUT ENABLE
Dwg. A-12,627
TIMING CONDITIONS
(VDD +25°C, Logic Levels Ground)
Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) Minimum Data Active Time After Clock Pulse (Data Hold Time) Minimum Data Pulse Width Minimum Clock Pulse Width Minimum Time Between Clock Activation Strobe Minimum Strobe Pulse Width Output Transition
Typical Time Between Strobe Activation
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input Serial Data Strobe Output Input
Logic Level High Logic Level Irrelevant
Latch Contents Output Enable
Output Contents
Present State
Previous State
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
Dimensions Inches
0.014 0.008
0.430 0.280 0.240
0.300
0.070 0.045
0.100 0.775 0.735
0.005
0.210
0.015
0.150 0.115 0.022 0.014
Dwg. MA-001-16A
Dimensions Millimeters (Based 25.4
0.355 0.204
10.92 7.11 6.10
7.62
1.77 1.15
2.54 19.68 18.67
0.13
5.33
0.39
3.81 2.93 0.558 0.356
Dwg. MA-001-16A
NOTES: Lead thickness measured seating plane below. Lead spacing tolerance non-cumulative. Exact body lead configuration vendor's option within limits shown.
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
This page intentionally left blank
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
This page intentionally left blank
BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER
BiMOS (Series 5800) DABiC (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS SELECTION GUIDE
Function
SERIAL-INPUT LATCHED DRIVERS 8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 9-Bit 10-Bit (active pull-downs) 12-Bit (active pull-downs) 20-Bit (active pull-downs) 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers) PARALLEL-INPUT LATCHED DRIVERS 4-Bit 8-Bit 8-Bit SPECIAL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver Addressable 28-Line Decoder/Driver
Output Ratings
-120
Part Number
5895 5821 5841 5842 5829 5810-F 5811 5812-F 5818-F 5833 5832
5800 5815 5801
1.25
5804 6817
Current maximum specified test condition, voltage maximum rating. specification sustaining voltage limits. Negative current defined coming (sourcing) output.
Complete part number includes additional characters indicate operating temperature range package style. Internal transient-suppression diodes included inductive-load protection.
Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements design products. Components made under military approvals will accordance with approval requirements. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringements patents other rights third parties which result from use.
Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

BiMOS 8-BIT SERIAL-INPUT, LATCHED DRIVER merged combination bipol

Top Searches for this datasheet

Other recent searches