The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

Opcode Instruction CALL rel16 CALL rel32 CALL r/m16 CALL r/m32 CALL pt


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



41.1 CALL-Call Procedure
Opcode Instruction CALL rel16 CALL rel32 CALL r/m16 CALL r/m32 CALL ptr16:16 CALL ptr16:32 CALL m16:16 CALL m16:32 Description
Call near, relative, displacement relative next instruction Call near, relative, displacement relative next instruction Call near, absolute indirect, address given r/m16 Call near, absolute indirect, address given r/m32 Call far, absolute, address given operand Call far, absolute, address given operand Call far, absolute indirect, address given m16:16 Call far, absolute indirect, address given m16:32
Description
Saves procedure linking information stack branches procedure (called procedure) specified with destination (target) operand. target operand specifies address first instruction called procedure. This operand immediate value, general-purpose register, memory location. This instruction used execute four different types calls:
Near call-A call procedure within current code segment (the segment currently
pointed register), sometimes referred intrasegment call.
call-A call procedure located different segment than current code segment,
sometimes referred intersegment call.
Inter-privilege-level call-A call procedure segment different privilege
level than that currently executing program procedure.
Task switch-A call procedure located different task.
latter call types (inter-privilege-level call task switch) only executed protected mode. section titled "Calling Procedures Using CALL RET", additional information near, far, inter-privilege-level calls. Chapter Task Management, Intel Architecture Software Developer's Manual, Volume information performing task switches with CALL instruction. Near Call. When executing near call, processor pushes value register (which contains offset instruction following CALL instruction) onto stack (for later return-instruction pointer). processor then branches address current code segment specified with target operand. target operand specifies either absolute offset code segment (that offset from base code segment) relative offset signed displacement relative current value instruction pointer register, which points instruction following CALL instruction). register changed near calls.
Intel Architecture Software Developer's Manual
41-31
near call, absolute offset specified indirectly general-purpose register memory location (r/m16 r/m32). operand-size attribute determines size target operand bits). Absolute offsets loaded directly into register. operand-size attribute upper bytes register cleared resulting maximum instruction pointer size bits. (When accessing absolute offset indirectly using stack pointer [ESP] base register, base value used value before instruction executes.) relative offset (rel16 rel32) generally specified label assembly code, machine code level, encoded signed, 32-bit immediate value. This value added value register. with absolute offsets, operand-size attribute determines size target operand bits). Calls Real-Address Virtual-8086 Mode. When executing call real-address virtual-8086 mode, processor pushes current value both registers onto stack return-instruction pointer. processor then performs "far branch" code segment offset specified with target operand called procedure. Here target operand specifies absolute address either directly with pointer (ptr16:16 ptr16:32) indirectly with memory location (m16:16 m16:32). With pointer method, segment offset called procedure encoded instruction, using 4-byte (16-bit operand size) 6-byte (32-bit operand size) address immediate. With indirect method, target operand specifies memory location that contains 4-byte (16-bit operand size) 6-byte (32-bit operand size) address. operand-size attribute determines size offset bits) address. address loaded directly into registers. operand-size attribute upper bytes register cleared Calls Protected Mode. When processor operating protected mode, CALL instruction used perform following three types calls:
call same privilege level. call different privilege level (inter-privilege level call). Task switch (far call another task).
protected mode, processor always uses segment selector part address access corresponding descriptor LDT. descriptor type (code segment, call gate, task gate, TSS) access rights determine type call operation performed. selected descriptor code segment, call code segment same privilege level performed. selected code segment different privilege level code segment non-conforming, general-protection exception generated.) call same privilege level protected mode very similar carried real-address virtual-8086 mode. target operand specifies absolute address either directly with pointer (ptr16:16 ptr16:32) indirectly with memory location (m16:16 m16:32). operand-size attribute determines size offset bits) address. code segment selector descriptor loaded into register, offset from instruction loaded into register. Note that call gate (described next paragraph) also used perform call code segment same privilege level. Using this mechanism provides extra level indirection preferred method making calls between 16-bit 32-bit code segments. When executing inter-privilege-level call, code segment procedure being called must accessed through call gate. segment selector specified target operand identifies call gate. Here again, target operand specify call gate segment selector either directly with pointer (ptr16:16 ptr16:32) indirectly with memory location (m16:16 m16:32). processor obtains segment selector code segment
41-32
Intel Architecture Software Developer's Manual
instruction pointer (offset) from call gate descriptor. (The offset from target operand ignored when call gate used.) inter-privilege-level calls, processor switches stack privilege level called procedure. segment selector stack segment specified currently running task. branch code segment occurs after stack switch. (Note that when using call gate perform call segment same privilege level, stack switch occurs.) stack, processor pushes segment selector stack pointer calling procedure's stack, (optional) parameters from calling procedures stack, segment selector instruction pointer calling procedure's code segment. value call gate descriptor determines many parameters copy stack.) Finally, processor branches address procedure being called within code segment. Executing task switch with CALL instruction, somewhat similar executing call through call gate. Here target operand specifies segment selector task gate task being switched (and offset target operand ignored.) task gate turn points task, which contains segment selectors task's code stack segments. also contains value next instruction that executed before task suspended. This instruction pointer value loaded into register that task begins executing again this next instruction. CALL instruction also specify segment selector directly, which eliminates indirection task gate. Chapter Task Management, Intel Architecture Software Developer's Manual, Volume detailed information mechanics task switch. Note that when execute task switch with CALL instruction, nested task flag (NT) EFLAGS register TSS's previous task link field loaded with tasks selector. Code expected suspend this nested task executing IRET instruction, which, because flag set, will automatically previous task link return calling task. (See "Task Linking" Chapter Intel Architecture Software Developer's Manual, Volume more information nested tasks.) Switching tasks with CALL instruction differs this regard from instruction which does flag therefore does expect IRET instruction suspend task. Mixing 16-Bit 32-Bit Calls. When making calls between 16-bit 32-bit code segments, calls should made through call gate. call from 32-bit code segment 16-bit code segment, call should made from first KBytes 32-bit code segment. This because operand-size attribute instruction only 16-bit return address offset saved. Also, call should made using 16-bit call gate that 16-bit values will pushed stack. Chapter Mixing 16-Bit 32-Bit Code, Intel Architecture Software Developer's Manual, Volume more information making calls between 16-bit 32-bit code segments.
Operation
near call THEN near relative call instruction pointer within code segment limit THEN #GP(0); THEN OperandSize THEN stack large enough 4-byte return address THEN #SS(0); Push(EIP); DEST; DEST rel32 ELSE OperandSize stack large enough 2-byte return address THEN #SS(0); Push(IP); (EIP DEST) 0000FFFFH; DEST rel16 ELSE near absolute call instruction pointer within code segment limit THEN #GP(0); OperandSize
Intel Architecture Software Developer's Manual
41-33
THEN stack large enough Push(EIP); DEST; DEST r/m32 ELSE OperandSize stack large enough Push(IP); DEST 0000FFFFH; call real-address virtual-8086 mode THEN OperandSize THEN stack large enough 6-byte return address THEN #SS(0); instruction pointer within code segment limit THEN #GP(0); Push(CS); padded with high-order bits Push(EIP); DEST[47:32]; DEST ptr16:32 [m16:32] DEST[31:0]; DEST ptr16:32 [m16:32] ELSE OperandSize stack large enough 4-byte return address THEN #SS(0); instruction pointer within code segment limit THEN #GP(0); Push(CS); Push(IP); DEST[31:16]; DEST ptr16:16 [m16:16] DEST[15:0]; DEST ptr16:16 [m16:16] 0000FFFFH; clear upper bits call Protected mode, virtual-8086 mode THEN segment selector target operand null THEN #GP(0); segment selector index within descriptor table limits THEN #GP(new code segment selector); Read type access rights selected segment descriptor; segment type conforming nonconforming code segment, call gate, task gate, THEN #GP(segment selector); Depending type access rights CONFORMING-CODE-SEGMENT; NONCONFORMING-CODE-SEGMENT; CALL-GATE; TASK-GATE; TASK-STATE-SEGMENT; CONFORMING-CODE-SEGMENT: THEN #GP(new code segment selector); segment present THEN #NP(new code segment selector); OperandSize THEN stack large enough 6-byte return address THEN #SS(0); instruction pointer within code segment limit THEN #GP(0); Push(CS); padded with high-order bits Push(EIP); DEST(NewCodeSegmentSelector); segment descriptor information also loaded CS(RPL) DEST(offset); ELSE OperandSize stack large enough 4-byte return address THEN #SS(0); instruction pointer within code segment limit THEN #GP(0); Push(CS); Push(IP); DEST(NewCodeSegmentSelector); segment descriptor information also loaded CS(RPL) DEST(offset) 0000FFFFH; clear upper bits END; NONCONFORMING-CODE-SEGMENT: (RPL CPL) (DPL CPL) THEN #GP(new code segment selector); segment present THEN #NP(new code segment selector); stack large enough return address THEN #SS(0); tempEIP DEST(offset) OperandSize=16 THEN tempEIP tempEIP 0000FFFFH; clear upper bits tempEIP outside code segment limit THEN #GP(0); OperandSize 4-byte return address THEN #SS(0); 2-byte return address THEN #SS(0); DEST r/m16
41-34
Intel Architecture Software Developer's Manual
THEN Push(CS); padded with high-order bits Push(EIP); DEST(NewCodeSegmentSelector); segment descriptor information also loaded CS(RPL) CPL; tempEIP; ELSE OperandSize Push(CS); Push(IP); DEST(NewCodeSegmentSelector); segment descriptor information also loaded CS(RPL) CPL; tempEIP; END; CALL-GATE: call gate THEN #GP(call gate selector); call gate present THEN #NP(call gate selector); call gate code-segment selector null THEN #GP(0); call gate code-segment selector index outside descriptor table limits THEN #GP(code segment selector); Read code segment descriptor; code-segment segment descriptor does indicate code segment code-segment segment descriptor THEN #GP(code segment selector); code segment present THEN #NP(new code segment selector); code segment non-conforming THEN MORE-PRIVILEGE; ELSE SAME-PRIVILEGE; END; MORE-PRIVILEGE: current 32-bit THEN TSSstackAddress code segment (DPL (TSSstackAddress limit THEN #TS(current selector); newSS TSSstackAddress newESP stack address; ELSE 16-bit TSSstackAddress code segment (DPL (TSSstackAddress limit THEN #TS(current selector); newESP TSSstackAddress; newSS TSSstackAddress stack segment selector null THEN #TS(stack segment selector); stack segment selector index within descriptor table limits THEN #TS(SS selector); Read code segment descriptor; stack segment selector's code segment stack segment code segment stack segment writable data segment THEN #TS(SS selector); stack segment present THEN #SS(SS selector); CallGateSize THEN stack does have room parameters plus bytes THEN #SS(SS selector); CallGate(InstructionPointer) within code segment limit THEN #GP(0); newSS; segment descriptor information also loaded newESP; CS:EIP segment descriptor information also loaded Push(oldSS:oldESP); from calling procedure temp parameter count from call gate, masked bits; Push(parameters from calling procedure's stack, temp) Push(oldCS:oldEIP); return address calling procedure ELSE CallGateSize stack does have room parameters plus bytes THEN #SS(SS selector); (CallGate(InstructionPointer) FFFFH) within code segment limit THEN #GP(0); newSS; segment descriptor information also loaded newESP; CS:IP segment descriptor information also loaded Push(oldSS:oldESP); from calling procedure temp parameter count from call gate, masked bits; Push(parameters from calling procedure's stack, temp) Push(oldCS:oldEIP); return address calling procedure
Intel Architecture Software Developer's Manual
41-35
CodeSegment(DPL) task gate present THEN #NP(task gate selector); Read segment selector task-gate descriptor; segment selector local/global local index within limits THEN #GP(TSS selector); Access descriptor GDT; descriptor specifies that busy (low-order bits 00001) THEN #GP(TSS selector); present THEN #NP(TSS selector); SWITCH-TASKS (with nesting) TSS; within code segment limit THEN #GP(0); END; TASK-STATE-SEGMENT: descriptor indicates available THEN #GP(TSS selector); present THEN #NP(TSS selector); SWITCH-TASKS (with nesting) within code segment limit THEN #GP(0); END;
Flags Affected
flags affected task switch occurs; flags affected task switch does occur.
Protected Mode Exceptions
#GP(0) target offset destination operand beyond code segment limit. segment selector destination operand null. code segment selector gate null. memory operand effective address outside segment limit. register used access memory contains null segment selector. #GP(selector) code segment gate selector index outside descriptor table limits. segment descriptor pointed segment selector destination operand conforming-code segment, nonconforming-code segment, call gate, task gate, task state segment. nonconforming-code segment equal segment's segment selector greater than CPL. conforming-code segment greater than CPL. from call-gate, task-gate, segment descriptor less than than call-gate, task-gate, TSS's segment selector.
41-36
Intel Architecture Software Developer's Manual
segment descriptor segment selector from call gate does indicate code segment. segment selector from call gate beyond descriptor table limits. code-segment obtained from call gate greater than CPL. segment selector local/global local. segment descriptor specifies that busy available. #SS(0) pushing return address, parameters, stack segment pointer onto stack exceeds bounds stack segment, when stack switch occurs. memory operand effective address outside segment limit. #SS(selector) pushing return address, parameters, stack segment pointer onto stack exceeds bounds stack segment, when stack switch occurs. register being loaded part stack switch segment pointed marked present. stack segment does have room return address, parameters, stack segment pointer, when stack switch occurs. #NP(selector) #TS(selector) code segment, data segment, stack segment, call gate, task gate, present. stack segment selector beyond TSS. stack segment selector null. stack segment selector equal code segment being accessed. stack segment descriptor stack segment equal code segment descriptor. stack segment writable data segment. segment-selector index stack segment outside descriptor table limits. #PF(fault-code) #AC(0) page fault occurs. unaligned memory access occurs when alignment checking enabled.
Real-Address Mode Exceptions
memory operand effective address outside segment limit. target offset beyond code segment limit.
Virtual-8086 Mode Exceptions
#GP(0) memory operand effective address outside segment limit. target offset beyond code segment limit. #PF(fault-code) page fault occurs.
Intel Architecture Software Developer's Manual
41-37
#AC(0)
unaligned memory access occurs when alignment checking enabled.
41.2
CBW/CWDE-Convert Byte Word/Convert Word Doubleword
Opcode Instruction CWDE Description sign-extend sign-extend
Description
Double size source operand means sign extension (see "Sign Extension"). (convert byte word) instruction copies sign (bit source operand into every register. CWDE (convert word doubleword) instruction copies sign (bit word register into higher bits register. CWDE mnemonics reference same opcode. instruction intended when operand-size attribute CWDE instruction when operand-size attribute Some assemblers force operand size when used when CWDE used. Others treat these mnemonics synonyms (CBW/CWDE) current setting operand-size attribute determine size values converted, regardless mnemonic used. CWDE instruction different from (convert word double) instruction. instruction uses DX:AX register pair destination operand; whereas, CWDE instruction uses register destination.
Operation
OperandSize instruction THEN SignExtend(AL); ELSE OperandSize instruction CWDE SignExtend(AX);
Flags Affected
None.
Exceptions (All Operating Modes)
None.
41.3
CDQ-Convert Double Quad
entry CWD/CDQ Convert Word Doubleword/Convert Doubleword Quadword.
41-38
Intel Architecture Software Developer's Manual
41.4
CLC-Clear Carry Flag
Opcode Instruction Description Clear flag
Description
Clears flag EFLAGS register.
Operation
Flags Affected
flag cleared flags unaffected.
Exceptions (All Operating Modes)
None.
41.5
CLD-Clear Direction Flag
Opcode Instruction Description Clear flag
Description
Clears flag EFLAGS register. When flag string operations increment index registers (ESI and/or EDI).
Operation
Flags Affected
flag cleared flags unaffected.
Exceptions (All Operating Modes)
None.
Intel Architecture Software Developer's Manual
41-39
41.6
CLI-Clear Interrupt Flag
Opcode Instruction Description Clear interrupt flag; interrupts disabled when interrupt flag cleared
Description
Clears flag EFLAGS register. other flags affected. Clearing flag causes processor ignore maskable external interrupts. flag instruction have affect generation exceptions interrupts. following decision table indicates action instruction (bottom table) depending processor's mode operating IOPL currently running program procedure (top table).
IOPL #GP(0) IOPL IOPL
NOTES: XDon't care NAction column taken YAction column taken
Operation
Executing real-address mode THEN ELSE Executing protected mode THEN IOPL THEN ELSE #GP(0); ELSE Executing Virtual-8086 mode IOPL THEN ELSE #GP(0);
Flags Affected
cleared equal less than IOPL; otherwise, affected. other flags EFLAGS register unaffected.
41-40
Intel Architecture Software Developer's Manual
Protected Mode Exceptions
#GP(0) greater (has less privilege) than IOPL current program procedure.
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
#GP(0) greater (has less privilege) than IOPL current program procedure.
41.7
CLTS-Clear Task-Switched Flag
Opcode Instruction CLTS Description Clears flag
Description
Clears task-switched (TS) flag register. This instruction intended operating-system procedures. privileged instruction that only executed allowed executed real-address mode allow initialization protected mode. processor sets flag every time task switch occurs. flag used synchronize saving context multitasking applications. description flag section titled "Control Registers" Chapter Intel Architecture Software Developer's Manual, Volume more information about this flag.
Operation
CR0(TS)
Flags Affected
flag register cleared.
Protected Mode Exceptions
#GP(0) greater than
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
#GP(0) greater than
Intel Architecture Software Developer's Manual
41-41
41.8
CMC-Complement Carry Flag
Opcode Instruction Description Complement flag
Description
Complements flag EFLAGS register.
Operation
Flags Affected
flag contains complement original value. flags unaffected.
Exceptions (All Operating Modes)
None.
41.9
CMOVcc-Conditional Move
Opcode Instruction CMOVA r16, r/m16 CMOVA r32, r/m32 CMOVAE r16, r/m16 CMOVAE r32, r/m32 CMOVB r16, r/m16 CMOVB r32, r/m32 CMOVBE r16, r/m16 CMOVBE r32, r/m32 CMOVC r16, r/m16 CMOVC r32, r/m32 CMOVE r16, r/m16 CMOVE r32, r/m32 CMOVG r16, r/m16 CMOVG r32, r/m32 CMOVGE r16, r/m16 CMOVGE r32, r/m32 CMOVL r16, r/m16 CMOVL r32, r/m32 CMOVLE r16, r/m16 CMOVLE r32, r/m32 CMOVNA r16, r/m16 CMOVNA r32, r/m32 CMOVNAE r16, r/m16 Description Move above (CF=0 ZF=0) Move above (CF=0 ZF=0) Move above equal (CF=0) Move above equal (CF=0) Move below (CF=1) Move below (CF=1) Move below equal (CF=1 ZF=1) Move below equal (CF=1 ZF=1) Move carry (CF=1) Move carry (CF=1) Move equal (ZF=1) Move equal (ZF=1) Move greater (ZF=0 SF=OF) Move greater (ZF=0 SF=OF) Move greater equal (SF=OF) Move greater equal (SF=OF) Move less (SF<>OF) Move less (SF<>OF) Move less equal (ZF=1 SF<>OF) Move less equal (ZF=1 SF<>OF) Move above (CF=1 ZF=1) Move above (CF=1 ZF=1) Move above equal (CF=1)
41-42
Intel Architecture Software Developer's Manual
CMOVNAE r32, r/m32 CMOVNB r16, r/m16 CMOVNB r32, r/m32 CMOVNBE r16, r/m16 CMOVNBE r32, r/m32 CMOVNC r16, r/m16 CMOVNC r32, r/m32 CMOVNE r16, r/m16 CMOVNE r32, r/m32 CMOVNG r16, r/m16 CMOVNG r32, r/m32 CMOVNGE r16, r/m16 CMOVNGE r32, r/m32 CMOVNL r16, r/m16 CMOVNL r32, r/m32 CMOVNLE r16, r/m16 CMOVNLE r32, r/m32
Move above equal (CF=1) Move below (CF=0) Move below (CF=0) Move below equal (CF=0 ZF=0) Move below equal (CF=0 ZF=0) Move carry (CF=0) Move carry (CF=0) Move equal (ZF=0) Move equal (ZF=0) Move greater (ZF=1 SF<>OF) Move greater (ZF=1 SF<>OF) Move greater equal (SF<>OF) Move greater equal (SF<>OF) Move less (SF=OF) Move less (SF=OF) Move less equal (ZF=0 SF=OF) Move less equal (ZF=0 SF=OF)
Opcode
Instruction CMOVNO r16, r/m16 CMOVNO r32, r/m32 CMOVNP r16, r/m16 CMOVNP r32, r/m32 CMOVNS r16, r/m16 CMOVNS r32, r/m32 CMOVNZ r16, r/m16 CMOVNZ r32, r/m32 CMOVO r16, r/m16 CMOVO r32, r/m32 CMOVP r16, r/m16 CMOVP r32, r/m32 CMOVPE r16, r/m16 CMOVPE r32, r/m32 CMOVPO r16, r/m16 CMOVPO r32, r/m32 CMOVS r16, r/m16 CMOVS r32, r/m32 CMOVZ r16, r/m16 CMOVZ r32, r/m32
Description Move overflow (OF=0) Move overflow (OF=0) Move parity (PF=0) Move parity (PF=0) Move sign (SF=0) Move sign (SF=0) Move zero (ZF=0) Move zero (ZF=0) Move overflow (OF=0) Move overflow (OF=0) Move parity (PF=1) Move parity (PF=1) Move parity even (PF=1) Move parity even (PF=1) Move parity (PF=0) Move parity (PF=0) Move sign (SF=1) Move sign (SF=1) Move zero (ZF=1) Move zero (ZF=1)
Description
CMOVcc instructions check state more status flags EFLAGS register (CF, perform move operation flags specified state condition). condition code (cc) associated with each instruction indicate condition being tested for. condition satisfied, move performed execution continues with instruction following CMOVcc instruction.
Intel Architecture Software Developer's Manual
41-43
These instructions move 32-bit value from memory general-purpose register from general-purpose register another. Conditional moves 8-bit register operands supported. conditions each CMOVcc mnemonic given description column above table. terms "less" "greater" used comparisons signed integers terms "above" "below" used unsigned integers. Because particular state status flags sometimes interpreted ways, mnemonics defined some opcodes. example, CMOVA (conditional move above) instruction CMOVNBE (conditional move below equal) instruction alternate mnemonics opcode 47H. CMOVcc instructions Pentium processor family; however, they supported processors family. Software determine CMOVcc instructions supported checking processor's feature information with CPUID instruction (see "CPUID-CPU Identification" this chapter).
Operation
temp DEST condition TRUE THEN DEST ELSE DEST temp
Flags Affected
None.
Protected Mode Exceptions
#GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions
memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions
#GP(0) #SS(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit.
41-44
Intel Architecture Software Developer's Manual
#PF(fault-code) #AC(0)
page fault occurs. alignment checking enabled unaligned memory reference made.
41.10
CMP-Compare Operands
Opcode Instruction imm8 imm16 EAX, imm32 r/m8, imm8 r/m16, imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description Compare imm8 with Compare imm16 with Compare imm32 with Compare imm8 with r/m8 Compare imm16 with r/m16 Compare imm32 with r/m32 Compare imm8 with r/m16 Compare imm8 with r/m32 Compare with r/m8 Compare with r/m16 Compare with r/m32 Compare r/m8 with Compare r/m16 with Compare r/m32 with
Description
Compares first source operand with second source operand sets status flags EFLAGS register according results. comparison performed subtracting second operand from first operand then setting status flags same manner instruction. When immediate value used operand, sign-extended length first operand. instruction typically used conjunction with conditional jump (Jcc), condition move (CMOVcc), SETcc instruction. condition codes used Jcc, CMOVcc, SETcc instructions based results instruction. "EFLAGS Cross-Reference Condition Codes" shows relationship status flags condition codes.
Operation
temp SRC1 SignExtend(SRC2); ModifyStatusFlags; Modify status flags same manner instruction*)
Flags Affected
flags according result.
Protected Mode Exceptions
#GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) memory operand effective address outside segment limit.
Intel Architecture Software Developer's Manual
41-45
#PF(fault-code) #AC(0)
page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions
memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions
#GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
41.11
CMPS/CMPSB/CMPSW/CMPSD-Compare String Operands
Opcode Instruction CMPS CMPS m16, CMPS m32, CMPSB CMPSW CMPSD Description Compares byte address DS:(E)SI with byte address ES:(E)DI sets status flags accordingly Compares word address DS:(E)SI with word address ES:(E)DI sets status flags accordingly Compares doubleword address DS:(E)SI with doubleword address ES:(E)DI sets status flags accordingly Compares byte address DS:(E)SI with byte address ES:(E)DI sets status flags accordingly Compares word address DS:(E)SI with word address ES:(E)DI sets status flags accordingly Compares doubleword address DS:(E)SI with doubleword address ES:(E)DI sets status flags accordingly
Description
Compares byte, word, double word specified with first source operand with byte, word, double word specified with second source operand sets status flags EFLAGS register according results. Both source operands located memory. address first source operand read from either DS:ESI DS:SI registers (depending address-size attribute instruction, respectively). address second source operand read from either ES:EDI ES:DI registers (again depending address-size attribute instruction). segment overridden with segment override prefix, segment cannot overridden.
41-46
Intel Architecture Software Developer's Manual
assembly-code level, forms this instruction allowed: "explicit-operands" form "no-operands" form. explicit-operands form (specified with CMPS mnemonic) allows source operands specified explicitly. Here, source operands should symbols that indicate size location source values. This explicit-operands form provided allow documentation; however, note that documentation provided this form misleading. That source operand symbols must specify correct type (size) operands (bytes, words, doublewords), they have specify correct location. locations source operands always specified DS:(E)SI ES:(E)DI registers, which must loaded correctly before compare string instruction executed. no-operands form provides "short forms" byte, word, doubleword versions CMPS instructions. Here also DS:(E)SI ES:(E)DI registers assumed processor specify location source operands. size source operands selected with mnemonic: CMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison). After comparison, (E)SI (E)DI registers incremented decremented automatically according setting flag EFLAGS register. flag (E)SI (E)DI register incremented; flag (E)SI (E)DI registers decremented.) registers incremented decremented byte operations, word operations, doubleword operations. CMPS, CMPSB, CMPSW, CMPSD instructions preceded prefix block comparisons bytes, words, doublewords. More often, however, these instructions will used LOOP construct that takes some action based setting status flags before next comparison made. "REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix" this chapter description prefix.
Operation
temp SRC1 SRC2; SetStatusFlags(temp); (byte comparison) THEN THEN (E)SI (E)SI (E)DI (E)DI ELSE (E)SI (E)SI (E)DI (E)DI ELSE (word comparison) THEN (E)SI (E)SI (E)DI (E)DI ELSE (E)SI (E)SI (E)DI (E)DI ELSE doubleword comparison*) THEN (E)SI (E)SI (E)DI (E)DI ELSE (E)SI (E)SI (E)DI (E)DI
Flags Affected
flags according temporary result comparison.
Intel Architecture Software Developer's Manual
41-47
Protected Mode Exceptions
#GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions
memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions
#GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
41.12
CMPXCHG-Compare Exchange
Opcode B0/r B1/r B1/r Instruction CMPXCHG r/m8,r8 CMPXCHG r/m16,r16 CMPXCHG r/m32,r32 Description Compare with r/m8. equal, loaded into r/m8. Else, clear load r/m8 into Compare with r/m16. equal, loaded into r/m16. Else, clear load r/m16 into Compare with r/m32. equal, loaded into r/m32. Else, clear load r/m32 into
Description
Compares value register (depending size operand) with first operand (destination operand). values equal, second operand (source operand) loaded into destination operand. Otherwise, destination operand loaded into register. This instruction used with LOCK prefix allow instruction executed atomically. simplify interface processor's bus, destination operand receives write cycle without regard result comparison. destination operand written back comparison fails; otherwise, source operand written into destination. (The processor never produces locked read without also producing locked write.)
41-48
Intel Architecture Software Developer's Manual
Intel Architecture Compatibility
This instruction supported Intel processors earlier than Intel486 processors.
Operation
accumulator EAX, depending whether byte, word, doubleword comparison being performed*) accumulator DEST THEN DEST ELSE accumulator DEST
Flags Affected
flag values destination operand register equal; otherwise cleared. flags according results comparison operation.
Protected Mode Exceptions
#GP(0) destination located nonwritable segment. memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions
memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions
#GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
Intel Architecture Software Developer's Manual
41-49
41.13
CMPXCHG8B-Compare Exchange Bytes
Opcode Instruction CMPXCHG8B Description Compare EDX:EAX with m64. equal, load ECX:EBX into m64. Else, clear load into EDX:EAX.
Description
Compares 64-bit value EDX:EAX with operand (destination operand). values equal, 64-bit value ECX:EBX stored destination operand. Otherwise, value destination operand loaded into EDX:EAX. destination operand 8-byte memory location. EDX:EAX ECX:EBX register pairs, contain high-order bits contain low-order bits 64-bit value. This instruction used with LOCK prefix allow instruction executed atomically. simplify interface processor's bus, destination operand receives write cycle without regard result comparison. destination operand written back comparison fails; otherwise, source operand written into destination. (The processor never produces locked read without also producing locked write.)
Intel Architecture Compatibility
This instruction supported Intel processors earlier than Pentium processors.
Operation
(EDX:EAX DEST) DEST ECX:EBX ELSE EDX:EAX DEST
Flags Affected
flag destination operand EDX:EAX equal; otherwise cleared. flags unaffected.
Protected Mode Exceptions
#GP(0) destination operand memory location. destination located nonwritable segment. memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
41-50
Intel Architecture Software Developer's Manual
Real-Address Mode Exceptions
destination operand memory location. memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions
#GP(0) #SS(0) #PF(fault-code) #AC(0) destination operand memory location. memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
41.14
CPUID-CPU Identification
Opcode Instruction CPUID Description Processor identification information
Description
Provides processor identification information registers EAX, EBX, ECX, EDX. This information identifies Intel vendor, gives family, model, stepping processor, feature information, cache information. input value loaded into register determines what information returned, shown Table 41-1. Table 41-1. Information Returned CPUID Instruction
Initial Value Information Provided about Processor Maximum CPUID Input Value Pentium® processor Pentium processor later versions Intel486processor that support CPUID instruction). "Genu" "ntel" "ineI" Version Information (Type, Family, Model, Stepping Reserved Reserved Feature Information Cache Information Cache Information Cache Information Cache Information
Intel Architecture Software Developer's Manual
41-51
CPUID instruction executed privilege level serialize instruction execution. Serializing instruction execution guarantees that modifications flags, registers, memory previous instructions completed before next instruction fetched executed (see "Serializing Instructions" Chapter Intel Architecture Software Developer's Manual, Volume When input value register processor returns highest value CPUID instruction recognizes register (see Table 41-1). vendor identification string returned EBX, EDX, registers. Intel processors, vendor identification string "GenuineIntel" follows:
756e6547h "Genu", with nibble 49656e69h "ineI", with nibble 6c65746eh "ntel", with nibble
When input value processor returns version information register feature information register (see Figure 41-1). Figure 41-1. Version Feature Information Registers
Family
Model
Stepping
Processor Type Family (0110B Pentium® Processor Family) Model (Beginning with 0001B)
MMXTechnology CMOV-Cond. Move/Cmp. Inst. MCA-Machine Check Arch. PGE-PTE Global MTRR-Mem. Type Range Reg. APIC-APIC Chip CXS-CMPXCHG8B Inst. MCE-Machine Check Exception PAE-Physical Address Extensions MSR-RDMSR WRMSR Support TSC-Time Stamp Counter PSE-Page Size Extensions DE-Debugging Extensions VME-Virtual-8086 Mode Enhancement FPU-FPU Chip Reserved
version information consists Intel Architecture family identifier, model identifier, stepping processor type. model, family, processor type first processor Intel Pentium family follows:
Model-0001B Family-0110B Processor Type-00B
41-52
Intel Architecture Software Developer's Manual
AP-485, Intel Processor Identification CPUID Instruction (Order Number 241618), Intel Pentium® Processor Specification Update (Order Number 242689), Intel Pentium® Processor Specification Update (Order Number 242480) more information identifying earlier Intel Architecture processors. available processor types given Table 41-2. Intel releases information stepping needed. Table 41-2. Processor Type Field
Type Original Processor Intel OverDrive Processor Dual processor Intel reserved. NOTE: applicable Intel386and Intel486processors.
Encoding
Table 41-3 shows encoding feature flags register. feature flag indicates corresponding feature supported. Software should identify Intel vendor properly interpret feature flags.
Intel Architecture Software Developer's Manual
41-53
Table 41-3. Feature Flags Returned Register (Sheet
Feature FPU-Floating-Point Unit Chip Description Processor contains executes Intel instruction set. Processor supports following virtual-8086 mode enhancements: CR4.VME enables virtual-8086 mode extensions. VME-Virtual-8086 Mode Enhancements CR4.PVI enables protected-mode virtual interrupts. Expansion with software indirection bitmap. EFLAGS.VIF (virtual interrupt flag). EFLAGS.VIP (virtual interrupt pending flag). DE-Debugging Extensions Processor supports breakpoints, including CR4.DE enabling debug extensions optional trapping access registers. Processor supports 4-Mbyte pages, including CR4.PSE enabling page size extensions, modified page directory entries (PDEs), page directory entries, page table entries (PTEs). Processor supports RDTSC (read time stamp counter) instruction, including CR4.TSD that, along with CPL, controls whether time stamp counter read. Processor supports RDMSR (read model-specific register) WRMSR (write model-specific register) instructions. Processor supports physical addresses greater than bits, extended page-table-entry format, extra level page translation tables, 2-MByte pages. CR4.PAE enables this feature. number address bits implementation specific. Pentium® processor supports bits addressing when set. Processor supports CR4.MCE bit, enabling machine check exceptions. However, this feature does define modelspecific implementations machine-check error logging, reporting, processor shutdowns. Machine-check exception handlers might have check processor version model-specific processing exception check presence standard machine-check feature.
PSE-Page Size Extensions
TSC-Time Stamp Counter MSR-Model Specific Registers
PAE-Physical Address Extension
MCE-Machine Check Exception
41-54
Intel Architecture Software Developer's Manual
Table 41-3. Feature Flags Returned Register (Sheet
Feature CX8-CMPXCHG8B Instruction APIC Reserved Processor supports machine-specific memory-type range registers (MTRRs). MTRRs contains fields that indicate processor's MTRR capabilities, including which memory types processor supports, number variable MTRRs processor supports, whether processor supports fixed MTRRs. Processor supports CR4.PGE flag enabling global both PTDEs PTEs. These bits used indicate translation lookaside buffer (TLB) entries that common different tasks need flushed when control register written. Processor supports MCG_CAP (machine check global capability) MSR. MCG_CAP register indicates many banks error reporting MSRs processor supports. Processor supports CMOVcc instruction and, feature flag (bit also set, supports FCMOVcc FCOMI instructions. Description Processor supports CMPXCHG8B (compare exchange bytes) instruction. Processor contains on-chip Advanced Programmable Interrupt Controller (APIC) been enabled available use.
10,11
MTRR-Memory Type Range Registers
PGE-PTE Global Flag
MCA-Machine Check Architecture CMOV-Conditional Move Compare Instructions Reserved
16-22
MMXTechnology
Processor supports instruction set. These instructions operate parallel multiple data elements bytes, words, doublewords) packed into quadword registers memory locations.
24-31
Reserved
When input value processor returns information about processor's internal caches TLBs EAX, EBX, ECX, registers. encoding these registers follows:
least-significant byte register (register indicates number times
CPUID instruction must executed with input value complete description processor's caches TLBs. Pentium® family processors will return
most significant (bit each register indicates whether register contains valid
information (cleared reserved (set
register contains valid information, information contained byte descriptors.
Table 41-4 shows encoding these descriptors.
Intel Architecture Software Developer's Manual
41-55
Table 41-4. Encoding Cache Descriptors
Descriptor Value Null descriptor Instruction TLB: 4K-Byte Pages, 4-way associative, entries Instruction TLB: 4M-Byte Pages, 4-way associative, entries Data TLB: 4K-Byte Pages, 4-way associative, entries Data TLB: 4M-Byte Pages, 4-way associative, entries Instruction cache: Bytes, 4-way associative, byte line size Instruction cache: Bytes, 4-way associative, byte line size Data cache: Bytes, 2-way associative, byte line size Data cache: Bytes, 2-way associative, byte line size Unified cache: 128K Bytes, 4-way associative, byte line size Unified cache: 256K Bytes, 4-way associative, byte line size Unified cache: 512K Bytes, 4-way associative, byte line size Unified cache: Byte, 4-way associative, byte line size Cache Description
first member Pentium processor family will return following information about caches TLBs when CPUID instruction executed with input value
These values interpreted follows:
least-significant byte (byte register 01H, indicating that CPUID
instruction needs executed only once with input value retrieve complete information about processor's caches TLBs.
most-significant four registers (EAX, EBX, ECX, EDX)
indicating that each register contains valid 1-byte descriptors.
Bytes register indicate that processor contains following:
01H-A 32-entry instruction (4-way associative) mapping 4-KByte pages. 02H-A 4-entry instruction (4-way associative) mapping 4-MByte pages. 03H-A 64-entry data (4-way associative) mapping 4-KByte pages.
descriptors registers valid, contain null descriptors. Bytes register indicate that processor contains following:
42H-A 256-KByte unified cache (the cache), 4-way associative, with 32-byte cache line size. 0AH-An 8-KByte data cache (the data cache), 2-way associative, with 32-byte cache line size. 04H-An 8-entry data (4-way associative) mapping 4M-byte pages.
41-56
Intel Architecture Software Developer's Manual
06H-An 8-KByte instruction cache (the instruction cache), 4-way associative, with 32-byte cache line size.
Intel Architecture Compatibility
CPUID instruction supported early models Intel486 processor Intel Architecture processor earlier than Intel486 processor. flag EFLAGS register used determine this instruction supported. procedure able clear this flag, CPUID supported processor running procedure.
Operation
CASE (EAX) highest input value understood CPUID; Pentium processor Vendor identification string; Vendor identification string; Vendor identification string; BREAK; EAX[3:0] Stepping EAX[7:4] Model; EAX[11:8] Family; EAX[13:12] Processor type; EAX[31:12] Reserved; Reserved; Reserved; Feature flags; Figure 41-1 BREAK; Cache information; Cache information; Cache information; Cache information; BREAK; DEFAULT: highest value recognized CPUID reserved, undefined; reserved, undefined; reserved, undefined; reserved, undefined; BREAK; ESAC;
Flags Affected
None.
Exceptions (All Operating Modes)
None.
41.15
CWD/CDQ-Convert Word Doubleword/Convert Doubleword Quadword
Opcode Instruction Description DX:AX sign-extend EDX:EAX sign-extend
Intel Architecture Software Developer's Manual
41-57
Description
Doubles size operand register (depending operand size) means sign extension stores result registers DX:AX EDX:EAX, respectively. instruction copies sign (bit value register into every position register (see"Sign Extension"). instruction copies sign (bit value register into every position register. instruction used produce doubleword dividend from word before word division, instruction used produce quadword dividend from doubleword before doubleword division. mnemonics reference same opcode. instruction intended when operand-size attribute instruction when operand-size attribute Some assemblers force operand size when used when used. Others treat these mnemonics synonyms (CWD/CDQ) current setting operand-size attribute determine size values converted, regardless mnemonic used.
Operation
OperandSize instruction THEN SignExtend(AX); ELSE OperandSize instruction SignExtend(EAX);
Flags Affected
None.
Exceptions (All Operating Modes)
None.
41.16
CWDE-Convert Word Doubleword
entry CBW/CWDE-Convert Byte Word/Convert Word Doubleword.
41-58
Intel Architecture Software Developer's Manual

Other recent searches


TA0283A - TA0283A   TA0283A Datasheet
MP-3Z - MP-3Z   MP-3Z Datasheet
SC-63 - SC-63   SC-63 Datasheet
G97XB - G97XB   G97XB Datasheet
AP-007-SW-E - AP-007-SW-E   AP-007-SW-E Datasheet
AM29F008T - AM29F008T   AM29F008T Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive