Pentium Processor® with MMXTechnology Packaging Information Pinou

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Pentium® Processor with MMXTechnology
Pentium Processor® with MMXTechnology Packaging Information
Pinout
Figure Pentium® Processor with MMXTechnology PPGA Package Pinout Side View
VCC3 VCC3 VCC3 VCC3 STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 PICCLK PICD0 PICD1 VCC3 VCC3 CPUTYP TRST# VCC3 VCC3 VCC3 VCC3 PEN# IGNNE# INIT SMI# VCC3 INTR D/P# VCC3 VCC3 VCC3
VCC3 VCC3
VCC2
VCC2 VCC2 VCC2
VCC2
VCC2 FLUSH# W/R#
EADS# ADSC#
VCC2 DET#
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
RESET
BE7#
BE5#
BE3#
BE1#
D/C#
ADS#
HLDA BREQ
LOCK#
SMIACT# VCC2 PCHK#
APCHK# PBREQ# VCC2
PBGNT# PRDY PHITM# VCC2 HOLD BRDYC# VCC2 BRDY# KEN# EWBE# VCC2 AHOLD
R/S#
WB/WT# PHIT# VCC2 BOFF#
Side View
CACHE# VCC2
MI/O#
VCC2
PM1BP1
FERR# PM0BP0 VCC2
IERR#
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3 VCC3
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
A6174-01
Datasheet
Pentium® Processor with MMXTechnology
Figure Pentium® Processor with MMXTechnology PPGA Package Pinout Bottom Side View
VCC2 VCC2
VCC2
VCC2 VCC3 VCC3
VCC3
VCC3 VCC3 INTR VCC3 D/P# VCC3 R/S# VCC3
FLUSH# VCC2 VCC2
ADSC# EADS#
VCC2 DET#
W/R#
HITM# BUSCHK# BE0# HIT# A20M#
BE2#
BE4#
BE6#
SCYC
D/C#
BE1#
BE3#
BE5#
BE7#
RESET
BREQ HLDA
ADS#
LOCK#
VCC2 SMIACT# PCHK#
VCC2 PBREQ# APCHK# PBGNT#
VCC2 PHITM# PRDY VCC2 HOLD
SMI#
PHIT# WB/WT# BOFF#
INIT IGNNE# VCC3 PEN#
VCC3 VCC3
VCC2 BRDYC# BRDY#
VCC2 EWBE# KEN# VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC2 PM1BP1 VCC2 CACHE# MI/O# AHOLD
Side View
STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 PICD1 VCC3 PICD0 VCC3 PICCLK VCC3 VCC3
VCC2 PM0BP0 FERR# IERR#
TRST# CPUTYP
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
A6173-01
Datasheet
Pentium® Processor with MMXTechnology
8.1.1
Cross Reference
Table Cross-Reference Name Address Data Pins
Location Location Location Location Location
Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 Data AK26 AL25 AK24 AL23 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33
Datasheet
Pentium® Processor with MMXTechnology
Table Cross-Reference Name Control Pins
Location Location Control A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BRDYC# AK08 AJ05 AM02 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 BREQ BUSCHK# CACHE# CPUTYP D/C# D/P# EADS# EWBE# FERR# FLUSH# FRCMC#1 AJ01 AL07 AK04 AE35 AM04 AN07 HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT KEN# LOCK# M/IO# NMI/LINT1 PCHK# PEN# PM0/BP0 PM1/BP1 APIC PICCLK H342 PICD0/[DP EN#] PICD1/[API CEN] AK06 AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# VCC2DET# W/R# WB/WT# AC05 AL03 AC35 AK20 AL17 AB34 AG03 AL01 AM06 AA05 Location Location
Clock Control AK182 [BF0] [BF1] STPCLK#
Dual Processor Private Interface PBGNT# AD04 PBREQ# AE03 PHIT# AA03 PHITM# AC03
NOTES: FRCMC# defined Pentium® processor with MMXtechnology. This should left "NC" tied VCC3 external pull-up resistor Pentium processor with technology. PICCLK V-tolerant-only Pentium processor with technology. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) PICCLK signal quality specification.
Datasheet
Pentium® Processor with MMXTechnology
Table Cross-Reference Name Power, Ground Connect Pins
VCC2 VCC3 AN01 AN03 AN05 AL19 AN35 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
8.1.2
Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected GND. Note: Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with future processor steppings.
8.1.3
Quick Reference
This section gives brief functional description each pins. detailed description, Hardware Interface chapter Embedded Pentium® Processor Family Developer's Manual (order number 273204). Note: input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active, asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. following pins become pins when Pentium processors with technology operating dual processing environment: ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#, M/IO#, D/C#, W/R#, SCYC, BE4#
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol Type Name Function When address mask asserted, processor emulates address wraparound Mbyte which occurs 8086 masking physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. A20M# internally masked processor when configured Dual processor. A31-A3 outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address strobe indicates that valid cycle currently being driven processor. address strobe (copy) functionally identical ADS#. response assertion address hold, Pentium® processor with MMXtechnology stops driving address lines (A31-A3) next clock. rest remains active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated processor. address parity check status asserted clocks after EADS# sampled active when processor detected parity error address during inquire cycles. APCHK# remains active clock each time parity error detected (including during dual processing private snooping). Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. When sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. byte enable pins used determine which bytes must written external memory which bytes were requested processor current cycle. byte enables driven same clock address lines (A31- A3). Additionally, lower 4-byte enables (BE3#-BE0#) used Pentium processor with technology APIC inputs sampled RESET. dual processing mode, BE4# used input during Flush cycles. frequency pins determine bus-to-core frequency ratio. BF1-BF0 sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF1-BF0 must change values while RESET active. Table Frequency Selections. backoff input used abort outstanding cycles that have completed. response BOFF#, processor floats pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. breakpoint pins (BP3-BP0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring.
A20M#
ADS# ADSC#
AHOLD
APCHK#
[APICEN] PICD1
BE7#-BE4# BE3#-BE0#
BF1-BF0
BOFF#
BP3-BP2 PM1-PM0/ BP1-BP0
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol Type Name Function burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. burst ready (copy) functionally identical BRDY#. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor latches address control signals machine check registers. When BUSCHK# active, processor vectors machine check exception. BUSCHK# assure that BUSCHK# always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. When BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor vectors exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst write back cycle (when write). When this driven inactive during read cycle, processor does cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external bus, requires levels. external timing parameters except TDI, TDO, TMS, TRST#, PICD0-PICD1 specified with respect rising edge CLK. This 3.3-V-tolerant-only Pentium processor with technology. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) PICCLK signal quality specification. recommended that begin toggling within after reaches proper operating level. This recommendation ensure long-term reliability device. type distinguishes Primary processor from Dual processor. single processor environment, when processor acting Primary processor dual processing system, CPUTYP should strapped VSS. Dual processor should have CPUTYP strapped VCC3. data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. dual/primary processor indication. Primary processor drives this when driving bus, otherwise drives this high. D/P# always driven. D/P# sampled current cycle with ADS# (like status pin). This defined only Primary processor. Dual processing supported system only both processors operating identical core frequencies. Within these restrictions, processors different steppings operate together system. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When processor driving data lines, they driven during T12, clocks that cycle. During reads, processor samples data when BRDY# returned.
BRDY#
BRDYC# BREQ
CACHE#
CPUTYP
D/C#
D/P#
D63-D0
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol Type Name Function These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back processor these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56, applies D7-D0. Dual processing enable output Dual processor input Primary processor. Dual processor drives DPEN# Primary processor RESET indicate that Primary processor should enable dual processor mode. DPEN# sampled system falling edge RESET determine dual-processor socket occupied. DPEN# multiplexed with PICD0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write, EWBE# sampled inactive, processor holds subsequent writes M-state lines data cache until write cycles have completed, which indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating-point error reporting. FERR# never driven active Dual processor. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicate completion write back invalidation. When FLUSH# sampled when RESET transitions from high low, threestate test mode entered. FLUSH# When Pentium processors with technology operating dual processing mode FLUSH# asserted, Dual processor performs flush first (without flush acknowledge cycle), then Primary processor performs flush followed flush acknowledge cycle. When FLUSH# signal asserted dual processing mode, must deasserted least clock prior BRDY# FLUSH Acknowledge cycle avoid arbitration problems. indication driven reflect outcome inquire cycle. When inquire cycle hits valid line processor data instruction cache, this asserted clocks after EADS# sampled asserted. When inquire cycle misses processor cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive Pentium processor with technology will resume driving bus. processor cycle pending, will driven clock cycle after HLDA deasserted.
DP7-DP0
[DPEN#] PICD0
EADS#
EWBE#
FERR#
HIT#
HITM#
HLDA
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol Type Name Function response hold request, processor floats most output input/output pins asserts HLDA after completing outstanding cycles. processor maintains this state until HOLD deasserted. HOLD recognized during LOCK cycles. processor recognizes HOLD during reset. internal error used indicate internal parity errors. When parity error occurs read from internal array, processor asserts IERR# clock then shuts down. This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor ignores pending unmasked numeric exception continues executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor executes instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor stops execution waits external interrupt. IGNNE# internally masked when processor configured Dual processor. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used instead RESET after power-up. When INIT sampled high when RESET transitions from high low, processor performs built-in self test prior start program execution. active maskable interrupt input indicates that external interrupt been generated. When EFLAGS register set, processor generates locked interrupt acknowledge cycles vectors interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated ensure that interrupt recognized. When local APIC enabled, this becomes LINT0. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle transformed into burst line fill cycle. When APIC enabled, this local interrupt When APIC disabled, this INTR. When APIC enabled, this local interrupt When APIC disabled, this NMI. lock indicates that current cycle locked. Pentium processor with technology does allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed deasserted least clock between back-to-back locked cycles.
HOLD
IERR#
IGNNE#
INIT
INTR/LINT0
KEN#
LINT0/INTR LINT1/NMI
LOCK#
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol M/IO# Type Name Function memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor issues ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. When local APIC enabled, this becomes LINT1. Private grant grant line that used when Pentium processors with technology configured dual processing mode, order perform private arbitration. PBGNT# should left unconnected only Pentium processor with technology exists system. Private request request line that used when Pentium processors with technology configured dual processing mode, order perform private arbitration. PBREQ# should left unconnected when only processor exists system. page cache disable reflects state CR3, Page Directory Entry, Page Table Entry. provides external cacheability indication page page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. When Pentium processors with technology operating dual processing mode, PCHK# driven three clocks after BRDY# returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. When this sampled active clock data parity error detected, processor latches address control signals cycle with parity error machine check registers. When PEN# sampled active machine check enable "1", processor vectors machine check exception before beginning next instruction. Private indication used when Pentium processors with technology configured dual processing mode, order maintain local cache coherency. PHIT# should left unconnected when only processor exists system. Private modified modified cache line indication used when Pentium processors with technology configured dual processing mode, order maintain local cache coherency. PHITM# should left unconnected only processor exists system. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input processor. PICCLK This 3.3-V-tolerant-only Pentium processor with technology. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) PICCLK signal quality specification. Programmable interrupt controller data lines Pentium processor with technology comprise data portion APIC 3-wire bus. They open-drain outputs that require external pull-up resistors. These signals multiplexed with DPEN# APICEN respectively.
NMI/LINT1
PBGNT#
PBREQ#
PCHK#
PEN#
PHIT#
PHITM#
PICD0/[DPEN#]- PICD1/[APICEN]
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol Type Name Function These pins function part performance monitoring feature. PM1/BP1- PM0/BP0 breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) more details. page write through reflects state CR3, page directory entry, page table entry. used provide external write back indication page-by-page basis. run/stop input provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) more details. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine three-state test mode checker mode will entered, Built-In Self-Test (BIST) will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock processor, thereby causing core consume less power. When processor recognizes STPCLK#, processor stops execution next instruction boundary, unless superseded higher priority interrupt, generates stop grant acknowledge cycle. When STPCLK# asserted, processor still responds interprocessor external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Pentium processor with technology power inputs. Pentium processor with technology power inputs. VCC2 detect used flexible motherboard implementations configure voltage output set-point appropriately VCC2 inputs processor.
PRDY
R/S#
RESET
SCYC
SMI#
SMIACT#
STPCLK#
TRST# VCC2 VCC3 VCC2DET#
Datasheet
Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol W/R# Type Name Function Pentium processor with technology ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. write back/write through input allows data cache line defined write back write through line-by-line basis. result, determines whether cache line initially state data cache.
WB/WT#
Core frequencies according Table Each Pentium processor with technology specified operate within single bus-to-core ratio specific minimum-tomaximum bus-frequency range (corresponding minimum-to-maximum core-frequency range). Operation other bus-to-core ratios outside specified operating frequency range supported advocated. example, Pentium processor with technology does operate beyond frequency only supports bus-to-core ratio; does support 1/3, 1/2, bus-to-core ratios. Table Frequency Selections
Bus/Core Ratio 1/2(1,2) Bus/Core Frequency (MHz) 66/200
Bus/Core Frequency (MHz) 33/100 N/A(2) N/A(2) 33/117
N/A(2) 66/233
NOTES: This default core ratio Pentium® processor with MMXtechnology. pins left floating, processor will configured core frequency ratio. Currently, there embedded products that support these fractions.
Datasheet
Pentium® Processor with MMXTechnology
8.1.4
Reference Tables
Table Output Pins
Name ADS# ADSC# APCHK# BE7#-BE4# BREQ CACHE#(1) D/P#
Active Level High High
When Floated Hold, BOFF# Hold, BOFF#
Hold, BOFF#
Hold, BOFF#
FERR# HIT# HITM# HLDA
IERR# LOCK# M/IO# D/C# W/R# PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC
Hold, BOFF# Hold, BOFF#
High High High High
Hold, BOFF# Hold, BOFF#
SMIACT# VCC2DET# NOTES:
states except Shift-DR Shift-IR
output input/output pins floated during three-state test mode (except IERR#). These signals when Pentium® processors with MMXtechnology operating dual processing mode. These signals undefined when processor configured Dual processor. internal pull-up resistor.
Datasheet
Pentium® Processor with MMXTechnology
Table Input Pins
Name A20M# AHOLD APICEN BOFF# BRDY# BRDYC# BUSCHK# CPUTYP EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR LINT1-LINT0 KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level High High High High High High High High High High High Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up First BRDY#/NA# Pull-up Pull-up BRDY# EADS# APICEN RESET First BRDY#/NA# State BRDY# Pull-down Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Synchronous Pull-up Pull-up Pull-up State T12, State T12, BRDY# Pull-up Pull-down Pull-up Internal Resistor Qualified
Undefined when processor configured Dual processor.
Datasheet
Pentium® Processor with MMXTechnology
Table Input/Output Pins
Name(1) A31-A3 BE3#-BE0# D63-D0 DP7-DP0 DPEN# PICD0 PICD1 Active Level When Floated Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# RESET Pull-up Pull-up Pull-down Pull-down(2) Internal Resistor
NOTES: output input/output pins floated during three-state test mode (except TDO, IERR# TDO). BE3#-BE0# have Pull-downs during RESET only.
Table Inter-processor Input/Output Pins
Name PHIT# PHITM# PBGNT# PBREQ# Active Level Internal Resistor Pull-up Pull-up Pull-up Pull-up
NOTE: proper inter-processor operation, system cannot load these signals.
Datasheet
Pentium® Processor with MMXTechnology
8.1.5
Grouping According Function
Table organizes pins with respect their function.
Table Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Dual Processing Private Control Interrupts Floating-Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Power Management Miscellaneous Dual Processing Debugging Voltage Detection RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD1-PICD0 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# CPUTYP, D/P# R/S#, PRDY VCC2DET# Pins
Datasheet
Pentium® Processor with MMXTechnology
Mechanical Specifications
Package summary information provided Table mechanical specifications Pentium processor with technology provided Table Figure
Table PPGA Package Information
Package Type Plastic Staggered Grid Array (PPGA) Total Pins Array Package Size 1.95" 1.95" 4.95 4.95
Figure PPGA Package Dimensions
Table PPGA Package Dimensions
Millimeters Symbol 1.52 3.05 2.54 0.40 49.43 45.59 23.44 2.29 17.56 23.04 3.30 Lead Count 0.060 0.120 0.100 2.72 1.83 1.00 0.51 49.63 45.85 23.95 2.79 0.016 1.946 1.795 0.923 0.090 0.692 0.907 0.130 Lead Count 3.33 2.23 Notes 0.107 0.072 0.039 0.020 1.954 1.805 0.943 0.110 0.131 0.088 Notes Inches
Datasheet
Pentium® Processor with MMXTechnology
Thermal Specifications
Pentium processor with technology specified proper operation when case temperature, TCASE, (TC) within range power dissipation specification Table provided designing thermal solutions operation sustained maximum level. This worst-case power device would dissipate system sustained period time. This number provided assist design thermal solution device.
Table Power Dissipation Requirements Thermal Design
Measured VCC2=2.8 VCC3=3.3 Parameter Active Power Stop Grant/Auto Halt Powerdown Power Stop Clock Power 0.03 Typical 7.9(3) 7.3(3) 17.0(4) 15.7(4) 2.61 2.41 Unit Watts Watts Watts Watts Watts Notes MHz, Note MHz, Note frequencies, Note
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device VCC2 running typical applications. This value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum active power dissipation. determined using worst case instruction with VCC2 VCC3 also takes into account thermal time constants package. Active Power (typ) average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. Active Power (max) maximum power dissipation under normal operating conditions nominal VCC2, worst-case temperature, while executing worst case power instruction mix. Active power (max) equivalent Thermal Design Power (max). Stop Grant/Auto Halt Power Down Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input.
Measuring Thermal Values
verify that proper maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (smaller than 0.150" diameter) should drilled through heatsink allow probing center package. Figure illustration measure minimize measurement errors, following approach:
36-gauge finer diameter type thermocouples. laboratory testing done
using thermocouple made Omega (part number 5TC-TTK-36-36).
Attach thermocouple bead junction center package surface using high
thermal conductivity cements. laboratory testing done using Omega Bond* (part number OB-100).
Attach thermocouple 90-degree angle shown Figure
Datasheet
Pentium® Processor with MMXTechnology
hole size should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heatsink base. contact
will affect thermocouple reading.
8.4.1
Thermal Equations
Pentium processor with technology, ambient temperature, (air temperature around processor), specified directly. only restriction that met. calculate values, following equations: Where: =Ambient case temperature (°C) Case-to-ambient thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Maximum power consumption (Watt)
Table lists values Pentium processor with technology passive heatsink. thermal resistance from package case. values shown these tables typical values. actual values depend actual thermal conductivity process attach. thermal resistance from package case ambient. values shown these tables typical values. actual values depend heatsink design, interface between heatsink package, flow system, thermal interactions between processor surrounding components through printed-circuit board ambient air. Figure graph data from Table Thermal data collection parameters:
Heatsinks omni-directional aluminum alloy Features were based standard extrusion practices given height size ranged from mils spacing ranged from mils Base thickness ranged from mils Heatsink attach 0.005" thermal grease Attach thickness 0.002" will improve performance approximately C/Watt
Datasheet
Pentium® Processor with MMXTechnology
Figure Technique Measuring PPGA Packages
Table Thermal Resistance PPGA Packages
Heat Sink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None (°C/Watt) 12.9 (°C/Watt) Laminar Airflow (linear ft/min) 12.2 11.2
Figure Thermal Resistance Heatsink Height, PPGA Packages
0.25 0.35 0.45 0.55 0.65
Flow Rate (LFM)
(°C/W)
Heatsink Height (inches)
Datasheet

Pentium Processor® with MMXTechnology Packaging Information Pinou

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