Pentium Processor® with MMXTechnology Electrical Specifications T
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Pentium® Processor with MMXTechnology
Pentium Processor® with MMXTechnology Electrical Specifications
This section describes electrical differences between Pentium processor with technology Pentium processor, specifications Pentium processor with technology.
Electrical Characteristics
When creating Pentium processor with technology design based existing Pentium processor design, there number electrical differences that require attention. following sections highlight electrical issues pertaining Pentium processor with technology power supplies, connection specifications buffer models. Note that possible design single motherboard that supports more than member Pentium processor family. Refer Pentium® Processor Flexible Motherboard Design Guidelines (order number 243187) more information specific implementation examples.
9.1.1
Power Supplies
main electrical difference between Pentium processor with technology Pentium processor operating voltage. Pentium processor with technology requires separate voltage inputs, VCC2 VCC3. VCC2 pins supply power Pentium processor with technology core, while VCC3 pins supply power processor pins. Pentium processor, other hand, requires single voltage supply pins. This single supply powers both core pins Pentium processor. connecting VCC2 pins together VCC3 pins together separate power islands, Pentium processor designs easily converted support Pentium processor with technology. order maintain compatibility with Pentium processor-based platforms, Pentium processor with technology supports standard 3.3-V specification VCC3 pins.
9.1.2
Power Supply Sequencing
There specific power sequence required powering powering down separate VCC2 VCC3 supplies Pentium processor with technology. recommended that VCC2 VCC3 supplies turned within second each other.
9.1.3
Connection Specifications
Connection specifications power ground inputs, 3.3-V inputs outputs, NC/INC unused inputs discussed following sections.
Datasheet
Pentium® Processor with MMXTechnology
9.1.3.1
Power Ground
clean on-chip power distribution, embedded Pentium processor with technology VCC3 (I/O power), VCC2 (core power) (ground) inputs. Power ground connections must made external pins Pentium processor with technology. circuit board, VCC3 pins must connected 3.3-V plane. VCC3 pins must connected 2.8-V plane. pins must connected plane.
9.1.3.2
VCC2 VCC3 Measurement Specification
values VCC2 VCC3 should measured bottom side processor pins using oscilloscope with bandwidth least (100 MS/s digital sampling rate). There should short isolation ground lead attached processor bottom side board. measurement should taken following VCC/VSS pairs: AN13/AM10, AN21/AM18, AN29/ AM26, AC37/Z36, U37/R36, L37/H36, A25/B28, A17/B20, A7/B10, G1/K2, S1/V2, AC1/Z2. One-half these pins VCC2 while others VCC3; operating ranges VCC2 VCC3 pins specified different voltages. Table specification. display should show continuous sampling voltage line, mV/div, ns/div with trigger point center point range. Slowly move trigger high ends specification, verify that excursions beyond these limits observed. There allowances crossing high limits voltage specification. more information measurement techniques, Voltage Guidelines Pentium® Processors with MMXTechnology (order number 243186).
9.1.3.3
Decoupling Recommendations
Liberal decoupling capacitance should placed near Pentium processor with technology. Pentium processor with technology, when driving large address data buses high frequencies, cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high-frequency electrical performance. Inductance reduced shortening circuit board traces between Pentium processor with technology decoupling capacitors much possible. These capacitors should evenly distributed around each component power plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Pentium processor with technology, power consumption transition from level power much higher level high power) very rapidly. typical example would entering exiting Stop Grant State. Another example would executing HALT instruction, causing Pentium processor with technology enter AutoHALT Power Down State, transitioning from HALT Normal State. these examples cause abrupt changes power being consumed Pentium processor with technology. Note that AutoHALT Power Down feature always enabled even when other power management features implemented. Bulk storage capacitors with Effective Series Resistance (ESR) 100- range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel.
Datasheet
Pentium® Processor with MMXTechnology
These capacitors should placed near Pentium processor with technology both VCC2 VCC3 plane ensure that supply voltage stays within specified limits during changes supply current during operation. Detailed decoupling recommendations provided Flexible Motherboard Design Guidelines (order number 243187). Note: Reducing available bulk capacitance could degrade long term system reliability.
9.1.3.4
3.3-V Inputs Outputs
inputs outputs Pentium processor with technology comply with 3.3-V JEDEC standard levels. Both inputs outputs also TTL-compatible, although inputs cannot tolerate voltage swings above VIN3 (max) specification. System support components which TTL-compatible inputs will interface Pentium processor with technology without extra logic. This because Pentium processor drives according specification (but beyond Pentium processor with technology inputs, voltage must exceed 3.3-V (max) specification. System support components consist 3.3-V devices open-collector devices. open-collector configuration, external resistor should biased VCC3. pins, including PICCLK Pentium processor with technology, V-tolerant-only. When 8259A interrupt controller used, example, system must provide level converters between 8259A Pentium processor with technology.
9.1.3.5
NC/INC Unused Inputs
Important: pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected (ground).
9.1.3.6
Private
When Pentium processors with technology operating dual processor mode, "private bus" exists arbitrate processor maintain local cache coherency. private consists pinout changes:
Five pins added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#. output pins become pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#,
HITM#, HLDA, SCYC, BE4#. pins given specifications valid delays setup times hold times. Simulate with these parameters their respective buffer models guarantee that proper timings met. specification gives input setup hold times signals that become pins. These setup hold times must only when dual processor present system.
Datasheet
Pentium® Processor with MMXTechnology
9.1.4
Buffer Models
structure buffer models Pentium processor with technology Pentium processor identical. Some values components have changed reflect minor manufacturing process package differences between processors. system should insignificant differences between behavior Pentium processor with technology Pentium processor. Simulation timings using Pentium processor with technology buffer models recommended ensure robust system designs. specific attention signal quality restrictions imposed 3.3-V buffers.
Absolute Maximum Ratings
Table provides stress ratings only. Functional operation Absolute Maximum Ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor with technology contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields.
Table Absolute Maximum Ratings
Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC2 VIN3 VCC3 Supply Voltage with respect VCC2 Supply Voltage with respect Only Buffer Input Voltage -0.5 -0.5 -0.5 VCC3 +0.5 (not exceed VCC3 max) Unit
Warning:
Stressing device beyond Absolute Maximum Ratings cause permanent damage. These stress ratings only. Operation beyond specifications recommended guaranteed extended exposure beyond specifications affect device reliability.
Datasheet
Pentium® Processor with MMXTechnology
Specifications
Tables through list specifications Pentium processor with technology.
Table TCASE Specifications
Symbol TCASE VCC2 VCC3 Parameter Case Temperature VCC2 Voltage VCC3 Voltage 3.135 Nom. Unit Range 3.57% Range -5%, +9.09% Notes
"VCC2 VCC3 Measurement Specification" page
Table Specifications
Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage -0.3 VCC3 +0.3 Unit Notes Level Level Level Level(4)
NOTES: Parameter measured nominal VCC3 which Parameter measured dual processing systems, load from second processor observed PCHK# signal. Based silicon characterization data, VOL3 PCHK# will remain less than even with load. PCHK# VOL3 will increase approximately with load (worst case system with system load). Parameter measured
Table Specifications
Measured VCC2=2.9 VCC3=3.6 Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current 6500 5700 Unit Notes
This value should used power supply design. determined using worst case instruction maximum VCC. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
Datasheet
Pentium® Processor with MMXTechnology
Table Input Output Characteristics
Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current -400 Unit Notes Guaranteed design Guaranteed design Guaranteed design Guaranteed design Guaranteed design Guaranteed design Guaranteed design VIL, VCC, Note VIL, VCC, Note Note Notes
NOTES: This parameter inputs/outputs without internal pull-up pull-down. This parameter inputs with internal pull-down. This parameter inputs with internal pull-up. This specification applies HITM# when driven input (e.g., JTAG mode).
Specifications
specifications consist output delays, input setup requirements input hold requirements. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced volts both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct Pentium processor with technology operation. Each valid delay specified load. system designer should buffer modeling account signal flight time delays. Each Pentium processor with technology specified operate within single bus-to-core ratio specific minimum maximum frequency range (corresponding minimum maximum core frequency range). Operation other bus-to-core ratios outside specified operating frequency range supported. example, Pentium processor with technology does operate beyond frequency only supports bus-to-core ratio; does support 1/3, 1/2, bus-to-core ratios. Table summarizes these specifications.
Datasheet
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay BE7#-BE0#, LOCK# Valid Delay ADS# Valid Delay ADSC#, D/C#, W/R#, SCYC, Valid Delay M/IO# Valid Delay A16-A3 Valid Delay A31-A17 Valid Delay ADS#, ADSC#, A31-A3, PWT, PCD, BE7#-BE0#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM1-PM0, BP3-BP0 Valid Delay PRDY Valid Delay D63-D0, DP7-DP0 Write Data Valid Delay D63-D0, DP3-DP0 Write Data Float Delay A31-A5 Setup Time A31-A5 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time 0.15 0.15 10.0 Parameter 33.33 15.0 66.6 30.0 ±250 Unit Figure Adjacent Clocks, Notes Note Note Notes Notes Notes
t10a t10b t11a t11b t16a t16b
10.0 10.0
NOTE: Table notes.
Datasheet
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol t18a t18b t24a t24b t25a t25b t42a Parameter KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDYC#, BUSCHK#) Hold Time, Async. 15.0 Unit Notes Power Notes RESET falling edge, Note RESET falling edge, Note Figure Notes Notes Notes Notes Notes Notes
t42b
NOTE: Table notes.
Datasheet
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol t42c t43a t43b t43c t43d Parameter Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. BF0, BF1, CPUTYP Setup Time BF0, BF1, CPUTYP Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 APIC Specifications t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j t80a PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD1-PICD0 Setup Time PICD1-PICD0 Hold Time PICD1-PICD0 Valid Delay (LtoH) PICD1-PICD0 Valid Delay (HtoL) PBREQ#, PBGNT#, PHIT# Flight Time 60.0 15.0 15.0 0.15 0.15 38.0 22.0 16.66 500.0 PICCLK PICCLK From PICCLK, Note From PICCLK, Note Notes 40.0 13.0 20.0 25.0 20.0 25.0 62.5 25.0 25.0 16.0 Unit Note Note Notes Notes Asynchronous, Note Notes Notes Notes Notes Notes Figure Notes RESET falling edge, Note RESET falling edge, Note RESET falling edge, Note RESET falling edge RESET falling edge
NOTE: Table notes.
Datasheet
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol t80b t83a t83b t83c t83d t83e t84a t84b t84c t84d Parameter PHITM# Flight Time A31-A5 Setup Time D/C#, W/R#, CACHE#, LOCK#, SCYC Setup Time ADS#, M/IO# Setup Time HIT#, HITM# Setup Time HLDA Setup Time CACHE#, HIT# Hold Time ADS#, D/C#, W/R#, M/IO#, A31-A5, HLDA, SCYC Hold Time LOCK# Hold Time HITM# Hold Time DPEN# Valid Time DPEN# Hold Time APIC (BE3#-BE0#) Setup Time APIC (BE3#-BE0#) Hold Time D/P# Valid Delay 10.0 Unit Figure Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes falling Edge RESET, Note From Falling Edge RESET, Note Primary Processor Only
NOTE: Table notes.
Datasheet
Pentium® Processor with MMXTechnology
Table Notes Table
NOTES: Notes general apply standard signals used with Pentium® processor family. Each valid delay specified load. system designer should buffer models account signal flight time delays. 100% tested. Guaranteed design/characterization. input test waveforms assumed transitions with V/ns rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK# PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions. V/ns input rise/fall time V/ns. V/ns input rise/fall time V/ns. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. 10.During debugging, boundary scan timings (t55 t58). This flight time specification, that includes both flight time clock skew. flight time time from where unloaded driver crosses (50% VCC), where receiver crosses level (50% VCC). Figure minimum flight time minus clock skew must greater than zero. 12.Setup time required guarantee recognition specific clock. Pentium® processor with MMXtechnology must meet this specification dual processor operation FLUSH# RESET signals. 13.Hold time required guarantee recognition specific clock. Pentium processor with technology must meet this specification dual processor operation FLUSH# RESET signals. 14.All timings referenced from 15.To guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. 16.This input driven asynchronously. However, when operating processors dual processing mode, FLUSH# RESET must asserted synchronously both processors. 17.When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT SMI# must deasserted (inactive) minimum clocks before being returned active. 18.Timings valid only when dual processor present. 19.Maximum time DPEN# valid from rising edge RESET. 20.Minimum time DPEN# valid after falling edge RESET. 21.The D/C#, M/IO#, W/R#, CACHE# A31-A5 signals sampled only that ADS# active. 22.In order override internal defaults guarantee that BF1-BF0 inputs remain stable while RESET active, these pins should strapped directly through pull-up/pull-down resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. Similarly, CPUTYP should also strapped directly through pull-up/pull-down resistor VCC3 ground. 23.RESET synchronous dual processing mode. signals which have setup hold time with respect falling rising edge RESET mode, should measured with respect first processor clock edge which RESET sampled either active inactive dual processing mode. 24.The PHIT# PHITM# signals operate core frequency. 25.These signals measured rising edge adjacent CLKs ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. internal clock generator requires constant frequency input within ±250 Therefore, input cannot changed dynamically. 26.In dual processing mode, timing replaced t83a. Timing required external snooping (e.g., address setup which EADS# sampled active) both uniprocessor dual processor modes. 27.BRDYC# BUSCHK# used reset configuration signals select buffer size. 28.This assumes external pull-up resistor lumped capacitive load. pull-up resistor must between capacitance must between product must between PICD1-PICD0 0.55
Datasheet
Pentium® Processor with MMXTechnology
Figure Clock Waveform
2.0V 0.8V T25, (Rise Time) T26, (Fall Time) T23, (High Time) T24, (Low Time) T22, (BLCK, TCK, PICCLK Period)
P6CB761a
1.5V
Figure Valid Delay Timings
1.5V max. Signal 1.5V VALID min.
t10, t11, t12, t60i, t60j, t80a,
Figure Float Delay Timings
Datasheet
Pentium® Processor with MMXTechnology
Figure Setup Hold Timings
Figure Reset Configuration Timings
Datasheet
Pentium® Processor with MMXTechnology
Figure Test Timings
Figure Test Reset Timings
Datasheet
Pentium® Processor with MMXTechnology
Figure Percent Measurement Flight Time
Datasheet
Pentium® Processor with MMXTechnology
Datasheet
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