This volume describes basic features operation embedded Pentium proces
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Architectural Features
This volume describes basic features operation embedded Pentium processors:
Embedded Pentium processors with maximum operating frequencies 100, 133,
Embedded Pentium processors with Voltage Reduction Technology with maximum
operating frequency
Embedded Pentium processors with MMXtechnology with maximum operating
frequencies
Low-power embedded Pentium processors with MMXtechnology with maximum operating
frequencies general terms "processor," "embedded Pentium processor," "embedded Pentium processor family" used throughout this manual refer embedded Pentium processor, embedded Pentium processor with Voltage Reduction Technology, embedded Pentium processor with technology, low-power embedded Pentium processor with technology together. Some features functions described using these terms, however, available each processor type. Refer datasheet each product determine whether specific feature offered. some instances, names "embedded Pentium processor 100/133/166 MHz)," "embedded Pentium processor with Voltage Reduction Technology," "embedded Pentium processor with technology," "low-power embedded Pentium processor with technology" used this manual distinguish between processors when specific differences exist. "Related Documents" page list datasheets other documents that describe operation Pentium processors.
15.1
Processor Features Overview
embedded Pentium processor supports features previous Intel® architecture processors provides significant enhancements, including following (refer datasheet specific list features supported each processor):
Superscalar architecture Dynamic branch prediction Pipelined Floating-Point Unit Improved instruction execution time Separate code data caches Writeback MESI protocol data cache 64-bit data cycle pipelining Address parity
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Architectural Features
Internal parity checking Functional redundancy checking lock-step operation Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Dual processing support Advanced power management features Fractional operation On-chip local APIC device
addition, embedded Pentium processor with technology offers following enhancements over embedded Pentium processor:
Support Intel technology Dual power supplies-separate VCC2 (core) VCC3 (I/O) voltage inputs Separate 16-Kbyte, 4-way set-associative code data caches, each with improved fully
associative TLBs
Pool four write buffers used both execution pipelines Enhanced branch prediction algorithm Fetch pipeline stage between Prefetch Instruction Decode
following features supported embedded Pentium processor, supported embedded Pentium processor with technology:
Functional redundancy checking lock-step operation Support Intel 82498/82493 82497/82492 cache chipset products Split line accesses code cache
following feature supported embedded Pentium processor with technology, supported low-power embedded Pentium processor with technology:
Dual processing support
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Architectural Features
15.2
Component Introduction
application instruction embedded Pentium processor family includes complete instruction existing Intel Architecture processors ensure backward compatibility, with extensions accommodate additional functionality embedded Pentium processor. application software written Intel386and Intel486microprocessors runs embedded Pentium processor without modification. on-chip Memory Management Unit (MMU) completely compatible with Intel386 Intel486 processors. embedded Pentium processor with technology adds instructions four data types accelerate performance multimedia communications software. technology based SIMD technique-Single Instruction, Multiple data-which enables increased performance wide variety multimedia communications applications. take advantage instructions, software modifications must made. When instructions used, hardware software modifications needed. instruction pipelines floating-point unit embedded Pentium processor capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. embedded Pentium processor with technology adds Fetch pipeline stage between Prefetch Instruction decode stages, which increases performance capability processor. embedded Pentium processor with technology doubles number write buffers available used dual pipelines. Branch prediction implemented embedded Pentium processor. support this, processor prefetch buffers, prefetch code linear fashion, that prefetches code according Branch Target Buffer (BTB) needed code almost always prefetched before needed execution. branch prediction algorithm been enhanced embedded Pentium processor with technology increased accuracy. embedded Pentium processor includes separate code data caches integrated chip meet performance goals. Each cache embedded Pentium processor with technology Kbytes size, four-way associative. caches embedded Pentium processor 100/133/166 MHz) each Kbytes two-way set-associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable writeback writethrough line-by-line basis follows MESI protocol. data cache tags triple ported support data transfers inquire cycle same clock. code cache inherently write protected cache. code cache tags embedded Pentium processor 100/133/166 MHz) also triple ported support snooping split-line accesses. embedded Pentium processor with technology does support split line accesses code cache. such, code cache tags dual ported. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware. embedded Pentium processor 64-bit data supports burst read burst writeback cycles. addition, cycle pipelining been added allow cycles progress simultaneously. Memory Management Unit contains optional extensions architecture that allow four-Mbyte page sizes.
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embedded Pentium processor added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. embedded Pentium processor features functional redundancy checking provide maximum error detection processor interface processor. When functional redundancy checking used, second processor, "checker" used execute lockstep with "master" processor. checker samples master's outputs, compares those values with values computes internally, asserts error signal when mismatch occurs. embedded Pentium processor with technology does support functional redundancy checking. more more functions integrated on-chip, complexity board-level testing increased. address this, embedded Pentium processor increased test debug capability implementing IEEE Boundary Scan (Standard 1149.1). System management mode (SMM) been implemented along with some extensions architecture. Enhancements Virtual 8086 mode have been made increase performance reducing number times necessary trap Virtual 8086 monitor. Figure 15-1 block diagram overview embedded Pentium processor with technology including instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instruction. separate code data caches shown. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units embedded Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit contains parallel decoders which decode issue next sequential instructions into execution pipeline. control contains microcode that controls sequence operations performed processor. control unit direct control over both pipelines. embedded Pentium processor contains pipelined floating-point unit that provides significant floating-point performance advantage over previous generations Intel architecturebased processors. embedded Pentium processor includes features support multi-processor systems, namely on-chip Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across processors), multiple subsystem support, 8259A compatibility, inter-processor interrupt support.
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Figure 15-1. Embedded Pentium® Processor Block Diagram
Control
Logic4
Branch Prefetch Target Buffer Address
Code Cache Kbytes1
1283
Instruction Pointer 64-Bit Data 32-Bit Address Unit Branch Verification Target Address
Prefetch Buffers Instruction Decode
Control
Control Unit
V-Pipeline Connection U-Pipeline Connection
Page Unit Address Address Generate Generate Pipeline) Pipeline)
Floating Point Unit
MMXTechnology Unit2
Control
Control Register File Divide Multiply
Integer Register File
64-Bit Data
Pipeline)
32-Bit Addr.
Pipeline)
Barrel Shifter
Data APIC5 Control
Data Cache Kbytes1
A6105-01
NOTES: Code Data caches each Kbytes size embedded Pentium® processor 100/133/166 MHz). Technology Unit present only embedded Pentium processor with MMXtechnology. internal instruction bits wide embedded Pentium processor. Dual processing present embedded Pentium processor with Voltage Reduction Technology low-power embedded Pentium processor with technology. APIC present embedded Pentium processor with Voltage Reduction Technology.
dual processor configuration allows embedded Pentium processors share single cache low-cost symmetric multi-processor system. processors appear system single embedded Pentium processor. Multiprocessor operating systems properly schedule computing tasks between processors. This scheduling tasks transparent software applications end-user. Logic built into processors support "glueless" interface easy system design. Through private bus, embedded Pentium processors arbitrate external maintain cache coherency. embedded Pentium processor also used conventional multi-processor system which cache dedicated each processor.
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Architectural Features
this document, order distinguish between embedded Pentium processors dual processing mode, processor referred Primary processor other Dual processor. Note that this different concept than that "master" "checker" processors described discussion functional redundancy. Dual processing supported system only when both processors operating identical core frequencies same type processor. Within these restrictions, processors different steppings operate together system. Chapter "Component Operation" more details about Dual processing. embedded Pentium processor produced Intel's advanced silicon technology. embedded Pentium processor also includes enhanced power management features. When clock embedded Pentium processor stopped, power dissipation virtually eliminated. operating voltages enhanced power management features make embedded Pentium processor good choice energy-efficient designs. embedded Pentium processor supports fractional operation. This allows internal processor core operate high frequencies, while communicating with external lower frequencies. datasheet bus-to-core frequency ratios supported specific member embedded Pentium processor family.
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