11.0 Low-power Embedded Pentium® Processor with MMXTechnology Pac

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11.0 Low-power Embedded Pentium® Processor with MMXTechnology Pac

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Low-Power Embedded Pentium® Processor with MMXTechnology
11.0
Low-power Embedded Pentium® Processor with MMXTechnology Packaging Information
Differences from Desktop Processors
following features have been eliminated low-power embedded Pentium processor with technology: Upgrade, Dual Processing (DP), Master/Checker functional redundancy. Table lists corresponding pins that exist Pentium processor with technology have been removed low-power embedded Pentium processor with technology.
11.1
Table Signals Removed from Low-Power Embedded Pentium® Processor with MMXTechnology
Signal ADSC# Function Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems.
BRDYC# CPUTYP D/P# FRCMC# PBGNT# PBREQ# PHIT# PHITM#
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Low-Power Embedded Pentium® Processor with MMXTechnology
11.2
PPGA Pinout Descriptions
text orientation side view drawings this section represents orientation mark actual packages. (Note that text shown this section actual text that will marked packages).
Figure PPGA Package Side View
VCC3 VCC3 VCC3 VCC3 INTR VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2
VCC2 FLUSH# W/R#
EADS#
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
VCC2DET BREQ
RESET
BE7#
BE5#
BE3#
BE1#
D/C# HLDA
ADS#
LOCK#
SMIACT# VCC2 PCHK# APCHK# PRDY VCC2 VCC2
R/S#
SMI# INIT
HOLD BUSCHK#
WB/WT# VCC2
VCC3 IGNNE# VCC3 VCC3
PEN#
BOFF# BOFF#
BRDYC# VCC2
VCC2
BRDY# KEN#
EWBE#
STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 TRST# VCC3
AHOLD#
Side View
INV#
CACHE# VCC2 VCC2
VCC3
MI/O#
PM1BP1
FERR# PM0BP0# VCC2 IERR# VCC2 VCC2 VCC2 VCC2
PICD1
VCC3 VCC3
PICD0
PICCLK
DP19
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
000260
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Low-Power Embedded Pentium® Processor with MMXTechnology
Figure PPGA Package Side View
BREQ
VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 INTR VCC3 VCC3 VCC3 VCC3
FLUSH# VCC2 W/R#
EADS#
VCC2DET
HITM# BUSCHK# BE0# HIT# A20M#
BE2#
BE4#
BE6#
SCYC
D/C# HLDA
BE1#
BE3#
BE5#
BE7#
RESET
ADS#
LOCK#
VCC2 SMIACT# VCC2 VCC2 PCHK# APCHK# PRDY
R/S#
BUSCHK# HOLD VCC2 WB/WT#
SMI# INIT
IGNNE#
BOFF#
PEN#
VCC3 VCC3
VCC2 BRDYC#
VCC2
BRDY# KEN#
EWBE#
AHOLD# INV#
STPCLK#
VCC2 CACHE# VCC2
Side View
VCC3
VCC3
MI/O#
VCC3 TRST#
VCC3 VCC3
PM1BP1
VCC2 PM0BP0# FERR# VCC2 VCC2 VCC2 VCC2 IERR#
VCC3 VCC3
VCC3 PICD0
PICD1
VCC3 VCC3 VCC3
PICCLK
DP19
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
000261
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Low-Power Embedded Pentium® Processor with MMXTechnology
Table Cross Reference Name (PPGA Package) (Sheet
Location Location Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 AK26 AL25 AK24 AL23 Data Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# AK08 AJ05 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# AJ01 AL07 AK04 AM04 HITM# HLDA HOLD IERR# IGNNE# INIT INTR/ LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# VCC2DET# W/R# AC05 AL03 AC35 AK20 AL17 AB34 AG03 AL01 AM06 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33 Location Location
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Table Cross Reference Name (PPGA Package) (Sheet
BRDY# Location FLUSH# HIT# Location AN07 AK06 PEN# PM0/BP0 APIC PICCLK PICD0 PICD1 [APICEN] Location WB/WT# Location AA05
Clock Control STPCLK# AK18
Table Connect, Power Supply Ground Cross Reference (PPGA Package)
VCC2 VCC3 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
Connect (NC) AA03 AC03 AD04 AE03 AE35 AL19 AM02 AN01 AN03 AN05 AN35
NOTE: Shaded pins differ functionally from Pentium® Processor with MMXTechnology pinout.
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Low-Power Embedded Pentium® Processor with MMXTechnology
11.3
HL-PBGA Pinout Descriptions
Figure HL-PBGA Package Side View
LOCK#
HOLD
BOFF# KEN# AHOLD M/IO# PM1/BP1 IERR# WB/WT# EWBE# PM0/BP0 VCC2 BRDY# VCC2 CACHE# FERR#
APCHK# PRDY
SMIACT#
VCC3
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
HLDA
BREQ PCHK# VCC2 VCC3 VCC2 VCC3 VCC3
VCC2 VCC3
VCC2 VCC3 VCC2
VCC2 VCC3 VCC3
VCC2 VCC2
VCC3 VCC2 VCC3 VCC2
VCC3 VCC2
D/C#
EADS#
W/R#
ADS#
FLUSH# HIT# HITM# VCC3 BE0# BE2# BUSCHK# BE1# A20M# VCC3 VCC3 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3
BE3# BE5#
BE4# BE7#
BE6#
View
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
SCYC RESET VCC2
VCC3 VCC3
VCC2 VCC2 VCC2
VCC2
VCC3 VCC2 VCC3
VCC3 VCC2
VCC3 VCC3
VCC3
VCC2
VCC2
VCC2 VCC2
VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC3 VCC2
PICD[0]
SMI# NMI/LINT1
INIT
BF[0] BF[2]
VCC2 VCC2
PICCLK
IGNNE# PEN# BF[1] STPCLK# INTR/LINT0
TRST#
PICD[1]
A4694-01
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Low-Power Embedded Pentium® Processor with MMXTechnology
Figure HL-PBGA Package Side View
IERR#
PM1/BP1 M/IO# EWBE# AHOLD KEN# BOFF# HOLD PM0/BP0 WB/WT# CACHE# BRDY# VCC2 VCC2 VCC2 VCC2 SMIACT#
VCC2
FERR#
PRDY APCHK# BREQ VCC2
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
VCC2 VCC3
PCHK# VCC3 VCC2 VCC3 VCC3
HLDA
VCC3 VCC2
VCC3 VCC2 VCC3 VCC2 VCC2 VCC3 VCC3
VCC3 VCC2
LOCK#
D/C#
EADS#
ADS#
W/R#
VCC3 HITM# HIT# FLUSH# VCC3 VCC3 BE0# BUSCHK# BE2#
A20M# BE1#
BE4# BE7#
BE3# BE5#
Bottom View
VCC3
BE6#
VCC2 VCC2 RESET SCYC VCC3 VCC2 VCC3 VCC3
VCC2 VCC3 VCC3
VCC3 VCC2 VCC2 VCC2
VCC2
VCC3
VCC2
VCC2 VCC2 VCC2 VCC2
VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC3 VCC3
VCC3 VCC2 VCC3
VCC2 VCC3 VCC3
VCC2
PICD[0]
PICCLK
VCC2
BF[2]
BF[0]
INIT
SMI#
NMI/LINT1
PICD[1]
TRST#
STPCLK# BF[1] PEN# IGNNE# INTR/LINT0
A4695-01
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Table Cross Reference Name (HL-PBGA Package) (Sheet
Location Location Address Data AC24 AC25 AB24 AB25 AA24 AA25 Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/ LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# AF14 AE14 AF13 AE12 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT# AF12 AE13 AE22 AE21 AF21 AF20 AF19 AF11 AE11 AF10 AE10 Location Location
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Table Cross Reference Name (HL-PBGA Package) (Sheet
BRDY# Location FLUSH# HIT# Location PEN# PM0/BP0 APIC PICCLK AE23 PICD0 AD23 PICD1 [APICEN] AF22 Location AF15 Location
Clock Control STPCLK# AE15 AF17 AF16 AE16
Table Connect, Power Supply Ground Cross Reference (HL-PBGA Package)
VCC2 VCC3 AA23 AD10 AD11 AD13 AD14 AD15 AD16 AD17 AD18 AD20 AD21 AD22 AD24 AE19 AE20 AC10 AC11 AC17 AC22 AB23 AC13 AC14 AC15 AC16 AC18 AC19 AC20 AC21 AC23 AD19 AE17 AE18
Connect (NC) AF18 Internal Connect (INC) AA26 AB26 AC12 AC26 AD12 AD25 AD26 AE24 AE25 AE26 AF23 AF24 AF25 AF26
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11.4
Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected (VSS). Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
11.5
Quick Reference
This section gives brief functional description each pin. detailed description, Hardware Interface chapter Embedded Pentium® Processor Family Developer's Manual. Note: input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. pins classified Input Output based their function Master Mode. Error Detection chapter Embedded Pentium® Processor Family Developer's Manual (order number 273204) further information.
Table Quick Reference (Sheet
Symbol Type Name Function When address mask asserted, Pentium® processor with MMXtechnology emulates address wraparound Mbyte, which occurs 8086. When A20M# asserted, processor masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven processor. response assertion address hold, processor will stop driving address lines (A31-A3) next clock. rest will remain active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-3).
A20M#
A31-A3
ADS#
AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
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Table Quick Reference (Sheet
Symbol Type Name Function Frequency pins determine bus-to-core frequency ratio. [2:0] sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF[2:0] must change values while RESET active. Table Frequency Selection. BF2-BF0 order override internal defaults guarantee that BF[2:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. During power RESET should asserted prior ramped simultaneously with core voltage supply processor. backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. BUSCHK# assure that BUSCHK# will always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor will vector exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external requires levels. external timing parameters except TDI, TDO, TMS, TRST# PICD0-1 specified with respect rising edge CLK. This V-tolerant-only low-power embedded Pentium processor with technology. recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device.
BOFF#
[APICEN] PICD1
BP3-BP2 PM/BP1-BP0
BRDY#
BREQ
CACHE#
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Low-Power Embedded Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol D/C# Type Name Function data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back Pentium processor with voltage reduction technology these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56; applies D7-D0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write EWBE# sampled inactive, processor will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using MS-DOS type floating-point error reporting. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicating completion writeback invalidation. FLUSH# sampled when RESET transitions from high low, three-state test mode entered. indication driven reflect outcome inquire cycle. inquire cycle hits valid line either data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive processor will resume driving bus. processor cycle pending, will driven same clock that HLDA de-asserted. response hold request, processor will float most output input/output pins assert HLDA after completing outstanding cycles. processor will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. processor will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, processor will assert IERR# clock then shutdown.
D63-D0
DP7-DP0
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IERR#
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Low-Power Embedded Pentium® Processor with MMXTechnology
Table Quick Reference (Sheet
Symbol Type Name Function This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will stop execution wait external interrupt. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, processor will perform built-in self test prior start program execution. active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, processor will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. lock indicates that current cycle locked. processor will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor will issue ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. page cache disable reflects state CR3; Page Directory Entry Page Table Entry. purpose provide external cacheability indication page-by-page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned.
IGNNE#
INIT
INTR
KEN#
LOCK#
M/IO#
PCHK#
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Table Quick Reference (Sheet
Symbol Type Name Function parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock, data parity error detected. processor will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", processor will vector machine check exception before beginning next instruction. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input Pentium processor with technology. Programmable interrupt controller data lines Pentium processor with technology comprise data portion APIC 3-wire bus. They opendrain outputs that require external pull-up resistor. These signals multiplexed with APICEN. These pins function part performance monitoring feature. PM/BP[1:0] breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output indicates that processor stopped normal execution response R/S# going active Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis. run/stop input provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (Order Number 273204) more details. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine three-state test mode will entered BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor with voltage reduction technology thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, processor will still respond external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state.
PEN#
PICCLK PICD0- PICD1 [APICEN]
PRDY
R/S#
RESET
SCYC
SMI#
SMIACT#
STPCLK#
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Table Quick Reference (Sheet
Symbol Type Name Function test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Differentiate between Pentium Processor with technology lowpower embedded Pentium processor with technology. This Internal Connect (INC) low-power embedded Pentium processor with technology. This defined HL-PBGA package. These pins power inputs core: input 166/266 PPGA; HL-PBGA; HL-PBGA. These pins power inputs I/O. These pins ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
TRST#
VCC2DET#
VCC2 VCC3 W/R#
WB/WT#
11.6
Fraction (BF) Selection
Each low-power embedded Pentium processor with technology must externally configured with BF2-BF0 pins operate specified fraction mode. Operation specification supported. example, low-power embedded Pentium processor with technology supports only fraction mode mode. configuration pins provided select allowable bus/core ratios 1/4. low-power embedded Pentium processor with technology multiplies input achieve higher internal core frequencies. internal clock generator requires constant frequency input within ±250 therefore, input cannot changed dynamically. external frequency during power-up Reset through pin. low-power embedded Pentium processor with technology samples BF0, pins falling edge RESET determine which bus/core ratio use. Table summarizes operation pins low-power embedded Pentium processor with technology. Note: pins must meet setup time falling edge RESET must change value while RESET active. Once frequency selected, changed with warm reset. Changing this speed ratio requires "power RESET pulse initialization.
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Low-Power Embedded Pentium® Processor with MMXTechnology
Table Frequency Selection
Bus/Core Ratio Bus/Core Frequency (MHz) 66/166 66/266
NOTE: other BF2-BF0 settings reserved low-power embedded Pentium processor with technology.
11.7
CPUID Instruction
CPUID instruction allows software determine type features processor which executing. When executing CPUID, low-power embedded Pentium processor with technology behaves like Pentium processor Pentium processor with technology follows:
value `0', then 12-byte ASCII string "Genuine Intel" (little endian)
returned EBX, ECX. Also, returned EAX.
value `1', then processor version returned processor
capabilities returned EDX. values low-power embedded Pentium processor with technology given below.
value neither `1', low-power embedded Pentium processor with
technology writes registers. following values defined CPUID instruction executed with `1'. processor version assignments given Figure assignments shown Figure Figure Assignments CPUID
(Reserved)
Type Family
Model Stepping
000250
Figure Assignments CPUID
Rsvd
000251
Reserved
Reserved
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Low-Power Embedded Pentium® Processor with MMXTechnology
type field low-power embedded Pentium processor with technology same Pentium processor with technology (type 00H). family field same other Pentium processors (family 5H). However, model field different: Pentium processor model number Pentium processor with technology model number low-power embedded Pentium processor with technology model number stepping field indicates revision number model. stepping A-step lowpower embedded Pentium processor with technology Stepping will documented low-power embedded Pentium processor with technology stepping information. After masking reserve bits, low-power embedded Pentium processor with technology-based products will value 0x008003BF (assuming APIC enabled boot), 0x008001BF (when APIC disabled, using APICEN boot pin) upon completion CPUID instruction. Table Assignment Definitions CPUID
10-11 15-22 24-31 Value Comments FPU: Floating-point Unit on-chip VME: Virtual-8086 Mode Enhancements Debugging Extensions PSE: Page Size Extension TSC: Time Stamp Counter Pentium® Processor PAE: Physical Address Extension MCE: Machine Check Exception CX8: CMPXCHG8B Instruction APIC: APIC on-chip Reserved write these bits rely their values MTRR: Memory Type Range Registers PGE: Page Global Enable MCA: Machine Check Architecture Reserved write these bits rely their values Intel Architecture with MMXtechnology supported Reserved write these bits rely their values
Indicates that APIC present hardware enabled (software disabling does affect this bit).
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11.8
Boundary Scan Chain List
boundary scan chain list low-power embedded Pentium processor with technology different than Pentium processor with technology removal some pins. boundary scan register low-power embedded Pentium processor with technology contains cell each pin. Following order low-power embedded Pentium processor with technology boundary scan register (left right, bottom): disapsba, PICD1, PICD0, Reserved, PICCLK, DP0, D10, D11, D12, D13, D14, D15, DP1, D16, D17, D18, D19, D20, D21, D22, D23, DP2, D24, D25, D26, D27, D28, D29, D30, D31, DP3, D32, D33, D34, D35, D36, D37, D38, D39, DP4, D40, D41, D42, D43, D44, D45, D46, diswr D47, DP5, D48, D49, D50, D51, D52, D53, D54, D55, DP6, D56, D57, D58, D59, D60, D61, D62, D63, DP7, IERR#, FERR#, PM0BP0, PM1BP1, BP2, BP3, MIO#, CACHE#, EWBE#, INV, AHOLD, KEN#, BRDYC#, BRDY#, BOFF#, NA#, WBWT#, HOLD, disbus, disbusl, dismisc, dismisca, SMIACT#, PRDY, PCHK#, APCHK#, BREQ, HLDA, LOCK#, PCD, PWT, DC#, EADS#, ADS#, HITM#, HIT#, WR#, BUSCHK#, FLUSH#, A20M#, BE0#, BE1#, BE2#, BE3#, BE4#, BE5#, BE6#, BE7#, SCYC, CLK, RESET, disabus A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A31, A30, A29, A28, A27, A26, A25, A24, A23, A22, A21, NMI, RS#, INTR, SMI#, IGNNE#, INIT, PEN#, Reserved, BF0, BF1, BF2, STPCLK#, Reserved, Reserved, Reserved, Reserved "Reserved" includes connect "NC" signals low-power embedded Pentium processor with technology. cells marked with dagger control cells that used select direction bidirectional pins three-state output pins. loaded into control cell, associated pin(s) three-stated selected input. following lists control cells their corresponding pins: Disabus: Disbus: Disbusl: Dismisc: Dismisca: Diswr: Disapsba: A31-A3, BE7#-BE0#, CACHE#, SCYC, M/IO#, D/C#, W/R#, PWT, ADS#, LOCK#, ADSC# APCHK#, PCHK#, PRDY, BP3, BP2, PM1/BP1, PM0/BP0, FERR#, SMIACT#, BREQ, HLDA, HIT#, HITM# IERR# D63-D0, DP7-DP0 PICD1-PICD0
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Low-Power Embedded Pentium® Processor with MMXTechnology
11.9
Reference Tables
Table Output Pins
Name ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM#(2) HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# VCC2DET#(3) Active Level High High High High High High states except Shift-DR Shift-IR Differentiates between Pentium® processor with MMXtechnology low-power embedded Pentium processor with technology Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated
NOTE: output input/output pins floated during three-state test mode (except TDO). HITM# internal pull-up resistor. This HL-PBGA pinout.
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Table Input Pins
Name A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Pullup Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Pullup Pullup State T2,T12,T2P BRDY# Pulldown Pullup Pulldown Internal Resistor Qualified
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Table Input/Output Pins
Name A31-A3 BE3#-BE0# D63-D0 DP7-DP0 PICD0 PICD1[APICEN] Active Level When Floated(1) Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown(2) Internal Resistor
NOTE: output input/output pins floated during three-state test mode (except TDO). BE3#-BE0# have pulldowns during RESET only.
11.10
Grouping According Function
Table Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating-point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Debugging RESET, INIT, BF[2:0] A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD0-PICD1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# R/S#, PRDY Pins
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Low-Power Embedded Pentium® Processor with MMXTechnology
11.11
Mechanical Specifications
mechanical terms, low-power embedded Pentium processor with technology 296-lead Plastic Staggered Grid Array (PPGA) completely identical Pentium processor with technology PPGA package. pins arranged 37x37 matrix package dimensions 1.95" 1.95" (4.95 4.95 cm). Package summary information PPGA device provided Table Figure shows package dimensions. HL-PBGA version low-power embedded Pentium processor with technology package type Pentium processor family. Package summary information HLPBGA device provided Table Figure shows package dimensions.
11.11.1
PPGA Package Mechanical Diagrams
Figure PPGA Package Dimensions
Seating Plane
Solder Resist Chip Capacitor
1.65 (Ref)
2.29 1.52 Chamfer (Index Corner)
Heat Slug
measurements
A5771-01
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Table PPGA Package Dimensions
Millimeters Symbol 1.52 0.40 49.43 45.59 23.44 2.29 3.05 2.54 0.060 2.72 1.83 1.00 Nominal 0.51 49.63 45.85 23.95 2.79 3.30 0.016 1.946 1.795 0.923 0.090 0.120 0.100 3.33 2.23 0.107 0.072 0.039 Nominal 0.020 1.954 1.805 0.943 0.110 0.130 0.131 0.088 Inches
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Low-Power Embedded Pentium® Processor with MMXTechnology
11.11.2
HL-PBGA Package Mechanical Diagrams
Figure shows ceramic HL-PBGA package. dimensions listed Table
Figure HL-PBGA Package Dimensions
Corner Corner
I.D. Dia. View
Bottom View
Side View
Seating Plane
Note: Dimensions Millimeters
A5830-01
Table HL-PBGA Package Dimensions
Millimeters Symbol
1.67 0.70 0.90 0.97 35.10 35.10 1.27 1.63
1.41 0.56 0.60 0.85 34.90 34.90
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Low-Power Embedded Pentium® Processor with MMXTechnology
11.12
Thermal Specifications
low-power embedded Pentium processor with technology specified proper operation when case temperature, TCASE (TC), within specified range PPGA package, HL-PBGA package.
11.12.1
Measuring Thermal Values
verify that proper maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (smaller than 0.150" diameter) should drilled through heatsink allow probing center package. Figure illustration measure minimize measurement errors, recommended following approach:
36-gauge finer diameter type thermocouples. laboratory testing done
using thermocouple made Omega* (part number 5TC-TTK-36-36).
Attach thermocouple bead junction center package surface using high
thermal conductivity cements. laboratory testing done using Omega Bond (part number OB-101).
thermocouple should attached 90-degree angle shown Figure hole size should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heatsink base. contact
will affect thermocouple reading.
11.12.2
Thermal Equations Data
low-power embedded Pentium processor with technology, ambient temperature, (air temperature around processor), specified directly. only restriction that met. equation used calculate
Where: Ambient case temperature (°C) Case-to-ambient thermal resistance (°C/Watt) Maximum power consumption (Watt)
thermal resistance from package case. values shown Tables typical values. actual values depend actual thermal conductivity process attach. thermal resistance from package case ambient. values shown these tables typical values. actual values depend heatsink design, interface between heatsink package, airflow system, thermal interactions between processor surrounding components through ambient.
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Figure Technique Measuring
000262
11.12.3
Airflow Calculations Maximum Typical Power
Below example determining airflow required during maximum power consumption low-power embedded Pentium processor with technology assuming ambient temperature (HL-PBGA) PHL-PBGA (HL-PBGA, without heat sink) 10.98 °C/W Figure indicates that this example would require about without heat sink, about with heat sink vertical orientation. Below example determining airflow required during typical power consumption low-power embedded Pentium processor with technology assuming ambient temperature (HL-PBGA) PHL-PBGA (HL-PBGA, without heat sink) 15.52 °C/W Figure indicates that this example would require about without heat sink. heat sink necessary typical power ambient conditions.
11.12.4
PPGA Package Thermal Resistance Information
Table lists values low-power embedded Pentium processor with technology PPGA package with passive heatsinks.
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Table Thermal Resistances PPGA Packages
Heatsink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None (°C/watt) 12.9 (°C/watt) Laminar Airflow (linear ft/min) 12.2 11.2
NOTES: Heatsinks omni-directional aluminum alloy. Features were based standard extrusion practices given height: size ranged from mils; spacing ranged from mils; base thickness ranged from mils. Heatsink attach 0.005" thermal grease. Attach thickness 0.002" will improve performance approximately watt.
Figure Thermal Resistance Heatsink Height, PPGA Packages
(°C/watt) Airflow Rate (LFM)
Heatsink Height (inches)
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11.12.5
HL-PBGA Package Thermal Resistance Information
Table lists values low-power embedded Pentium processor with technology HL-PBGA package. thermal data collection conditions were:
bidirectional anodized aluminum alloy heat sink used. Heat sink height 7mm. horizontal orientation component mounted flush with motherboard. vertical orientation component mounted add-in card perpendicular motherboard.
Table Thermal Resistances HL-PBGA Packages
Heatsink/ Orientation Heat Sink Horizontal Vertical (°C/watt) 0.76 0.76 0.76 (°C/watt) Laminar Airflow (linear ft/min) 15.66 12.09 11.33 12.33 8.57 8.34 10.3 6.52 6.38 8.85 4.82 4.69 7.89 4.06 3.95
Figure Thermal Resistance Airflow HL-PBGA Package
Airflow (LFM) Horizontal Heat Sink Vertical Heat Sink Heat Sink
(°C/W)
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11.0 Low-power Embedded Pentium® Processor with MMXTechnology Pac

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