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PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Optimized 32-bit applications running advanced 32-bit operating systems Single Edge Contact (S.E.C.) cartridge packaging technology; S.E.C. cartridge delivers high performance with improved handling protection socketability Integrated high performance instruction data, nonblocking, level cache Available with integrated unified, nonblocking, level cache Enables systems which scaleable processors physical memory Error-correcting code System data
Available MHz, MHz, MHz, core frequencies Binary compatible with applications running previous members Intel microprocessor line Dynamic Execution micro architecture Dual Independent architecture: Separate dedicated external System dedicated internal high-speed cache Intel's highest performance processor combines power Pentium processor with capabilities MMXtechnology Power Management capabilities System Management mode Multiple low-power states
Intel Pentium® processor designed high-performance desktops, workstations mainstream servers, binary compatible with previous Intel Architecture processors. Pentium processor provides best performance available applications running advanced operating systems such Windows* Windows UNIX*. This achieved integrating best attributes Intel's processors dynamic execution performance Pentium processor plus capabilities MMXtechnology bringing level performance system buyers. Pentium processor scaleable processors multiprocessor system extends power Pentium processor with performance headroom business media, communication Internet capabilities. Systems based Pentium processors also include latest features simplify system management lower cost ownership large small business environments.
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel. INTEL CORPORATION 1995 January 1998 Order Number: 243335-003
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request.Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained from calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation 1996, 1997. Third-party brands names property their respective owners.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
CONTENTS
PAGE PAGE 3.0. SYSTEM SIGNAL SIMULATIONS. 3.1. System Clock (BCLK) Signal Quality Specifications. 3.2. GTL+ Signal Quality Specifications. 3.3. Non-GTL+ Signal Quality Specifications. 3.3.1. OVERSHOOT/UNDERSHOOT GUIDELINES. 3.3.2. RINGBACK SPECIFICATION 3.3.3. SETTLING LIMIT GUIDELINE. 4.0. THERMAL SPECIFICATIONS DESIGN CONSIDERATIONS. 4.1. Thermal Specifications. 4.2. Pentium® Processor Thermal Analysis 4.2.1. THERMAL SOLUTION PERFORMANCE. 4.2.2. MEASUREMENTS THERMAL SPECIFICATIONS. 4.2.2.1. Thermal Plate Temperature Measurement 4.2.2.2. Cover Temperature Measurement 4.3. Thermal Solution Attach Methods 4.3.1. HEATSINK CLIP ATTACH 4.3.2. RIVSCREW* ATTACH. 5.0. S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS 5.1. S.E.C. Cartridge Materials Information 5.2. Processor Edge Finger Signal Listing. 6.0. BOXED PROCESSOR SPECIFICATIONS 6.1. Introduction. 6.2. Mechanical Specifications. 6.2.1. BOXED PROCESSOR FAN/HEATSINK DIMENSIONS. 6.2.2. BOXED PROCESSOR FAN/HEATSINK WEIGHT. 6.2.3. BOXED PROCESSOR RETENTION MECHANISM FAN/HEATSINK SUPPORT 6.3. Boxed Processor Requirements 6.3.1. FAN/HEATSINK POWER SUPPLY.
1.0. INTRODUCTION 1.1. Terminology. 1.1.1. S.E.C. CARTRIDGE TERMINOLOGY 1.2. References. 2.0. ELECTRICAL SPECIFICATIONS 2.1. Pentium® Processor System VREF 2.2. Clock Control Power States 2.2.1. NORMAL STATE STATE 2.2.2. AUTO HALT POWER DOWN STATE STATE 2.2.3. STOP-GRANT STATE STATE 2.2.4. HALT/GRANT SNOOP STATE STATE 2.2.5. SLEEP STATE STATE 2.2.6. DEEP SLEEP STATE STATE 2.2.7. CLOCK CONTROL POWER MODES. 2.3. Power Ground Pins. 2.4. Decoupling Guidelines 2.4.1. SYSTEM GTL+ DECOUPLING 2.5. Pentium® Processor System Clock Processor Clocking. 2.5.1. MIXING PROCESSORS DIFFERENT FREQUENCIES. 2.6. Voltage Identification 2.7. Pentium® Processor System Unused Pins 2.8. Pentium® Processor System Signal Groups 2.8.1. ASYNCHRONOUS SYNCHRONOUS SYSTEM SIGNALS 2.9. Test Access Port (TAP) Connection. 2.10. Maximum Ratings 2.11. Processor Specifications 2.12. GTL+ System Specifications 2.13. Pentium® Processor System Specifications.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
6.4. Thermal Specifications. 6.4.1. BOXED PROCESSOR COOLING REQUIREMENTS 7.0. ADVANCED FEATURES. ALPHABETICAL SIGNALS REFERENCE A.1.1 A[35:0]# (I/O) A.1.2 A20M# A.1.3 ADS# (I/O) A.1.4 AERR# (I/O) A.1.5 AP[1:0]# (I/O). A.1.6 BCLK A.1.7 BERR# (I/O) A.1.8 BINIT# (I/O) A.1.9 BNR# (I/O). A.1.10 BP[3:2]# (I/O). A.1.11 BPM[1:0]# (I/O). A.1.12 BPRI# A.1.13 BR0# (I/O), BR1# A.1.14 BSEL# (I/O) A.1.15 D[63:0]# (I/O) A.1.16 DBSY# (I/O). A.1.17 DEFER# A.1.18 DEP[7:0]# (I/O) A.1.19 DRDY# (I/O) A.1.20 EMI. A.1.21 FERR# (O). A.1.22 FLUSH# (I). A.1.23 FRCERR (I/O) A.1.24 HIT# (I/O), HITM# (I/O). A.1.25 IERR# (O). A.1.26 IGNNE# (I). A.1.27 INIT# (I). A.1.28 LINT[1:0] (I). A.1.29 LOCK# (I/O). A.1.30 PICCLK A.1.31 PICD[1:0] (I/O). A.1.32 PM[1:0]# A.1.33 PRDY# A.1.34 PREQ# A.1.35 PWRGOOD (I). A.1.36 REQ[4:0]# (I/O). FIGURES
A.1.37 RESET# A.1.38 (I/O). A.1.39 RS[2:0]# (I). A.1.40 RSP# A.1.41 SLOTOCC# A.1.42 SLP# (I). A.1.43 SMI# A.1.44 STPCLK# A.1.454 A.1.46 (I). A.1.47 A.1.48 TESTHI (I). A.1.49 THERMTRIP# A.1.50 A.1.51 TRDY# (I). A.1.52 TRST# A.1.53 VID[4:0] (O). SIGNAL SUMMARIES.
Figure Second Level (L2) Cache Implementations. Figure GTL+ Topology. Figure Stop Clock State Machine. Figure Timing Diagram System Multiplier Signals. Figure Example Schematic System Multiplier Sharing Figure BCLK Core Logic Offset Figure BCLK, TCK, PICCLK Generic Clock Wave Form Figure System Valid Delay Timings. Figure System Setup Hold Timings Figure Mode BCLK PICCLK Timing Figure System Reset Configuration Timings Figure Power-On Reset Configuration Timings Figure Test Timings (TAP Connection). Figure Test Reset Timings Figure BCLK, TCK, PICCLK Generic Clock Wave form Processor Edge Fingers
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Figure Substrate S.E.C. Cartridge Substrate Detail Figure Conceptual Boxed Pentium® Processor Retention Mechanism. Figure Side View Space Requirements Boxed Processor (fan heatsink supports shown) Figure Front View Space Requirements Boxed Processor Figure View Space Requirements Boxed Processor Figure Heatsink Support Hole Locations Sizes Figure Side View Space Requirements Boxed Processor Fan/Heatsink Supports. Figure View Space Requirements Boxed Processor Fan/Heatsink Supports. Figure Boxed Processor Fan/Heatsink Power Cable Connector Description. Figure Recommended Motherboard Power Header Placement Relative Power Connector Slot Figure PWRGOOD Relationship Power-On.
Figure High GTL+ Receiver Ringback Tolerance. Figure Non-GTL+ Overshoot/Undershoot Ringback. Figure Processor S.E.C. Cartridge Thermal Plate. Figure Processor Thermal Plate Temperature Measurement Location Figure Technique Measuring TPLATE with Angle Attachment
Figure Technique Measuring TPLATE with Angle Attachment Figure Guideline Locations Cover Temperature (TCOVER) Thermocouple Placement. Figure Processor with Example Profile Heatsink Attached using Spring Clips. Figure Processor with Example Full Height Heatsink Attached using Spring Clips. Figure Heatsink Recommendations Guidelines with Rivscrews* Figure Heatsink Rivscrew* Thermal Plate Recommendations Guidelines. Figure General Rivscrew* Heatsink Mechanical Recommendations Figure Heatsink Attachment Mechanism Design Space Figure S.E.C. Cartridge Thermal Plate Cover Side Views Figure S.E.C. Cartridge Overall Cartridge Dimensions Figure S.E.C. Cartridge Thermal Plate Side View Dimensions. Figure S.E.C. Cartridge Thermal Plate Flatness Dimensions Figure S.E.C. Cartridge Latch Details. Figure S.E.C. Cartridge Latch Arm, Thermal Plate Lug, Cover Dimensions Figure S.E.C. Cartridge Mark Locations Figure S.E.C. Cartridge Bottom Side View Figure S.E.C. Cartridge Substrate Dimensions Figure S.E.C. Cartridge Substrate Dimensions, Cover Side View
TABLES Table Core Frequency System Multiplier Configuration Table Voltage Identification Definition Table Recommended Pull-Up Resistor Values (Approximate) CMOS Signals Table Pentium® Processor/Slot System Signal Groups. Table Pentium® Processor Absolute Maximum Ratings Table Pentium® Processor Voltage Current Specifications. Table GTL+ Signal Groups Specifications. Table Non-GTL+ Signal Groups Specifications. Table Pentium® Processor GTL+ Specifications.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table System Specifications (Clock) Table Valid Slot System Bus, Core Frequency Cache Frequencies Table GTL+ Signal Groups System Specifications. Table System Specifications (CMOS Signal Group). Table System Specifications (Reset Conditions). Table System Specifications (APIC Clock APIC I/O) Table System Specifications (TAP Connection). Table BCLK Signal Quality Specifications Table GTL+ Signal Groups Ringback Tolerance Table Signal Ringback Specifications NonGTL+ Signals Table Pentium® Processor Thermal Design Specification. Table Example Thermal Solution Performance Pentium® Processor Thermal Plate Power 37.0 Watts.
Table S.E.C. Cartridge Materials Table S.E.C. Cartridge Dimensions Table Description Table Processor Markings Table Signal Listing Order Number Table Signal Listing Order Signal Name. Table Boxed Processor Fan/Heatsink Spatial Dimensions Table Boxed Processor Fan/Heatsink Support Dimensions. Table Fan/Heatsink Power Signal Specifications. Table BR0# (I/O) BR1# Signals Rotating Interconnect Table BR[1:0]# Signal Agent Table Slot Occupation Truth Table Table Output Signals. Table Input Signals. Table Input/Output Signals (Single Driver). Table Input/Output Signals (Multiple Driver)
1.0.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
pipeline synchronous static (BSRAM) memories) multiple die. Transfer rates between Pentium processor core cache one-half processor core clock frequency scale with processor core frequency. Both TagRAM BSRAM receive clocked data directly from Pentium processor core. with Pentium processor, cache does connect Pentium processor System (see Figure with Pentium processor, Pentium processor dedicated bus, thus maintaining dual independent architecture deliver high bandwidth high performance (see Figure Pentium processor utilizes Single Edge Contact (S.E.C.) cartridge packaging technology. S.E.C. cartridge allows cache remain tightly coupled processor, while enabling high volume commercial SRAM components. cache performance optimized tested package level. S.E.C. cartridge utilizes surface mount technology substrate with edge finger connection. S.E.C. cartridge introduced Pentium processor will also used future Slot processors. S.E.C. cartridge following features: thermal plate, cover substrate with edge finger connection. thermal plate allows standardized heatsink attachment customized thermal solutions. full enclosure also protects surface mount components. edge finger connection maintains socketability system configuration. edge finger connector noted `Slot connector' this other documentation.
INTRODUCTION
Pentium processor next Intel386TM, Intel486TM, Pentium Pentium line Intel processors. Pentium processor, like Pentium processor, implements Dynamic Execution micro-architecture unique combination multiple branch prediction, data flow analysis speculative execution. This enables Pentium processor deliver higher performance than Pentium processor, while maintaining binary compatibility with previous Intel architecture processors. Pentium processor also executes technology instructions enhanced media communication performance. Pentium processor utilizes multiple low-power states such AutoHALT, StopGrant, Sleep Deep Sleep conserve power during idle times. Pentium processor utilizes same multiprocessing System technology Pentium processor. This allows higher level performance both uni-processor two-way multi-processor (2-way systems. Memory cacheable addressable memory space, allowing significant headroom business desktop systems. Pentium processor System operates same manner Pentium processor System Bus. Pentium processor System uses GTL+ signal technology. Pentium processor deviates from Pentium processor using commercially available cache. cache (the TagRAM burst
Processor Core
Processor Core
Schematic only
Pentium Processor Dual Cavity Package
Pentium Processor Substrate Components
000756c
Figure Second Level (L2) Cache Implementations
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
1.1.
Terminology
Additional terms referred this other related documentation: Slot connector that S.E.C. cartridge plugs into, just Pentium® processor uses Socket Retention mechanism enabled mechanical piece which holds package Slot connector. Heatsink support support pieces that mounted motherboard provide added support heatsinks. cache (TagRAM, BSRAM) dies keep standard industry names.
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D#[3:0] `LHLH' also refers High logic level, logic level). term "System Bus" refers interface between processor, system core logic (a.k.a. PCIset components) other agents. System multiprocessing interface processors, memory I/O. term "Cache Bus" refers interface between processor cache components (TagRAM BSRAMs). Cache does connect System Bus, visible other agents System Bus.
1.2.
References
reader this specification should also familiar with material concepts presented following documents: AP-485, Intel Processor Identification With CPUID Instruction (Order Number 241618) AP-585, Pentium® Processor GTL+ Guidelines (Order Number 243330) AP-586, Pentium® Processor Thermal Design Guidelines (Order Number 243333) AP-587, Pentium® Processor Power Distribution Guidelines (Order Number 243332) AP-588, Mechanical Assembly Technology S.E.C. Cartridge Processors (Order Number 243333) AP-589, Pentium® Processor Electro-Magnetic Interference (Order Number 243334) Pentium® Processor Specification Update (Order Number 243337) Pentium® Processor Buffer Models, IBIS Format (Electronic Form) Pentium® Processor Developer's Manual (Order Number 243341) Intel Architecture Software Developer's Manual Volume Basic Architecture (Order Number 243190) Volume Instruction Reference (Order Number 243191) Volume III: System Programming Guide (Order Number 243192)
1.1.1.
S.E.C. CARTRIDGE TERMINOLOGY
following terms used often this document explained here clarification: Pentium® processor entire product including internal components, substrate, thermal plate cover. S.E.C. cartridge processor packaging technology called "Single Edge Contact cartridge." Processor substrate -The structure which components mounted inside S.E.C. cartridge (with without components attached). Processor core processor's execution engine. Thermal plate surface used connect heatsink other thermal solutions processor. Cover processor casing opposite side thermal plate. Latch Arms processor feature that utilized means securing processor retention mechanism.
2.0. 2.1.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
ELECTRICAL SPECIFICATIONS Pentium® Processor System VREF
243341) GTL+ specification. VREF generated S.E.C. cartridge Pentium processor core. Local VREF copies should generated motherboard other devices GTL+ System Bus. Figure schematic representation GTL+ topology with Pentium processor. GTL+ depends incident wave switching. Therefore timing calculations GTL+ signals based flight time opposed capacitive deratings. Analog signal simulation Pentium processor System including trace lengths highly recommended when designing system with heavily loaded GTL+ bus. Intel's World Wide page (http://www.intel.com) download buffer models, Pentium® Processor Buffer Models, IBIS Format (Electronic Form).
Most Pentium processor signals variation voltage Gunning Transceiver Logic (GTL) signaling technology. Pentium processor System specification similar specification, been enhanced provide larger noise margins reduced ringing. improvements accomplished increasing termination voltage level controlling edge rates. Because this specification different from standard specification, referred GTL+ this document. more information GTL+ specifications, AP-585, Pentium® Processor GTL+ Guidelines (Order Number 243330). GTL+ signals open-drain requires termination supply that provides high signal level. GTL+ inputs differential receivers which require reference signal (VREF). Termination (usually resistor each signal trace) used pull high voltage level control reflections transmission line. VREF used receivers determine signal logical logical generated S.E.C. cartridge processor core. processor contains termination resistors that provide termination Pentium processor System Bus. Termination (usually resistor each signal trace) used pull high voltage level control reflections transmission line. Table termination voltage specifications GTL+ Pentium® Processor Developer's Manual (Order Number
2.2.
Clock Control Power States
Pentium processor allows AutoHALT, Stop-Grant, Sleep Deep Sleep states reduce power consumption stopping clock internal sections processor, depending each particular state. Figure visual representation Pentium processor power states. processor fully realize current consumption Stop-Grant, Sleep Deep Sleep states, Model Specific Register (MSR) must set. 02AH (Hex), must (this power default setting) processor stop internal clocks during these modes. more information, Pentium® Processor Developer's Manual (Order Number 243341).
Stubs Pentium® Processor ASIC ASIC Pentium Processor
000916
Figure GTL+ Topology
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
HALT Instruction HALT Cycle Generated Auto HALT Power Down State BCLK running. Snoops interrupts allowed. INIT#, BINIT#, INTR, NMI, SMI#, RESET# Normal State Normal execution.
STPCLK# De-asserted SLP# De-asserted
Snoop Event Occurs Snoop Event Serviced
-ass erted
Snoop Event Occurs
sser
STPCLK# Asserted
HALT/Grant Snoop State BCLK running. Service snoops caches.
Snoop Event Serviced
Stop Grant State BCLK running. Snoops interrupts allowed.
SLP# Asserted
Sleep State BCLK running. snoops interrupts allowed. BCLK Input Stopped BCLK Input Restarted
Deep Sleep State BCLK stopped. snoops interrupts allowed.
B757a
Figure Stop Clock State Machine
inability processors recognize transactions during Sleep state Deep Sleep state, two-way systems allowed have processor Sleep/Deep Sleep state other processor Normal Stop-Grant states simultaneously.
2.2.2.
AUTO HALT POWER DOWN STATE STATE
2.2.1.
NORMAL STATE STATE
AutoHALT power state entered when processor executes HALT instruction. processor will transition Normal state upon occurrence SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR). RESET# will cause processor immediately initialize itself. return from handler either Normal Mode AutoHALT Power Down state. Intel Architecture Software Developer's Manual, Volume III: System Programming Guide (Order Number 243192) more information.
This normal operating state processor.
2.2.3.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
HALT/Grant Snoop state. processor will stay this state until snoop Slot processor System been serviced (whether processor another agent Slot processor another agent Slot processor System Bus). After snoop serviced, processor will return Stop-Grant state AutoHALT Power Down state, appropriate.
FLUSH# will serviced during AutoHALT state processor will return AutoHALT state. system generate STPCLK# while processor AutoHALT Power Down state. When system deasserts STPCLK# interrupt, processor will return execution HALT state.
STOP-GRANT STATE STATE
2.2.5.
SLEEP STATE STATE
Stop-Grant state processor entered when STPCLK# signal asserted. Since GTL+ signal pins receive power from System Bus, these pins should driven (allowing level return VTT) minimum power drawn termination resistors this state. addition, other input pins System should driven inactive state. FLUSH# will serviced during Stop-Grant state processor will return Stop-Grant state. RESET# will cause processor immediately initialize itself, processor will stay StopGrant state. transition back Normal state will occur with deassertion STPCLK# signal. transition HALT/Grant Snoop state will occur when processor detects snoop System (see Section 2.2.4.). transition Sleep state (see Section 2.2.5.) will occur with assertion SLP# signal. While Stop-Grant state, SMI#, INIT# LINT[1:0] will latched processor, only serviced when processor returns Normal state. Only occurrence each event will recognized upon return Normal state.
Sleep state very power state which processor maintains context, maintains phase-locked loop (PLL), stopped internal clocks. Sleep state only entered from Stop-Grant state. Once Stop-Grant state, SLP# asserted, causing processor enter Sleep state. SLP# recognized Normal AutoHALT states. Snoop events that occur while Sleep state during transition into Sleep state will cause unpredictable behavior. Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals (with exception SLP# RESET#) allowed system while processor Sleep state. transition input signal before processor returned Stop Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop-Grant state. RESET# driven active while processor Sleep state, SLP# STPCLK# signals should deasserted immediately after RESET# asserted ensure processor correctly executes Reset sequence. While Sleep state, processor capable entering lowest power state, Deep Sleep state, stopping BCLK input. (see Section 2.2.6.) Once Sleep Deep Sleep states, SLP# deasserted another asynchronous System event occurs. SLP# minimum assertion BCLK period.
2.2.4.
HALT/GRANT SNOOP STATE STATE
processor will respond snoop transactions Slot processor System while Stop-Grant state AutoHALT Power Down state. During snoop transaction, processor enters
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
2.2.6. DEEP SLEEP STATE STATE
Deep Sleep state lowest power state processor enter while maintaining context. Deep Sleep state entered stopping BCLK input (after Sleep state entered from assertion SLP# pin). processor Deep Sleep state immediately after BCLK stopped. recommended that BCLK input held during Deep Sleep state. Stopping BCLK input lowers overall current consumption leakage levels. re-enter Sleep state, BCLK input must restarted. period allow stabilization) must occur before processor considered Sleep state. While Deep Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals allowed System while processor Deep Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior.
Sleep states. When transitioning from Deep Sleep Sleep states, PICCLK must restarted with BCLK.
2.3.
Power Ground Pins
future versions Pentium processors released, operating voltage processor core cache differ from each other. There groups power inputs Pentium processor package support possible voltage difference between components package. There also five pins defined package voltage identification (VID). These pins specify voltage required processor core. These have been added cleanly support voltage specification variations current future Pentium processors. clean on-chip power distribution, Pentium processors have (power) (ground) inputs. pins further divided provide different voltage levels components. VccCORE inputs processor core some cache components account pins, while inputs (1.5 used provide GTL+ termination voltage processor VccL2 inputs (3.3 cache TagRAM BSRAMs. Vcc5 provided Slot Test Kit. Vcc5, VccL2, VccCORE must remain electrically separated from each other. circuit board, VccCORE pins must connected voltage island VccL2 pins must connected separate voltage island island portion power plane that been divided, entire plane). Similarly, pins must connected system ground plane.
2.2.7.
CLOCK CONTROL POWER MODES
processor provides clock signal cache. During AutoHALT Power Down StopGrant states, processor will process snoop phase System cycle. processor will stop clock data cache during AutoHALT Power Down Stop-Grant states. Entrance into HALT/Grant Snoop state will allow cache snooped, similar Normal state. When processor Sleep Deep Sleep states, will respond interrupts snoop transactions. During Sleep state, clock cache stopped. During Deep Sleep state, clock cache stopped. clock cache will restarted only after internal clocking mechanism processor stable (i.e., processor re-entered Sleep state). PICCLK should removed during AutoHALT Power Down Stop-Grant states. PICCLK removed during Sleep Deep
2.4.
Decoupling Guidelines
large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. This causes voltages power planes below their nominal value bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed this document. Failure result timing violations reduced lifetime component.
Regulator solutions need provide bulk capacitance with Effective Series Resistance (ESR) keep interconnect resistance from regulator pins) Slot connector less than This accomplished keeping maximum distance inches between regulator output Slot connector. recommended VccCORE interconnect inch wide (the width connector) inch long (maximum distance between Slot connector connector) plane segment with standard 1-ounce plating. Bulk decoupling large current swings when processor powering entering/exiting power states, provided voltage regulation module (VRM) defined Pentium® Processor Power Distribution Guidelines. VccCORE input should capable delivering recommended minimum dIccCORE/dt (defined Table while maintaining tolerances (also defined Table
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
243341) definition these pins during Reset operation pins after Reset. Figure timing relationship between System multiplier signals, RESET#, CRESET# normal processor operation. Table list multipliers supported. other multipliers authorized supported. Using CRESET# (CMOS reset baseboard), circuit Figure used share these configuration signals. component used multiplexer must have outputs that drive higher than order meet Pentium processor's tolerant buffer specifications. multiplexer output current should limited maximum, case VccCORE supply processor ever fails. shown Figure pull-up resistors between multiplexer processor (330 force ratio into processor event that Pentium processor powers before multiplexer and/or core logic. This prevents processor from ever seeing ratio higher than final ratio. multiplexer were powered Vcc2.5, pulldown could used CRESET# instead four pull-up resistors between multiplexer Pentium processor. this case, multiplexer must designed such that compatibility inputs truly ignored, their state unknown. compatibility inputs multiplexer must meet input specifications multiplexer. This require level translation before multiplexer inputs unless inputs signals driving them already compatible. mode operation, multiplexer will need clocked using BCLK meet setup hold times processors. This require high speed programmable logic. Multiplying clock frequency required increase performance while allowing cost effective distribution signals within system. System frequency multipliers supported shown Table other combinations will validated they authorized implementation.
2.4.1.
SYSTEM GTL+ DECOUPLING
Pentium processor contains high frequency decoupling capacitance processor substrate; however, bulk decoupling must provided system motherboard proper GTL+ operation. AP-585, Pentium® Processor GTL+ Guidelines (Order Number 243330); AP-587, Pentium® Processor Power Distribution Guidelines (Order Number 243332); Pentium® Processor Developer's Manual (Order Number 243341) more information.
2.5.
Pentium® Processor System Clock Processor Clocking
BCLK input directly controls operating speed Pentium Processor System interface. Pentium Processor System timing parameters specified with respect rising edge BCLK input. Pentium processor core frequency must configured during Reset using A20M#, IGNNE#, LINT[1]/NMI LINT[0]/INTR pins. (See Table value these pins during Reset determines multiplier that will internal core clock. Pentium® Processor Developer's Manual (Order Number
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
IGNNE#
Table Core Frequency System Multiplier Configuration Ratio System Processor Core Frequency LINT[1] LINT[0] A20M#
BCLK
RESET#
CRESET# System Multiplier
Final Ratio
Final Ratio
Compatibility
000917a
Figure Timing Diagram System Multiplier Signals
A20M# IGNNE# LINT1/NMI LINT0/INTR
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Pentium® Processors
Ratio:
CRESET#
000918
Figure Example Schematic System Multiplier Sharing
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Clock multiplying within processor provided internal Phase Lock Loop (PLL), requiring constant frequency BCLK input. System frequency ratio cannot changed dynamically during normal operation, changed during power modes. System frequency ratio changed when RESET# active, assuming that Reset specifications met. BCLK frequency should changed Deep Sleep state. (See Section 2.2.6.)
Table provides definition VID[4:0]. ensure system ready Pentium processor variations, range values which BOLD Table must supported. smaller range will risk ability system migrate higher performance processor. wider range provides more flexibility acceptable. Support wider range settings will benefit system meeting power requirements future processors. Note that `11111' (all opens) used detect absence processor core Slot connector long power supply used does affect these lines. Detection logic pull-ups should affect inputs power source. (See Section A.1.53.) pins should pulled TTLcompatible level with external resistors power source regulator only required regulator external logic monitoring VID[4:0] signals. power source chosen must guaranteed stable whenever supply voltage regulator stable. This will prevent possibility processor supply going above event failure supply lines. case DC-to-DC converter, this accomplished using input voltage converter line pull-ups. resistor greater than equal ohms should used connect signals converter input. Pentium® Processor Power Distribution Guidelines further information power supply specifications Pentium processor future Slot processors.
2.5.1.
MIXING PROCESSORS DIFFERENT FREQUENCIES
Mixing processor different internal clock frequencies fully supported been validated Intel. Intel recommends using identical steppings processor running same core/system frequencies.
2.6.
Voltage Identification
There five voltage identification pins Pentium processor/Slot connector. These pins used support automatic selection power supply voltages. These pins signals, either open circuit short circuit processor. combination opens shorts defines voltage required processor core. pins needed cleanly support voltage specification variations Pentium future processors. These pins (VID[0] through VID[4]) defined Table this table refers open refers short ground. definition provided below superset definition previously defined Pentium processor. power supply must supply voltage that requested disable itself.
VID4
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Voltage Identification Definition1, Processor Pins VID3 VID2 VID1 VID0 VccCORE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.80 1.85 1.90 1.95 2.00 2.05 Core
NOTES: Processor connected VSS. Open processor; pulled motherboard. Pentium® Processor Power Distribution Guidelines (Order Number 243332). output should disabled VccCORE values less than 1.80 ensure system ready Pentium® processor variations, values BOLD Table must supported.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
2.7.
Pentium® Processor System Unused Pins
RESERVED pins must remain unconnected. Connection Reserved pins VccCORE, VccL2, signal result component malfunction incompatibility with future Slot products. Section 5.2. listing processor location each Reserved pin. TESTHI pins must connected pull-up resistor between value. PICCLK must driven with valid clock input PICD[1:0] lines must pulled-up even when local APIC will used. separate pull-up resistor must provided each PICD line (see Table recommended values). Table Recommended Pull-Up Resistor Values (Approximate) CMOS Signals1, Recommended Resistor Value (Approximate)
connected 2.5V. Unused active high inputs should connected ground (VSS). Unused outputs left unconnected. resistor must used when tying bi-directional signals power ground. When tying signal power ground, resistor will also allow system testability. unused pins, suggested that resistors used pull-ups (except PICD[1:0] discussed above) resistors used pull-downs.
2.8.
Pentium® Processor System Signal Groups
order simplify following discussion, Pentium processor System signals have been combined into groups buffer type. Pentium processor System outputs open drain require high-level source provided externally termination pull-up resistor. GTL+ input signals have differential input buffers, which VREF reference signal. GTL+ output signals require termination this document, term "GTL+ Input" refers GTL+ input group well GTL+ group when receiving. Similarly, "GTL+ Output" refers GTL+ output group well GTL+ group when driving. pins should connected motherboard ground and/or chassis ground through zero resistors. zero resistors should placed close proximity Slot connector. path chassis ground should short length have impedance. CMOS, Clock, APIC JTAG inputs each driven from ground CMOS, APIC JTAG outputs open drain should pulled high This ensures only correct operation Pentium processor, compatibility future Slot products well. Table recommended pull-up resistor values each CMOS signal. resistors expected PICD[1:0] lines. Other values Table specified proper logic analyzer test mode operation only. groups signals contained within each group shown Table Refer Appendix descriptions these signals.
CMOS Signal TDO, TMS, PICD[0]#, PICD[1]# FERR#, IERR#, THERMTRIP# A20M#, IGNNE#, INIT#, LINT[1]/NMI, LINT[0]/INTR, PWRGOOD, SLP#, PREQ#, STPCLK#, SMI# FLUSH#
NOTES: These resistor values recommended system implementations using open drain CMOS buffers. These approximate resistor values proper operation debug tools only ~150 pull-up resistor expected these signals. TRST# signal must driven power reset. This accomplished with pulldown resistor.
reliable operation, always connect unused inputs bi-directional signals appropriate signal level. Unused GTL+ inputs should left connects; GTL+ termination provided processor. Unused active CMOS inputs should
GTL+ Input GTL+ Output GTL+ CMOS Input CMOS Output Host Clock APIC Clock APIC I/O5 Input5 Output5 Power/Other6
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Pentium® Processor/Slot System Signal Groups Group Name Signals BPRI#, BR1# DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#, SLP#3, STPCLK# FERR#, IERR#, THERMTRIP#4 BCLK PICCLK PICD[1:0] TCK, TDI, TMS, TRST# VccCORE, VccL2, Vcc5, VID[4:0], VTT, VSS, SLOTOCC#, TESTHI, BSEL#,
NOTES: BR0# only BREQ signal that bi-directional. internal BREQ# signals mapped onto pins after agent determined. Appendix more information. Section A.1.35 information PWRGOOD signal. Section 2.2.5 Section A.1.42 information SLP# signal. Section A.1.49 information THERMTRIP# signal. These signals specified operation. Table recommended pull-up resistor values. VccCORE power supply processor core cache logic. VccL2 power supply cache component core logic. VID[4:0] described Section 2.6. used terminate System generate VREF processor substrate. system ground. TESTHI should connected with 1K-10K resistor. Vcc5 connected Pentium® processor. This supply used debug purposes only. SLOTOCC# described Section A.1.41. BSEL# should connected VSS. Appendix descriptions.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
2.8.1. ASYNCHRONOUS SYNCHRONOUS SYSTEM SIGNALS
GTL+ signals synchronous BCLK. CMOS, Clock, APIC signals applied asynchronously BCLK, except when running processors mode. Synchronization logic required signals going both processors order mode. Also note timing requirements mode operation. With enabled, PICCLK must BCLK synchronized with respect BCLK. PICCLK must always BCLK specified Table APIC signals synchronous PICCLK. signals synchronous TCK.
connectors; Slot terminator substrate connects TDO. Pentium® Processor Developer's Manual (Order Number 243341) more details.
2.10.
Maximum Ratings
Table contains Pentium processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
2.9.
Test Access Port (TAP) Connection
2.11.
Processor Specifications
voltage levels supported other components Test Access Port (TAP) logic, recommended that Pentium processor first chain followed other components within system. translation buffer should used connect rest chain unless other components capable accepting input. Similar considerations must made TCK, TRST#. copies each signal required with each driving different voltage level. Debug Port described Pentium® Processor Developer's Manual (Order Number 243341). Debug Port will have placed start chain with first component coming from Debug Port from last component going Debug Port. 2-way system, cautious when including empty Slot connector scan chain. connectors scan chain must have processor installed complete chain system must support method bypass empty
processor specifications this section defined Pentium processor edge fingers. Appendix processor edge finger signal definitions. Most signals Pentium processor System GTL+ signal group. These signals specified terminated specifications these signals listed Table allow connection with other devices, Clock, CMOS, APIC designed interface non-GTL+ levels. specifications these pins listed Table Table through Table list specifications Pentium processor. Specifications valid only while meeting specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter.
Symbol TStorage VCC(All) VinGTL+ VinCMOS IVID ISLOTOCC Mech Latch Arms Mech Edge Fingers
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Pentium® Processor Absolute Maximum Ratings Parameter Processor storage temperature processor supply voltage with respect -0.5 Operating Voltage +1.4 Operating Voltage +1.0 GTL+ buffer input voltage with respect CMOS buffer input voltage with respect current SLOTOCC# current Mechanical integrity latch arms Mechanical integrity substrate edge fingers -0.5 -0.3 -0.5 -0.3 CORE +0.7 Unit Notes
Cycles Insertion/ Extraction
1,2,8
NOTES: Operating voltage voltage which component designed operate. Table This rating applies VccCORE, VccL2, Vcc5 input (except noted below) processor. Parameter applies CMOS, APIC signal groups only. mechanical integrity latch arms specified last maximum cycles. electrical mechanical integrity substrate edge fingers specified last insertion/extraction cycles. Intel performed internal testing showing functionality single S.E.C. cartridge processors after 5000 insertions. While insertion/extraction cycling above insertions cause increase contact resistance (above ohms) degradation material integrity edge finger gold plating, possible have processor functionality above specified limit. actual number insertions before processor failure will vary based upon system configuration environmental conditions. This specification applies 63x. This specification applies 65x.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Notes ±3%, ±9%4
Table Pentium® Processor Voltage Current Specifications Symbol VccCORE Parameter processor core Core Freq VccL2 Baseboard Tolerance, Static cache termination voltage Baseboard voltage, static tolerance level VccCORE Tolerance, Static VccCORE voltage, static tolerance level VccCORE Tolerance, Transient VccCORE voltage, transient tolerance level IccCORE VccCORE IccL2 Ivtt cache Termination voltage supply current 3.135 1.365 -0.070 -0.150 -0.150 -0.120 -0.145 -0.120 -0.090 -0.090 -0.085 -0.090 -0.085 -0.195 -0.195 -0.140 -0.185 -0.140 2.80 2.80 2.00 2.80 2.00 2.00 3.30 3.465 1.635 0.100 0.150 0.150 0.120 0.145 0.120 0.100 0.100 0.100 0.100 0.100 0.195 0.195 0.140 0.185 0.140 11.8 12.7 8.492 14.2 9.303 2.677 Unit
Baseboard Baseboard voltage, transient Tolerance, Transient tolerance level
Symbol IccDSLP CORE IccSGNT IccSLP IccDSLP dlccCORE/dt dlccL2/dt dlccVtt/dt Vcc5 Icc5
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Pentium® Processor Voltage Current Specifications (Cont'd) Parameter Deep Sleep VccCORE Stop-Grant VccL2 Sleep VccL2 Deep Sleep VccL2 Power supply current slew rate cache power supply current slew rate Termination current slew rate supply voltage supply voltage 4.75 5.00 Core Freq 0.35 0.35 5.25 Unit Notes
A/µs A/µs A/µs A/µs Table
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. IccCORE VccCORE supply processor core cache buffers. VccL2 IccL2 supply cache core. must held ±9%. recommended that held V±3% during System idle. These tolerance requirements, across bandwidth, Slot connector pins bottom side baseboard. requirements Slot connector pins account voltage drops (and impedance discontinuities) across connector, substrate edge fingers processor core. Slot connector following requirements: Self Inductance: 10.5 nH(max); Capacitance: (max, MHz); Contact Resistance: (max averaged over power/ground contacts). Contact Intel testing conditions these requirements. These tolerance requirements, across bandwidth, processor substrate edge fingers. requirements processor substrate edge fingers account voltage drops (and impedance discontinuities) substrate edge fingers processor core. typical IccCORE measurements average current draw during execution Winstone* Windows* operating system. These numbers meant guideline only, guaranteed specification. Actual measurements will vary based upon system environmental conditions configuration. measurements measured nominal voltage under maximum signal loading conditions. current specified current required single Pentium® processor. similar current needed opposite GTL+ bus. current specified also AutoHALT Power Down state. Maximum values specified design/characterization nominal VccCORE nominal VccL2. Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. dICC/dt measured Slot connector pins. Vcc5 Icc5 used Pentium processor. This supply used debug purposes only. Typical Voltage Specification with tolerance level specification provide correct voltage regulation processor. Voltage regulators designed with minimum equivalent internal resistance ensure that output voltage, maximum current output, greater than nominal voltage level CORE (VccCORE_TYP). this case, maximum current level regulator, IccCORE_REG, reduced from specified maximum current IccCORE_MAX calculated equation: IccCORE_REG IccCORE_MAX VccCORE_TYP VccCORE_MAX This specification applies 63x. This specification applies 65x.
Symbol
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table GTL+ Signal Groups Specifications Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage 0.015 Output Current Leakage Current Output Leakage Current -0.3 1.22 0.82 0.60 ±100 Unit Notes
NOTES: Parameter measured into resistor +5%). VOUT +5%). Table This specification applies 63x. This specification applies 65x.
Table Non-GTL+ Signal Groups Specifications Symbol Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Output Current Input Leakage Current Output Leakage Current ±100 -0.3 2.625 2.625 Unit maximum outputs opendrain Notes
NOTES: Parameter measured (for with inputs). +5%). VOUT +5%).
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
2.12.
GTL+ System Specifications
Appendix Pentium processor edge finger signal definitions. Table through Table list specifications associated with Pentium processor System Bus. System specifications broken into following categories: Table Table contain System clock core frequency Cache frequencies; Table contains GTL+ specifications Table contains CMOS signal group specifications; Table contains timings reset conditions; Table covers APIC timing; Table covers timing. System specifications GTL+ signal group relative rising edge BCLK input. GTL+ timings referenced VREF both logic levels unless otherwise specified. timings specified this section should used conjunction with buffer models provided Intel. These buffer models, which include package information, available IBIS format Intel's site: "http://www.intel.com". GTL+ layout guidelines also available AP-585, Pentium® Processor GTL+ Guidelines (Order Number 243330). Care should taken read notes associated with particular timing parameter.
recommended have GTL+ routed daisy-chain fashion with termination resistors each every signal trace. These termination resistors placed electrically between ends signal traces voltage supply generally chosen approximate substrate impedance. valid high levels determined input buffers using reference voltage called VREF. Table lists nominal specification GTL+ termination voltage (VTT). GTL+ reference voltage (VREF) should core logic using voltage divider motherboard. important that motherboard impedance specified held ±20% tolerance, that intrinsic trace capacitance GTL+ signal group traces known. more details GTL+, Pentium® Processor Developer's Manual (Order Number 243341) Pentium® Processor GTL+ Guidelines (Order Number 243330).
2.13.
Pentium® Processor System Specifications
System timings specified this section defined processor edge fingers. Timings will tested processor core during manufacturing. Timings processor edge fingers will specified design characterization.
Table Pentium® Processor GTL+ Specifications Symbol VREF Parameter Termination Voltage Termination Resistor Reference Voltage 1.365 1.635 Units Ohms Notes ±3%, ±9%2 ±2%3
NOTES: Pentium® processor contains GTL+ termination resistors signal trace processor substrate. Pentium processor generates VREF, processor, using voltage divider supplied through Slot connector. must held ±9%; dIccVtt/dt specified Table recommended that held during System idle. VREF generated processor nominally.
Parameter T1B:
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table System Specifications (Clock)1, 66.67 15.0 0.78 ±300 4.70 5.10 0.75 0.75 1.95 1.95 Unit Figure Notes processor core frequencies Absolute Value @>1.8 @<0.7 (0.7 V-1.8 (1.8 V-0.7
System Frequency BCLK Period BCLK Core Logic Offset BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time
NOTES: timings GTL+ signals referenced BCLK rising edge 0.70 processor edge fingers. This reference account trace length capacitance processor substrate, allowing processor core receive signal with reference 1.25 GTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor edge fingers. timings CMOS signals referenced BCLK rising edge 0.70 processor edge fingers. This reference account trace length capacitance processor substrate, allowing processor core reference voltage 1.25 CMOS signal timings (address bus, data bus, etc.) referenced 1.25 processor edge fingers. internal core clock frequency derived from System clock. System clock core clock ratio determined during initialization described Section 2.5. Table shows supported ratios each processor. BCLK period allows +0.5 tolerance clock driver variation. BCLK offset time absolute difference needed between BCLK signal rising edge arriving Slot edge finger arriving core logic 1.25 positive offset needed account delay between Slot connector processor core. positive offset ensures both processor core core logic receive BCLK edge concurrently. Section 3.1. System clock signal quality specifications. difficulty accurately measuring processor clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25 jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point clock driver, measured into load, should less than kHz. This specification ensured design and/or measured with spectrum analyzer. 100% tested. Specified design/characterization clock driver requirement.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
116.67 133.33 133.33 150.00 166.67
Table Valid Slot System Bus, Core Frequency Cache Frequencies1, BCLK Frequency (MHz) 66.67 66.67 66.67 66.67 66.67 Frequency Multipliers Supported Core Frequency Rating (MHz) 233.33 266.66 266.67 300.00 333.33 Cache Frequency (MHz)
NOTES: Contact your local Intel representative latest information processor frequencies and/or frequency multipliers. While other ratios defined, operation frequencies other than those listed supported. This specification applies 63x. This specification applies 65x.
Table GTL+ Signal Groups System Specifications1, T10: Parameter GTL+ Output Valid Delay GTL+ Input Setup Time GTL+ Input Hold Time RESET# Pulse Width 1.07 2.53 1.53 1.00 6.37 Unit Figure Notes
NOTES: 100% tested. Specified design characterization. timings GTL+ signals referenced BCLK rising edge 0.70 processor edge fingers. GTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor edge fingers. Valid delay timings these signals specified into minimum clocks must specified between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. Specification minimum 0.40 swing. Specification maximum swing. After VccCORE, VccL2 BCLK become stable.
T11: T12: T13: T14: T15: Parameter
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table System Specifications (CMOS Signal Group)1, 1.00 5.50 1.75 10.5 Unit BCLKs BCLKs Figure Active Inactive states Notes
Output Valid Delay Input Setup Time Input Hold Time Input Pulse Width, except PWRGOOD PWRGOOD Inactive Pulse Width
NOTES: 100% tested. Specified design characterization. timings CMOS signals referenced BCLK rising edge processor edge fingers. CMOS signal timings (address bus, data bus, etc.) referenced 1.25 processor edge fingers. These signals driven asynchronously, must driven synchronously mode. Valid delay timings these signals specified +5%. Table pull-up resistor values. ensure recognition specific clock, setup hold times with respect BCLK must met. INTR only valid during APIC disable mode. LINT[1:0]# only valid during APIC enabled mode. When driven inactive after VccCORE, VccL2 BCLK become stable.
Table System Specifications (Reset Conditions) T16: Parameter Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Setup Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Delay Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time Unit BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET# Before deassertion RESET# After assertion RESET# After clock that deasserts RESET#
T17:
BCLKs
T18:
T19:
BCLKs
T20:
BCLKs
NOTE: Reset, clock ratio defined these signals must safe value (their final lower multiplier) within this delay unless PWRGOOD being driven inactive.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Notes
Table System Specifications (APIC Clock APIC I/O)1, T21: Parameter PICCLK Frequency 30.0 12.0 12.0 12.0 33.3 500.0 Unit Figure
T21B: Mode BCLK PICCLK Offset T22: T23: T24: T25: T26: T27: T28: T29: PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time PICD[1:0] Valid Delay
NOTES: 100% tested. Specified design characterization. timings CMOS signals referenced PICCLK rising edge 0.70 processor edge fingers. CMOS signal timings (address bus, data bus, etc.) referenced 1.25 processor edge fingers. With enabled PICCLK must 1/4X BCLK synchronized with respect BCLK. Referenced PICCLK Rising Edge. open drain signals, Valid Delay synonymous with Float Delay. Valid delay timings these signals specified +5%. Table recommended pull-up resistor values.
T30: T31: T32: T33: T34: T35: T36: T37: T38: T39: T40: T41: T42: T43: T44: Parameter
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table System Specifications (TAP Connection)1 16.667 60.0 25.0 25.0 40.0 14.5 13.5 28.5 27.5 27.5 14.5 Unit @1.7 @0.7 (0.7 V-1.7 (1.7 V-0.7 Asynchronous2 Figure Notes
Frequency Period High Time Time Rise Time Fall Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Inputs Setup Time Non-Test Inputs Setup Time Non-Test Inputs Hold Time
NOTES: timings signals referenced rising edge 0.70 processor edge fingers. signal timings (address bus, data bus, etc.) referenced 1.25 processor edge fingers. 100% tested. Specified design characterization. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified +5%. Table pull-up resistor values. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals operations. During Debug Port operation, normal specified timings rather than signal timings.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
000807
BCLK Slot BCLK Core Logic
0.7V
1.25V
Figure BCLK Core Logic Offset NOTES FIGURE THROUGH FIGURE
Figure through Figure used conjunction with Table through Table timings GTL+ signals referenced BCLK rising edge 0.70 processor edge fingers. This reference account trace length capacitance processor substrate, allowing processor core receive signal with reference 1.25 Timings other components baseboard should BCLK reference voltage 1.25 GTL+ signal timings (address bus, data bus, etc.) referenced 1.00 Slot connector pin. These measurements collected Pentium® processor edge fingers.
1.8V 0.7V T25, (Rise Time) T26, (Fall Time) T23, (High Time) T24, (Low Time) T22, (BLCK, TCK, PICCLK Period)
000761b
1.25V
Figure BCLK, TCK, PICCLK Generic Clock Wave Form
Signal
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Valid T11, (Valid Delay) Valid
T14, (Pulse Wdith) 1.0V GTL+ signal group; 1.25V CMOS, APIC signal groups
000762b
Figure System Valid Delay Timings
Signal
Valid
T12, (Setup Time) T13, (Hold Time) 1.0V GTL+ signal group; 1.25V CMOS, APIC signal groups
000763b
Figure System Setup Hold Timings
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
000919
BCLK
PICCLK
T21B (FRC Mode BCLK PICCLK offset) Figure Mode BCLK PICCLK Timing
BCLK
RESET#
Configuration (A20M#, IGNNE#, LINT[1:0]#) Configuration (A[14:5], BR0#, FLUSH#, [1:0]#)
Safe
Valid Valid
(GTL+ Input Hold Time) (GTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Delay Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Setup Time)
PCB-764
Figure System Reset Configuration Timings
BCLK
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
CORE VREF
PWRGOOD
RESET# Configuration (A20M#, IGNNE#, LINT[1:0]#)
Valid Ratio (PWRGOOD Inactive Pulse Width) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0#]) Hold Time)
000765b
Figure Power-On Reset Configuration Timings
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
TDI,
1.25
Input Signals
Output Signals
(All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold Time) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Delay)
000766b
Figure Test Timings (TAP Connection)
TRST#
1.25V (TRST# Pulse Width)
PCB-773
Figure Test Reset Timings
3.0.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
below simulated contact processor edge fingers.
SYSTEM SIGNAL SIMULATIONS
Many scenarios have been simulated generate GTL+ layout guidelines which available Pentium® Processor GTL+ Guidelines (Order Number 243330). Refer Pentium® Processor Developer's Manual (Order Number 243341) GTL+ buffer specification. wave terms described
3.1.
System Clock (BCLK) Signal Quality Specifications
Table describes signal quality System clock (BCLK) signal. Figure describes signal quality wave form System clock.
Table BCLK Signal Quality Specifications Parameter BCLK BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback Tline Ledge Voltage Tline Ledge Oscillation -0.5 Unit Figure Overshoot, Undershoot Absolute Value1 Absolute Value1 Ledge Midpoint2 Peak-to-Peak3 Notes
NOTES: rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. BCLK processor edge fingers have ledge midway rising falling edge. midpoint voltage level this ledge must within range specified. ledge (V13) allowed have peak-to-peak oscillation specified.
000808
Figure BCLK, TCK, PICCLK Generic Clock Wave form Processor Edge Fingers
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Notes
Table GTL+ Signal Groups Ringback Tolerance Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Sequential Ringback -250 Unit Figure
NOTES: Specified edge rate V/ns. Figure generic wave form. values determined design/characterization. Ringback VREF +250 authorized.
VREF +0.2 VREF
VREF -0.2
0.7V
Vstart Clock
Time
NOTE: High case analogous.
000914a
Figure High GTL+ Receiver Ringback Tolerance
3.2. 3.3.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
3.3.1. OVERSHOOT/UNDERSHOOT GUIDELINES
GTL+ Signal Quality Specifications
Table Figure describe GTL+ signal quality specifications Pentium processor. more information GTL+ interface, Pentium® Processor Developer's Manual (Order Number 243341).
Non-GTL+ Signal Quality Specifications
Signals driven Pentium processor System should meet signal quality specifications ensure that components read data properly that incoming signals affect long term reliability component. There three signal quality parameters defined: Overshoot/Undershoot, Ringback Settling Limit. three signal quality parameters shown Figure non-GTL+ signal groups.
Overshoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot/undershoot guideline limits transitions beyond fast signal edge rates. (See Figure non-GTL+ signals.) processor damaged repeated overshoot events tolerant buffers charge large enough (i.e., overshoot great enough). However, excessive ringback dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating overshoot/undershoot guideline will make satisfying ringback specification difficult). overshoot/ undershoot guideline assumes absence diodes input. These guidelines should verified simulations without onchip protection diodes present because diodes will begin clamping tolerant signals beginning approximately 1.25 above VccCORE below VSS. signals reaching clamping voltage, this will issue. system should rely diodes overshoot/ undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Falling-Edge Ringback
Overshoot
Settling Limit
Rising-Edge Ringback
Settling Limit
Time
Undershoot
000767b
Figure Non-GTL+ Overshoot/Undershoot Ringback
3.3.2.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
3.3.3. SETTLING LIMIT GUIDELIN
RINGBACK SPECIFICATION
Ringback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. (See Figure illustration ringback.) Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal Ringback specification allowed under circumstances non-GTL+ signals. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications non-GTL+ signals.
Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed percent total signal swing (VHI-VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Table Signal Ringback Specifications Non-GTL+ Signals Input Signal Group Non-GTL+ Signals Non-GTL+ Signals Transition Maximum Ringback (with Input Diodes Present) Figure
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
4.0.
THERMAL SPECIFICATIONS DESIGN CONSIDERATIONS
Pentium processor thermal plate heatsink attachment. thermal plate interface intended provide multiple types thermal solutions. This chapter will provide necessary data thermal solution developed. Figure thermal plate location.
thermal power, even processor with lower thermal dissipation planned. thermal plate attach location thermal solutions. maximum allowed thermal plate temperature specified Table thermal solution should designed ensure temperature thermal plate never exceeds these specifications. processor power result heat dissipated through thermal plate other paths. heat dissipation combination heat from both processor core cache. overall system thermal design must comprehend processor power. combination processor core cache dissipating heat through thermal plate thermal plate power. heatsink should designed dissipate thermal plate power. Table Pentium processor thermal design specifications.
4.1.
Thermal Specifications
Table provides thermal design power dissipation Pentium processor. While processor core dissipates majority thermal power, thermal power dissipated cache also impacts thermal plate power specification overall processor power specification. Systems should design highest possible
Left Latch
Thermal Plate Right Latch
Cover Skirt
000921
Figure Processor S.E.C. Cartridge Thermal Plate
Processor Core Frequency (MHz)
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Pentium® Processor Thermal Design Specification1 Processor Power2 23.7 43.0 19.5 38.2 34.8 Thermal Plate Power3 21.8 41.4 17.8 37.0 33.6
Cache Size (kB)
TPLATE (°C)
TPLATE (°C)
TCOVER (°C)
TCOVER (°C)
NOTES: These values specified nominal VccCORE processor core nominal VccL2 (3.3 cache. Processor power 100% processor core 100% cache power. Thermal plate power 100% processor core power percentage cache power. This specification applies 63x. This specification applies 65x.
4.2.
Pentium® Processor Thermal Analysis
THERMAL SOLUTION PERFORMANC
solution performance Pentium processor different ambient temperatures around processor. Table Example Thermal Solution Performance Pentium® Processor Thermal Plate Power 37.0 Watts Thermal Solution (Performance) Local Ambient Temperature (TLA) thermal plate ambient (°C/watt) 1.08 0.95 0.81
4.2.1.
processor thermal solutions should attach thermal plate. thermal solution must adequately control thermal plate cover temperatures below maximum above minimum specified Table performance thermal solution defined thermal resistance between thermal plate ambient around processor (thermal plate ambient). lower thermal resistance between thermal plate ambient air, more efficient thermal solution required thermal plate ambient dependent upon maximum allowed thermal plate temperature (TPLATE), ambient temperature (TLA) thermal plate power (PPLATE). thermal plate ambient (TPLATE TLA) PPLATE maximum TPLATE thermal plate power listed Table function system design. Table provides resultant thermal
thermal plate ambient value made primary components: thermal resistance between thermal plate heatsink (thermal plate heatsink) thermal resistance between heatsink ambient around processor (heatsink air). critical controllable factor decrease resultant value thermal plate heatsink management thermal interface between thermal plate heatsink. Thermal interfaces addressed AP-586, Pentium® Processor Thermal Design Guidelines (Order Number 243333). other controllable factor (heatsink air) resultant design heatsink airflow around heatsink. Heatsink design constraints also provided AP-586, Pentium® Processor Thermal Design Guidelines (Order Number 243333).
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
4.2.2. MEASUREMENTS THERMAL SPECIFICATIONS Thermal Plate Temperature Measurement
4.2.2.1.
conduction through thermocouple leads, heat loss radiation convection, contact between thermocouple cement heatsink base. minimize these errors, following approach recommended: gauge finer diameter type thermocouples. Intel's laboratory testing done using thermocouple made Omega* (part number: 5TC-TTK-36-36). Attach thermocouple bead junction surface thermal plate location specified Figure using high thermal conductivity cements. thermocouple should attached angle heatsink attached thermal plate. heatsink attached thermal plate heatsink does cover location specified TPLATE measurement, thermocouple should attached angle (refer Figure 20).
ensure functional reliable Pentium processor operation, thermal plate temperature (TPLATE) must maintained below maximum TPLATE temperature specified Table Figure shows location TPLATE measurement. Special care required when measuring TPLATE ensure accurate temperature measurement. Thermocouples used measure TPLATE. Before taking temperature measurements, thermocouples must calibrated. When measuring temperature surface, errors introduced measurement handled properly. measurement errors poor thermal contact between thermocouple junction surface thermal plate,
Cover 2.673 Measure from edge thermal plate. Measure TPLATE this point.
Approx. location recommended heatsink attachment.
1.089 Processor Core
Substrate Recommended location 0.35 thermal grease application. dimensions inches.
000874b
Figure Processor Thermal Plate Temperature Measurement Location
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
000899
Figure Technique Measuring TPLATE with Angle Attachment
000900
Figure Technique Measuring TPLATE with Angle Attachment
thermocouple should attached angle heatsink attached thermal plate heatsink covers location specified TPLATE measurement (refer Figure 21). hole size through heatsink base route thermocouple wires should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heatsink base. This contact will affect thermocouple reading. Cover Temperature Measurement
4.3.
Thermal Solution Attach Methods
design thermal plate intended support different attach methods heatsink clips Rivscrews*. Figure shows thermal plate locations attach features. Only attach method should used thermal solution. 4.3.1. HEATSINK CLIP ATTACH
4.2.2.2.
maximum minimum S.E.C. cartridge cover temperature (TCOVER) Pentium processor specified Table This temperature specification meant ensure correct reliable operation processor. Figure illustrates hottest points S.E.C. cartridge cover. TCOVER thermal measurements should made these points.
Figure Figure illustrate example clip designs support profile full height heatsink, respectively. clips attach heatsink engaging with underside thermal plate. clearance thermal plate internal processor substrate minimum 0.124" (illustrated Figure Figure 24). clips should designed such that they will engage within this space, also damage substrate upon insertion removal. Finally, clips should able retain heatsink onto thermal plate through system level mechanical shock vibration test. clips should also apply high enough force spread interface material spot size selected.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
000966
1.31
Edge near Slot connector Figure Guideline Locations Cover Temperature (TCOVER) Thermocouple Placement
Thermal Plate 0.124
Spring Clip
Processor Core Processor Substrate Cover dimensions inches.
000877a
Figure Processor with Example Profile Heatsink Attached using Spring Clips
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Thermal Plate
0.124
Spring Clip
Processor Core Processor Substrate Cover dimensions inches.
000878a
Figure Processor with Example Full Height Heatsink Attached using Spring Clips
4.3.2.
RIVSCREW* ATTACH
Rivscrew attach mechanism uses specialized rivet that inserted through hole heatsink into thermal plate. Upon insertion, threaded fastener formed that removed necessary. Rivscrew attachment, minimum between thermal plate processor substrate
0.139". Advel Rivscrew (part number 1712-3510), heatsink base thickness must 0.140 ±0.010". Figure Figure Figure details heatsink requirements with Rivscrews. other heatsink base thickness, contact Advel other Rivscrew parts that would required.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
000901
Maximum Total Heatsink Depth
0.064 (Including Tolerance)
0.140 ±0.010 Recommended Heatsink Base Thickness dimensions inches.
0.305 fins allow clearance nose, Rivscrew* mandrel (Minimum)
Figure Heatsink Recommendations Guidelines with Rivscrews*
Mandrel Rivscrew* Heatsink Base Thermal Plate 0.139 Min. Processor Core Processor Substrate dimensions inches.
000915
0.140 ±0.010 Heatsink Base (Recommended) 0.144 ±0.005 Thermal Grease
Figure Heatsink Rivscrew* Thermal Plate Recommendations Guidelines
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Hole 0.150
0.005
0.305
eatsink
ensions inches.
000903
Figure General Rivscrew* Heatsink Mechanical Recommendations
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Figure Heatsink Attachment Mechanism Design Space
5.0.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
S.E.C. CARTRIDGE MECHANICAL SPECIFICATIONS
Pentium processor uses S.E.C. cartridge technology. S.E.C. cartridge contains processor core, cache other passive components. S.E.C. cartridge connects motherboard through edge connector. Mechanical specifications processor given this section. Section 1.1.1. complete terminology listing. Figure shows thermal plate side view cover side view processor. Figure shows S.E.C. cartridge dimensions. Figure through Figure provide details S.E.C. cartridge substrate edge finger contacts. processor edge connector defined this document referred "Slot
Table through Table provide processor edge fingers Slot connector signal definitions Pentium processor. signal locations Slot edge connector used signal routing, simulation component placement motherboard.
5.1.
S.E.C. Cartridge Materials Information
S.E.C. cartridge comprised multiple pieces make complete assembly. This section will provide information relevant acceptance package. complete S.E.C. cartridge assembly weighs approximately grams. Table Table further piece part information.
Table S.E.C. Cartridge Materials S.E.C. Cartridge Piece Thermal Plate Latch Arms Cover Skirt Piece Material Aluminum 6063-T6 Lexan 940, glass filled Lexan Lexan Table S.E.C. Cartridge Dimensions Symbol Description S.E.C. Cartridge Length S.E.C. Cartridge Height S.E.C. Cartridge Depth Thermal Plate Length Thermal Plate Height 5.495 2.457 0.637 5.324 1.917 5.515 2.489 0.657 5.354 1.927 Figure Maximum Piece Weight (Grams) 67.0 Less than latch 24.0
NOTE: This table applies dimensions noted Figure through Figure
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
NOTES FIGURE THROUGH FIGURE
Unless otherwise specified, following drawings dimensioned inches. dimensions provided with tolerances guaranteed normal production product. Figures drawings labeled "Reference Dimensions" provided informational purposes. Reference Dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference Dimensions checked part processor manufacturing. Drawings scale.
Left Latch
Right Latch
Cover
Left Latch
Thermal Plate Right Latch
Cover Skirt
000893a
Figure S.E.C. Cartridge Thermal Plate Cover Side Views
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Left Thermal Plate
Thermal Plate Side View
Right Left
Right Latch
Left Latch
Cover Side View
View
Cover
Right Side
Right
Skirt
000894b
Figure S.E.C. Cartridge Overall Cartridge Dimensions
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
0.127 ±0.005 0.340 ±0.005
3.805 ±0.020
2.473 ±0.016 2.070 ±0.020
1.235 ±0.020
These dimensions from bottom substrate edge fingers
0.265 ±0.005
1.845 ±0.005
1.830 ±0.005
NOTE: Figure details.
000906
Figure S.E.C Cartridge Thermal Plate Side Dimensions
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
0.0625 ±0.002
+0.001 -0.002
Detail
0.124
Detail
0.365 ±0.005
0.978 ±0.008
0.500 ±0.008
0.250 ±0.008
NOTE: Figure details.
000907
Figure S.E.C. Cartridge Thermal Plate Side View Dimensions
0.375 ±0.008
0.000
0.000
2.110 ±0.008
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
1.25 2.50
0.001 1.000 1.000
NOTE: dimensions without tolerance information considered reference dimensions only.
000908
Figure S.E.C. Cartridge Thermal Plate Flatness Dimensions
0.236
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
0.015
0.075 0.022 0.060 0.060 0.113 0.122 0.060 0.084
Detail
Detail (Bottom Side View)
0.120 Min. 0.277 0.058 0.316 0.116 0.216 0.055 0.291 0.276 0.082
Detail Detail
NOTE: dimensions without tolerance information considered reference dimensions only.
000909
Detail
Figure S.E.C. Cartridge Latch Details
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
0.647 ±0.015
0.238 ±0.010 0.103 0.005 0.174 ±0.005
0.488 ±0.010
0.058 ±0.005 0.253 ±0.010
0.136 ±0.005
Left
000910
Figure S.E.C. Cartridge Latch Arm, Thermal Plate Lug, Cover Dimensions
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Matrix Mark
pentium
with MMXtechnology
iCOMP® index=YYY SZNNN/XYZ ORDER CODE XXXXXXXX-NNNN
pentium
with MMXtechnology
Dynamic Mark Area
pentium
Hologram Location
000911a
Figure S.E.C. Cartridge Mark Locations
Table Description Table Processor Markings Code Letter Description Logo Product Name Trademark Logo Product Name Dynamic Mark Area with matrix
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
3.243 ±0.015
Thermal Plate
Cover
Skirt
2.263 ±0.015
Left
Bottom View
5.344 ±0.010
5.255 ±0.006
5.505 ±0.010
Right
000870d
Figure S.E.C. Cartridge Bottom Side View
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Thermal Plate
Cover
A121
Substrate
Detail Next Figure 1.850 2.008 ±0.008 5.000
+0.007 0.062 -0.005
2.835
2.992 ±0.008
NOTE: dimensions without tolerance information considered reference dimensions only.
000814d
Figure S.E.C. Cartridge Substrate Dimensions
ubstra
NOTE: Cover completely shown allow substrate details shown. This drawing shows details cover side S.E.C. cartridge.
000858c
Figure S.E.C. Cartridge Substrate Dimensions, Cover Side View
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
0.236
0.098 0.098
(0.010) 0.356 Min. 0.008
0.138 Min. 0.039 0.037 0.043 ±0.002 .008 .002
NOTE: dimensions without tolerance information considered reference dimensions only.
0.146 Max.
0.074 ±0.002
0.045 0.016 ±0.002 .008 .002
000859b
Figure Substrate S.E.C. Cartridge Substrate Detail
5.2.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Processor Edge Finger Signal Listing
Table processor substrate edge finger listing order number. Table Signal Listing Order Number Name VCC_VTT Signal Buffer Type GTL+ Supply GTL+ Supply CMOS Output CMOS Input CMOS Output CMOS Input JTAG Input JTAG Output CMOS Input CMOS Test Input CMOS Output Reserved Future CMOS Input CMOS CMOS Input GTL+ GTL+ GTL+ GTL+ Name FLUSH# SMI# INIT# VCC_VTT STPCLK# SLP# VCC_VTT TRST# Reserved VCC_CORE Reserved Reserved LINT[1]/NMI VCC_CORE PICCLK BP#[2] Reserved BSEL# PICD[1] PRDY# BPM#[1] VCC_CORE Signal Buffer Type Management CMOS Input CMOS Input CMOS Input GTL+ Supply CMOS Input JTAG Input CMOS Input GTL+ Supply JTAG Input JTAG Input Reserved Future Processor Core Reserved Future Reserved Future CMOS Input Processor Core APIC Clock Input GTL+ Reserved Future CMOS GTL+ Output GTL+ Processor Core
VCC_VTT IERR# A20M#
FERR# IGNNE# PWRGOOD TESTHI THERMTRIP# Reserved LINT[0]/INTR PICD[0] PREQ# BP#[3] BPM#[0] BINIT# DEP#[0]
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Number (Cont'd) Name DEP#[1] DEP#[3] DEP#[5] DEP#[6] D#[61] D#[55] D#[60] D#[53] D#[57] D#[46] D#[49] D#[51] D#[42] D#[45] D#[39] Reserved D#[43] D#[37] D#[33] D#[35] Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Reserved Future GTL+ GTL+ GTL+ GTL+ Name DEP#[2] DEP#[4] DEP#[7] VCC_CORE D#[62] D#[58] D#[63] VCC_CORE D#[56] D#[50] D#[54] VCC_CORE D#[59] D#[48] D#[52] D#[41] D#[47] D#[44] VCC_CORE D#[36] D#[40] D#[34] VCC_CORE D#[38] D#[32] D#[28] Signal Buffer Type GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Management GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+
D#[31] D#[30] D#[27] D#[24] D#[23] D#[21] D#[16] D#[13] D#[11] D#[10] D#[14] D#[9] D#[8] D#[5] D#[3] D#[1] BCLK BR0# BERR# A#[33]
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Number (Cont'd) Name Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Processor Clock Input GTL+ GTL+ GTL+ Name VCC_CORE D#[29] D#[26] D#[25] VCC_CORE D#[22] D#[19] D#[18] D#[20] D#[17] D#[15] VCC_CORE D#[12] D#[7] D#[6] VCC_CORE D#[4] D#[2] D#[0] VCC_CORE RESET# BR1# FRCERR VCC_CORE A#[35] A#[32] Signal Buffer Type Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Management GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ Input GTL+ Input GTL+ Processor Core GTL+ GTL+
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Number (Cont'd) A100 A101 A102 A103 A104 A105 A106 Name A#[34] A#[30] A#[31] A#[27] A#[22] A#[23] Reserved A#[19] A#[18] A#[16] A#[13] A#[14] A#[10] A#[5] A#[9] A#[4] BNR# BPRI# TRDY# DEFER# Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Reserved Future GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Input GTL+ Input GTL+ Input B100 B101 B102 B103 B104 B105 B106 Name A#[29] A#[26] A#[24] A#[28] VCC_CORE A#[20] A#[21] A#[25] VCC_CORE A#[15] A#[17] A#[11] VCC_CORE A#[12] A#[8] A#[7] VCC_CORE A#[3] A#[6] SLOTOCC# REQ#[0] REQ#[1] REQ#[4] VCC_CORE LOCK# Signal Buffer Type GTL+ Management GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ GTL+ Processor Core GTL+ GTL+ Management GTL+ GTL+ GTL+ Processor Core GTL+
A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 REQ#[2] REQ#[3] HITM# DBSY# RS#[1] Reserved ADS# Reserved AP#[0] VID[2] VID[1] VID[4]
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Number (Cont'd) Name Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ Input Reserved Future GTL+ Reserved Future GTL+ VccCORE VccCORE VccCORE B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 Name DRDY# RS#[0] VCC5 HIT# RS#[2] Reserved VCC_L2 RSP# AP#[1] VCC_L2 AERR# VID[3] VID[0] VCC_L2 Signal Buffer Type GTL+ GTL+ Input Other GTL+ GTL+ Input Reserved Future Other GTL+ GTL+ Input GTL+ Other GTL+ VccCORE VccCORE Other
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table processor substrate edge connector listing order name. Table Signal Listing Order Signal Name A100 Name A#[3] A#[4] A#[5] A#[6] A#[7] A#[8] A#[9] A#[10] A#[11] A#[12] A#[13] A#[14] A#[15] A#[16] A#[17] A#[18] A#[19] A#[20] A#[21] A#[22] A#[23] A#[24] A#[25] A#[26] A#[27] A#[28] Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ A115 B118 A117 B116 A101 A103 Name A#[29] A#[30] A#[31] A#[32] A#[33] A#[34] A#[35] A20M# ADS# AERR# AP#[0] AP#[1] BCLK BERR# BINIT# BNR# BP#[2] BP#[3] BPM#[0] BPM#[1] BPRI# BR0# BR1# BSEL# D#[0] D#[1]
Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ CMOS Input GTL+ GTL+ GTL+ GTL+ Processor Clock Input GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Input GTL+ GTL+ Input GTL+ GTL+
D#[2] D#[3] D#[4] D#[5] D#[6] D#[7] D#[8] D#[9] D#[10] D#[11] D#[12] D#[13] D#[14] D#[15] D#[16] D#[17] D#[18] D#[19] D#[20] D#[21] D#[22] D#[23] D#[24] D#[25] D#[26] D#[27] D#[28]
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Signal Name (Cont'd) Name Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ A045 A043 A044 A039 A040 A041 Name D#[29] D#[30] D#[31] D#[32] D#[33] D#[34] D#[35] D#[36] D#[37] D#[38] D#[39] D#[40] D#[41] D#[42] D#[43] D#[44] D#[45] D#[46] D#[47] D#[48] D#[49] D#[50] D#[51] D#[52] D#[53] D#[54] D#[55] Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Signal Name (Cont'd) A111 A105 B107 B100 Name D#[56] D#[57] D#[58] D#[59] D#[60] D#[61] D#[62] D#[63] DBSY# DEFER# DEP#[0] DEP#[1] DEP#[2] DEP#[3] DEP#[4] DEP#[5] DEP#[6] DEP#[7] DRDY# FERR# FLUSH# FRCERR Signal Buffer Type GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Input GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ GTL+ Management Management Management Management Management CMOS Output CMOS Input GTL+ A042 A102 A106 Name Signal Buffer Type
A110 A114 A118 B110 A109 B106 B102 B103 A107 A108 B104 A113 A116 HIT# HITM# IERR# IGNNE# INIT#
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Signal Name (Cont'd) Name Signal Buffer Type GTL+ GTL+ CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input GTL+ APIC Clock Input CMOS CMOS GTL+ Output CMOS Input CMOS Input GTL+ GTL+ GTL+ GTL+ GTL+ Reserved Future Reserved Future Reserved Future Reserved Future Reserved Future B112 B114 B108 A112 B111 B115 B101 A104 Name Reserved Reserved Reserved Reserved Reserved RESET# RS#[0] RS#[1] RS#[2] RSP# SLOTOCC# SLP# SMI# STPCLK# TESTHI THERMTRIP# TRDY# TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE Signal Buffer Type Reserved Future Reserved Future Reserved Future Reserved Future Reserved Future GTL+ Input GTL+ GTL+ Input GTL+ Input GTL+ Input GTL+ Input CMOS Input CMOS Input CMOS Input JTAG Input JTAG Input JTAG Output CMOS Test Input CMOS Output JTAG Input GTL+ Input JTAG Input Processor Core Processor Core Processor Core Processor Core
LINT[0]/INTR LINT[1]/NMI LOCK# PICCLK PICD[0] PICD[1] PRDY# PREQ# PWRGOOD REQ#[0] REQ#[1] REQ#[2] REQ#[3] REQ#[4] Reserved Reserved Reserved Reserved Reserved
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Table Signal Listing Order Signal Name (Cont'd) Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Signal Buffer Type Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core Processor Core B105 B113 B117 B121 B109 B120 A120 A119 B119 A121 Name VCC_CORE VCC_L2 VCC_L2 VCC_L2 VCC_VTT VCC_VTT VCC_VTT VCC_VTT VCC5 VID[0] VID[1] VID[2] VID[3] VID[4] Signal Buffer Type Processor Core Other Other Other GTL+ Supply GTL+ Supply GTL+ Supply GTL+ Supply Other VccCORE VccCORE VccCORE VccCORE VccCORE
6.0. 6.1.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
important OEMs that manufacture motherboards system integrators. Unless otherwise noted, figures this chapter dimensioned inches. Figure shows mechanical representation Boxed Pentium processor retention mechanism. NOTE airflow fan/heatsink into center sides fan/heatsink. large arrows Figure denote direction airflow.
BOXED PROCESSOR SPECIFICATIONS Introduction
Pentium processor also offered Intel Boxed processor. Intel Boxed processors intended system integrators build systems from motherboards standard components. Boxed Pentium processor will supplied with attached fan/heatsink. This chapter documents motherboard system requirements fan/heatsink that will supplied with Boxed Pentium processor. This chapter particularly
Boxed Processor Heatsink Support Mechanism Processor Shroud Covering Heatsink Fins
Retention Mechanism
Power Connector Motherboard Heatsink Support Mechanism
000904a
Figure Conceptual Boxed
Pentium®
Processor Retention Mechanism
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
6.2.
Mechanical Specifications
6.2.1.
This section documents mechanical specifications Boxed Pentium processor fan/heatsink.
BOXED PROCESSOR FAN/HEATSINK DIMENSIONS
Boxed processor will shipped with attached fan/heatsink. Clearance required around fan/heat sink ensure unimpeded flow proper cooling. space requirements dimensions Boxed Processor with integrated fan/heatsink shown Figure (Side View), Figure (Front View), Figure (Top View). dimensions inches.
1.291
Heatsink
S.E.C. Cartridge Cover
Slot Connector
0.485
000890a
Figure Side View Space Requirements Boxed Processor (fan heatsink supports shown)
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Power Cable Connector
4.90
2.19
1.25
000891a
Figure Front View Space Requirements Boxed Processor
Measure ambient temperature 0.3" above center inlet
0.40 Space (both ends) Space Heatsink
0.20 space
S.E.C. Cartridge Cover
000892
Figure View Space Requirements Boxed Processor Table Boxed Processor Fan/Heatsink Spatial Dimensions Fig. Ref. Label Dimensions (Inches) Fan/Heatsink Depth (off processor thermal plate) Fan/Heatsink Height above motherboard Fan/Heatsink Height (see front view) Fan/Heatsink Width (see front view) Airflow keepout zones from fan/heatsink Airflow keepout zones from face fan/heatsink 0.40 0.20 0.485 2.19 4.90 1.291
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
6.2.2. BOXED PROCESSOR FAN/HEATSINK WEIGHT
Boxed processor fan/heatsink will weigh more than grames. Section Section details processor weight heatsink requirements. 6.2.3. BOXED PROCESSOR RETENTION MECHANISM FAN/HEATSINK SUPPORT
Boxed processor will ship with heatsink support. support differs from supports passive heatsinks. Boxed processor fan/heatsink support requires heatsink support holes motherboard. Location size these holes give Figure motherboard components placed area beneath fan/heatsink supports must recognize clearance give Table below. Component height restrictions passive heatsink support designs, described AP-588, Mechanical Assembly Technology S.E.C. Cartridge Processors (Order Number 243333), still apply. Motherboards designed system integrators should have objects installed heatsink support holes. Otherwise, removal instructions objects pre-installed heatsink support holes should included motherboard documentation.
Boxed processor requires processor retention mechanism described AP-588, Mechanical Assembly Technology S.E.C. Cartridge Processors (Order Number 243333) secure processor Slot Boxed processor will ship with retention mechanism. Motherboards designed system integrators should include retention mechanism appropriate installation instructions.
Table Boxed Processor Fan/Heatsink Support Dimensions1, Fig. Ref. Label Dimensions (Inches) Fan/Heatsink support height Fan/Heatsink support clearance above motherboard Fan/Heatsink support standoff diameter Fan/Heatsink support front edge heatsink support hole center Fan/Heatsink support standoff protrusion beneath motherboard Motherboard thickness Spacing between fan/heatsink support posts Fan/Heatsink support width Fan/Heatsink support inner edge heatsink support hole 0.05 2.261 0.430 0.275 0.240 0.06 0.06 4.084 0.600 0.400 0.075 0.300
NOTES: This table applies dimensions noted Figure through Figure dimensions inches. Unless otherwise specified, x.xxx dimension tolerance ±0.005 inches. x.xx dimension tolerance ±0.01 inches.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Slot Connector
0.156 Thru
1.769
0.187 Thru Recommendations: 0.300 dia. trace keepout -all external layers 0.250 dia. trace keepout -all internal layers
2.932
1.950
dimensions inches.
000875
Figure Heatsink Support Hole Locations Sizes
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
2.261
0.275 (0.300 MAX) 0.060 0.430
0.060 0.240 1.769
000804
Figure Side View Space Requirements Boxed Processor Fan/Heatsink Supports
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
0.600
4.084
0.400
000805
Figure View Space Requirements Boxed Processor Fan/Heatsink Supports
6.3.
Boxed Processor Requirements
FAN/HEATSINK POWER SUPPLY
6.3.1.
motherboard pull-up resistor provides match motherboard-mounted speed monitor requirements, applicable. SENSE signal optional. SENSE signal used, connector should tied GND. power header baseboard must positioned allow fan/heatsink power cable reach power header identification location should documented motherboard documentation motherboard. Figure shows recommended location power connector relative Slot connector. motherboard power header should positioned within 4.75 inches (lateral) power connector.
Boxed processor's fan/heatsink requires power supply. power cable will shipped with Boxed processor draw power from power header motherboard. power cable connector pinout shown Figure Motherboards must provide matched power header support Boxed processor. Table contains specifications input output signals fan/heatsink connector. cable length will inches (±0.25"). fan/heatsink outputs SENSE signal, which open-collector output, that pulses rate pulses revolution.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
000888
Signal +12V SENSE Straight square pin, 3-pin terminal housing with polarizing ribs friction locking ramp. 0.100" pitch, 0.025" square width. Waldom*/Molex* 22-01-3037 equivalent. Match with straight pin, friction lock header motherboard Waldom/Molex 22-23-2031, AMP* 640456-3, equivalent.
Figure Boxed Processor Fan/Heatsink Power Cable Connector Description
Table Fan/Heatsink Power Signal Specifications Description volt power supply current draw SENSE: SENSE frequency (motherboard should pull this appropriate with resistor) pulses revolution 13.8
1.439
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
Slot Connector
power connector location (1.56 inches above motherboard)
1.449
4.75 inches
Motherboard power header should positioned within 4.75 inches power connector (lateral distance)
000913
Figure Recommended Motherboard Power Header Placement Relative Power Connector Slot
6.4.
Thermal Specifications
This section describes cooling requirements fan/heatsink solution utilized Boxed processor.
keep thermal plate temperature, TPLATE, within specifications (see Table 20), provided airflow through fan/heatsink unimpeded temperature entering below (see Figure measurement location). Airspace required around ensure that airflow through fan/heatsink blocked. Blocking airflow fan/heatsink reduces cooling efficiency decreases life. Figure illustrates acceptable airspace clearance fan/heatsink.
6.4.1.
BOXED PROCESSOR COOLING REQUIREMENTS
Boxed processor will cooled with fan/heatsink. Boxed processor fan/heatsink will
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
7.0.
ADVANCED FEATURES
Some nonessential information regarding Pentium processor considered Intel confidential proprietary documented this publication. This information available with appropriate nondisclosure agreements place. Please contact Intel Corporation details. This information specifically targeted software developers chipset manufacturers develop following types low-level software chipsets: operating system kernels virtual memory managers BIOS processor test software performance monitoring tools cycle information
software developers designing other categories software, this information does apply. required program development details provided Intel Architecture Software Developer's Manual: Volume Instruction Reference (Order Number 243191), which publicly available from Intel Corporation Literature Center. obtain this document, contact Intel Corporation Literature Center Intel Corporation Literature Center P.O. 7641 Prospect, 60056-7641 call 1-800-879-4683 reference Order Number 243191
A.1.1
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
APPENDIX
This appendix provides alphabetical listing Pentium processor signals. tables this appendix summarize signals direction: output, input, I/O. During active RESET#, each processor begins sampling A20M#, IGNNE# LINT[1:0] values determine ratio core-clock frequency busclock frequency. (See Table active-toinactive transition RESET#, each processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation; Figure example implementation this logic.
ALPHABETICAL SIGNALS REFERENCA[35:0]# (I/O)
A.1.3 A[35:3]# (Address) signals define 236-byte physical memory address space. When ADS# active, these pins transmit address transaction; when ADS# inactive, these pins transmit transaction type information. These signals must connect appropriate pins agents Pentium processor System Bus. A[35:24]# signals parity-protected AP1# parity signal, A[23:3]# signals parity-protected AP0# parity signal. active-to-inactive transition RESET#, processors sample A[35:3]# pins determine their power-on configuration. Pentium® Processor Developer's Manual (Order Number 243341) details.
ADS# (I/O)
ADS# (Address Strobe) signal asserted indicate validity transaction address A[35:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. This signal must connect appropriate pins Pentium processor System agents.
A.1.4
AERR# (I/O)
A.1.2
A20M#
A20M# (Address-20 Mask) input signal asserted, Pentium processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around 1-Mbyte boundary. Assertion A20M# only supported real mode. A20M# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding Write transaction.
AERR# (Address Parity Error) signal observed driven Pentium processor System agents, used, must connect appropriate pins Pentium processor System agents. AERR# observation optionally enabled during power-on configuration; enabled, valid assertion AERR# aborts current transaction. AERR# observation disabled during power-on configuration, central agent handle assertion AERR# appropriate Machine Check Architecture (MCA) system.
A.1.5
AP[1:0]# (I/O)
AP[1:0]# (Address Parity) signals driven request initiator along with ADS#, A[35:3]#, REQ[4:0]#, RP#. AP1# covers A[35:24]#,
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connect appropriate pins Pentium processor System agents.
BINIT# observation enabled during power-on configuration, BINIT# sampled asserted, state machines reset data which transit lost. agents reset their rotating arbitration state after reset, internal count information lost. caches affected. BINIT# observation disabled during power-on configuration, central agent handle assertion BINIT# appropriate Machine Check Architecture (MCA) system.
A.1.6
BCLK
BCLK (Bus Clock) signal determines frequency. Pentium processor System agents must receive this signal drive their outputs latch their inputs BCLK rising edge. external timing parameters specified with respect BCLK signal.
A.1.9
BNR# (I/O)
A.1.7
BERR# (I/O)
BNR# (Block Next Request) signal used assert stall agent unable accept transactions. During stall, current owner cannot issue transactions. Since multiple agents might need request stall same time, BNR# wire-OR signal which must connect appropriate pins Pentium processor System agents. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, BNR# activated specific clock edges sampled specific clock edges.
BERR# (Bus Error) signal asserted indicate unrecoverable error without protocol violation. driven Pentium processor System agents, must connect appropriate pins such agents, used. However, Pentium processors observe assertions BERR# signal. BERR# assertion conditions configurable system level. Assertion options defined following options: Enabled disabled. Asserted optionally internal errors along with IERR#. Asserted optionally request initiator transaction after observes error. Asserted agent when observes error transaction. BINIT# (I/O)
A.1.10
BP[3:2]# (I/O)
BP[3:2]# (Breakpoint) signals outputs from processor that indicate status breakpoints.
A.1.11
BPM[1:0]# (I/O)
A.1.8
BPM[1:0]# (Breakpoint Monitor) signals breakpoint performance monitor signals. They outputs from processor which indicate status breakpoints programmable counters used monitoring processor performance.
BINIT# (Bus Initialization) signal observed driven Pentium processor System agents, used must connect appropriate pins such agents. BINIT# driver enabled during power configuration, BINIT# asserted signal condition that prevents reliable future information.
A.1.12
BPRI#
BPRI# (Bus Priority Request) signal used arbitrate ownership Pentium processor System Bus. must connect appropriate pins
A.1.13
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
A.1.15 D[63:0]# (I/O)
Pentium processor System agents. Observing BPRI# active asserted priority agent) causes other agents stop issuing requests, unless such requests part ongoing locked operation. priority agent keeps BPRI# asserted until requests completed, then releases deasserting BPRI#.
D[63:0]# (Data) signals data signals. These signals provide 64-bit data path between Pentium processor System agents, must connect appropriate pins such agents. data driver asserts DRDY# indicate valid data transfer.
BR0# (I/O), BR1#
A.1.16
DBSY# (I/O)
BR0# BR1# (Bus Request) pins drive BREQ[1:0]# signals system. BREQ[1:0]# signals interconnected rotating manner individual processor pins. Table gives rotating interconnect between processor signals. Table BR0# (I/O) BR1# Signals Rotating Interconnect Signal BREQ0# BREQ1# Agent Pins BR0# BR1# Agent Pins BR1# BR0#
DBSY# (Data Busy) signal asserted agent responsible driving data Pentium processor System indicate that data use. data released after DBSY# deasserted. This signal must connect appropriate pins Pentium processor System agents.
A.1.17
DEFER#
During power-up configuration, central agent must assert BR0# signal. symmetric agents sample their BR[1:0]# pins active-toinactive transition RESET#. which agent samples active level determines agent agents then configure their pins match appropriate signal protocol, shown Table Table BR[1:0]# Signal Agent Sampled Active RESET# BR0# BR1# Agent
DEFER# signal asserted agent indicate that transaction cannot guaranteed inorder completion. Assertion DEFER# normally responsibility addressed memory agent. This signal must connect appropriate pins Pentium processor System agents.
A.1.18
DEP[7:0]# (I/O)
DEP[7:0]# (Data Protection) signals provide optional protection data bus. They driven agent responsible driving D[63:0]#, must connect appropriate pins Pentium processor System agents which them. DEP[7:0]# signals enabled disabled protection during power configuration.
A.1.19 A.1.14 BSEL# (I/O)
DRDY# (I/O)
BSEL# (Bus Select) signal used future Slot processors motherboards. This signal must tied proper processor operation.
DRDY# (Data Ready) signal asserted data driver each data transfer, indicating valid data data bus. multi-cycle data transfer, DRDY# deasserted insert idle clocks. This signal must connect appropriate pins Pentium processor System agents.
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
A.1.20
must connected with master's FRCERR input this configuration. point-to-point connections, checker always compares against master's outputs. bussed single-driver signals, checker compares against signal when master only allowed driver. bussed multiple-driver wired-OR signals, checker compares against signal only master expected drive signal low. When processor configured checker, FRCERR toggled during reset action. checker asserts FRCERR approximately second after active-to-inactive transition RESET# executes Built-In Self-Test (BIST). When BIST execution completes, checker processor deasserts FRCERR BIST completed successfully, continues assert FRCERR BIST fails. checker processor does execute BIST action, then keeps FRCERR asserted approximately clocks then deasserts asynchronous signals must externally synchronized BCLK system logic during mode operation.
pins should connected motherboard ground and/or chassis ground through zero resistors. zero resistors should placed close proximity Slot connector. path chassis ground should short length have impedance.
A.1.21
FERR#
FERR# (Floating-point Error) signal asserted when processor detects unmasked floatingpoint error. FERR# similar ERROR# signal Intel coprocessor, included compatibility with systems using MS-DOS*-type floating-point error reporting.
A.1.22
FLUSH#
When FLUSH# input signal asserted, processors write back data Modified state from their internal caches invalidate internal cache lines. completion this operation, processor issues Flush Acknowledge transaction. processor does cache data while FLUSH# signal remains asserted. FLUSH# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding Write transaction. active-to-inactive transition RESET#, each processor samples FLUSH# determine poweron configuration. Pentium® Processor Developer's Manual (Order Number 243341) details.
A.1.24
HIT# (I/O), HITM# (I/O)
HIT# (Snoop Hit) HITM# (Hit Modified) signals convey transaction snoop operation results, must connect appropriate pins Pentium processor System agents. such agent assert both HIT# HITM# together indicate that requires snoop stall, which continued reasserting HIT# HITM# together.
A.1.25 A.1.23 FRCERR (I/O)
IERR#
processors configured Functional Redundancy Checking (FRC) master/checker pair, single "logical" processor, FRCERR (Functional Redundancy Checking Error) signal asserted checker mismatch detected between internally sampled outputs master's outputs. checker's FRCERR output
IERR# (Internal Error) signal asserted processor result internal error. Assertion IERR# usually accompanied SHUTDOWN transaction Pentium processor System Bus. This transaction optionally converted external error signal (e.g., NMI) system core logic. processor will keep IERR# asserted until handled software, with assertion RESET#, BINIT#, INIT#.
A.1.26
PENTIUM® PROCESSOR MHZ, MHZ, MHZ,
APIC component. When APIC disabled, LINT0 signal becomes INTR, maskable interrupt request signal, LINT1 becomes NMI, nonmaskable interrupt. INTR backward compatible with signals those names Pentium processor. Both signals asynchronous. Both these signals must software configured BIOS programming APIC register space used either NMI/INTR LINT[1:0]. Because APIC enabled default after reset, operation these pins LINT[1:0] default configuration. During active RESET#, Pentium processor begins sampling A20M#, IGNNE#, LINT[1:0] values determine ratio core-clock frequency bus-clock frequency. (See Table activeto-inactive transition RESET#, Pentium processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation; Figure example implementation this logic.
IGNNE#
IGNNE# (Ignore Numeric Error) signal asserted force processor ignore numeric error continue execute noncontrol floatingpoint instructions. IGNNE# deasserted, processor generates exception noncontrol floating-point instruction previous floating-point instruction caused error. IGNNE# effect when control register set. IGNNE# asynchronous signal. However, ensure recognition this signal following writ
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