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EMBEDDED ULTRA-LOW POWER Intel486GX PROCESSOR 16-Bit External Dat


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Ultra-Low Power Member Intel486
EMBEDDED ULTRA-LOW POWER Intel486GX PROCESSOR
16-Bit External Data
Processor Family 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Cycles Data Parity Generation Checking Intel System Management Mode (SMM) Boundary Scan (JTAG)
176-Lead Thin Quad Flat Pack (TQFP) Separate Voltage Supply Core Circuitry Fast Core-Clock Restart Auto Clock Freeze Ideal Embedded Battery-Operated Hand-Held Applications
64-Bit Interunit Transfer
32-Bit Data 32-Bit Data Linear Address
Core Clocks
Clock Control
Interface
Barrel Shifter Register File
Base/ Index
Segmentation Unit
PCD,
Paging Unit
Cache Unit
Address Drivers Write Buffers Data Transceivers Control
A31-A2 BE3#-BE0#
Descriptor Registers Limit Attribute Translation Lookaside Buffer
Physical Address
Kbyte Cache
D15-D0
Displacement MicroInstruction
Prefetcher Request Sequencer Byte Code Queue Bytes Burst Control Data Parity Generation Control Cache Control Boundary Scan Control
ADS# W/R# D/C# M/IO# RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR SMI# SMIACT# STPCLK#
Control Protection Test Unit Control
Instruction Decode Decoded Instruction Path
Code Stream
BRDY# BLAST#
DP0, PCHK#
KEN# FLUSH# AHOLD EADS#
Figure Embedded Intel486GX Processor Block Diagram
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel. INTEL CORPORATION, 1995 September 1995 Order Number: 272755-001
Contents
EMBEDDED ULTRA-LOW POWER Intel486GX PROCESSOR
INTRODUCTION Features Family Members THIS DOCUMENT DESCRIPTIONS Assignments Quick Reference ARCHITECTURAL FUNCTIONAL OVERVIEW Separate Supply Voltages Fast Clock Restart Level-Keeper Circuits Low-Power Features 4.4.1 Auto Clock Freeze Interface Operation 4.5.1 16-Bit Data 4.5.2 Parity 4.5.3 Data Transfer Mechanism 4.5.3.1 Multiple Burst Cycle Transfers 4.5.3.2 Cacheable Cycles 4.5.3.3 Non-Cacheable Cycles 4.5.3.4 Burst Transfer Address Prediction CPUID Instruction 4.6.1 Operation CPUID Instruction Identification After Reset Boundary Scan (JTAG) 4.8.1 Device Identification 4.8.2 Boundary Scan Register Bits Order ELECTRICAL SPECIFICATIONS Maximum Ratings Specifications Specifications Capacitive Derating Curves MECHANICAL DATA Package Dimensions Package Thermal Specifications
FIGURES Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure TABLES Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Contents
Embedded Intel486GX Processor Block Diagram Package Diagram 176-Lead TQFP Package Embedded Intel486GX Processor Example Supply Voltage Power Sequence Stop Clock State Diagram with Typical Power Consumption Values Logic Generate BHE# BLE# Address Prediction Burst Transfers Address Prediction Burst Transfers Address Prediction Burst Transfers Waveform Input Setup Hold Timing Input Setup Hold Timing Output Valid Delay Timing PCHK# Valid Delay Timing Maximum Float Delay Timing Waveform Test Signal Timing Diagram Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-to-High Transition Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-to-Low Transition Package Mechanical Specifications Lead TQFP Package
Embedded Ultra-Low Power Intel486GX Processor Assignment 176-Lead TQFP Package Embedded Intel486GX Processor. Cross Reference 176-Lead TQFP Package Embedded Intel486GX Processor. Embedded Intel486GX Processor Descriptions Output Pins Input/Output Pins Test Pins Input Pins Valid Byte-Enable Cycles Address Sequence Cache Line Transfers Instruction Prefetches Valid Burst Cycle Sequences Reads Writes CPUID Instruction Description Boundary Scan Component Identification Code Absolute Maximum Ratings Operating Supply Voltages
Contents
Specifications Active Values Clock Stop, Stop Grant, Auto HALT Power Down Values Characteristics Specifications Test Access Port Thermal Resistance Maximum Ambient Temperature (TA)
Table Table Table Table Table Table Table
Contents
INTRODUCTION
Embedded Ultra-Low Power Intel486GX Processor
This data sheet describes embedded Ultra-Low Power (ULP) Intel486GX processor. intended embedded battery-operated hand-held applications. embedded Intel486 processor provides features Intel486 processor except 8-bit sizing logic processor-upgrade pin. processor typically uses less power than Intel486 processor. Additionally, embedded Intel486 processor external data parity signals have level-keeper circuitry fast-recovery core clock which vital ultra-low-power system designs. processor available Thin Quad Flat Package (TQFP) enabling low-profile component implementation. embedded Intel486 processor consists 32-bit integer processing unit, on-chip cache, memory management unit. design ensures full instruction-set compatibility with 8086, 8088, 80186, 80286, Intel386SX, Intel386 versions Intel486 processors.
On-Chip Cache with Cache Consistency Support 8-Kbyte, write-through, internal cache used both data instructions. Cache hits provide zero wait-state access times data within cache. activity tracked detect alterations memory represented internal cache. internal cache invalidated flushed that external cache controller maintain cache consistency. External Cache Control Write-back flush controls external cache provided processor maintain cache consistency. On-Chip Memory Management Unit Address management memory space protection mechanisms maintain integrity memory multitasking virtual memory environment. Both segmentation paging supported. Burst Cycles Burst transfers allow 16-bit data word read from memory each clock cycle. This capability especially useful instruction prefetch filling internal cache. Burst transfers also occur some memory write some data transfers. Write Buffers processor contains four write buffers enhance performance consecutive writes memory. processor continue internal operations after write these buffers, without waiting write completed external bus. Backoff When another master needs control during processor initiated cycle, embedded Intel486 processor floats signals, then restarts cycle when becomes available again. Instruction Restart Programs continue execution following exception generated unsuccessful attempt access memory. This feature important supporting demand-paged virtual memory applications. Boundary Scan (JTAG) Boundary Scan provides in-circuit testing components printed circuit boards. Intel Boundary Scan implementation conforms with IEEE Standard Test Access Port Boundary Scan Architecture.
Features
embedded Intel486 processor offers these features Intel486 processor: 32-bit RISC-Technology Core embedded Intel486 processor performs complete arithmetic logical operations 16-, 32-bit data types using full-width eight general purpose registers. Single Cycle Execution Many instructions execute single clock cycle. Instruction Pipelining Overlapped instruction fetching, decoding, address translation execution.
Embedded Ultra-Low Power Intel486GX Processor
Intel System Management Mode (SMM) unique Intel architecture operating mode provides dedicated special purpose interrupt address space that used implement intelligent power management other enhanced functions manner that completely transparent operating system applications software. Restart instruction interrupted System Management Interrupt (SMI#) automatically restarted following execution instruction. Stop Clock embedded Intel486 processor stop clock control mechanism that provides low-power states: Stop Grant state (40-85 typical, depending input clock frequency) Stop Clock state (~60 typical, with input clock frequency MHz). Auto HALT Power Down After execution HALT instruction, embedded Intel486 processor issues normal Halt cycle clock input processor core automatically stopped, causing processor enter Auto HALT Power Down state (40-85 typical, depending input clock frequency). embedded Intel486 processor differs from Intel486 processor following areas: 16-Bit External Data embedded Intel486 processor designed 16-bit embedded systems, internally provides 32bit architecture Intel486 processor family. data parity bits provided. Processor Upgrade Removed signal provided. Dynamic Bus-Sizing Removed BS8# signal provided.
Separate Processor-Core Power While embedded Intel486 processor requires supply voltage processor core dedicated pins operates with supply voltage Small, Low-Profile Package 176-Lead Thin Quad Flat Pack (TQFP) package approximately square only height. This approximately diameter thickness U.S. quarter. embedded Intel486 processor ideal embedded hand-held battery-powered applications. Level Keeper Circuits embedded Intel486 processor level-keeper circuits 16-bit external data parity signals. They retain valid high logic voltage levels when processor Stop Grant Stop Clock states. level-keeper circuits parity signals always enabled. This power-saving improvement from floating data Intel486 processor. Auto Clock Freeze embedded Intel486 processor monitors events internal activity. Auto Clock Freeze feature automatically controls internal clock distribution, turning clocks internal units when they idle. This power-saving function transparent embedded system. Fast Clock Restart embedded Intel486 processor requires only eight clock periods synchronize internal clock with input signal. This provides faster transition from Stop Clock State Normal State. 33-MHz operation, this synchronization time only compared with (PLL startup latency) Intel486 processor.
Family Members
Embedded Ultra-Low Power Intel486GX Processor
Table shows embedded Intel486 processor briefly describes characteristics.
Table Embedded Ultra-Low Power Intel486GX Processor Supply Voltage
(VCCP)
Product
Processor Core Supply Voltage
(VCC)
Processor Frequency
(MHz)
Package
FA80486GXSF-33
176-Lead TQFP
THIS DOCUMENT
DESCRIPTIONS Assignments
Even though 16-bit external data bus, embedded Intel486 processor characteristics similar 32-bit Intel486 processor. This document describes features embedded Intel486 processor. Some Intel486 processor information also included minimize dependence reference documents. complete documentation related embedded Intel486 processor, this document conjunction with following reference documents: Intel486Processor Family datasheet Order 242202 Intel486 Microprocessor Family Programmer's Reference Manual Order 240486 Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction Order 241618
following figures tables show assignments 176-pin Thin Quad Flat Pack (TQFP) package embedded Intel486 processor. Included are: Figure Package Diagram 176-Lead TQFP Package Embedded Intel486GX Processor (pg. Table Assignment 176-Lead TQFP Package Embedded Intel486GX Processor (pg. Table Cross Reference 176-Lead TQFP Package Embedded Intel486GX Processor (pg. Table Embedded Intel486GX Processor Descriptions (pg. Table Output Pins (pg. Table Input/Output Pins (pg. Table Test Pins (pg. Table Input Pins (pg. tables figures show "no-connects" "N/C." These pins should always remain unconnected. Connecting pins VCC, VCCP, VSS, other signal result component malfunction incompatibility with future steppings embedded Intel486 processor.
Embedded Ultra-Low Power Intel486GX Processor
Figure Package Diagram 176-Lead TQFP Package Embedded Intel486GX Processor
EADS# A20M# RESET FLUSH# INTR SRESET SMIACT# VCCP SMI# STPCLK# VCCP VCCP VCCP VCCP
BLAST# PLOCK# LOCK# VCCP PCHK# BRDY# BOFF# RDY# KEN# HOLD AHOLD HLDA W/R# VCCP BREQ BE0# BE1# BE2# BE3# M/IO# D/C# VCCP
ADS# VCCP VCCP RESERVED VCCP VCCP VCCP VCCP VCCP
176-Lead TQFP (top view)
VCCP VCCP VCCP VCCP VCCP
Embedded Ultra-Low Power Intel486GX Processor
Table Assignment 176-Lead TQFP Package Embedded Intel486GX Processor Description
BLAST# PLOCK# LOCK# VCCP PCHK# BRDY# BOFF# RDY# KEN# HOLD AHOLD HLDA W/R# VCCP BREQ BE0# BE1# BE2# BE3# M/IO# D/C# VCCP
Description
EADS# A20M# RESET FLUSH# INTR SRESET SMIACT# VCCP SMI# STPCLK# VCCP VCCP VCCP VCCP
Description
VCCP VCCP VCCP VCCP VCCP
Description
VCCP VCCP VCCP VCCP VCCP RESERVED VCCP VCCP ADS#
Embedded Ultra-Low Power Intel486GX Processor
Table Cross Reference 176-Lead TQFP Package Embedded Intel486GX Processor Address
Data
Control
A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ D/C# EADS# FLUSH# HLDA HOLD INTR KEN# LOCK# M/IO# PCHK# PLOCK# RDY# RESERVED RESET SMI# SMIACT# SRESET STPCLK# W/R#
VCCP
Quick Reference
Embedded Ultra-Low Power Intel486GX Processor
following brief description. detailed signal descriptions refer "Signal Description" section Intel486Processor Family datasheet. Table Embedded Intel486GX Processor Descriptions (Sheet Symbol Type Name Function Clock provides fundamental timing internal operating frequency embedded Intel486 processor. external timing parameters specified with respect rising edge CLK. Address Lines A31-A2, together with byte enable signals, BE3#-BE0#, define physical area memory input/output space accessed. Address lines A31-A4 used drive addresses into embedded Intel486 processor perform cache line invalidation. Input signals must meet setup hold times t23. A31-A2 driven during address hold. Byte Enable signals indicate active bytes during read write cycles. During first cycle cache fill, external system should assume that byte enables active. BE3#-BE0# active driven during hold. BE3# applies processor data bits D31-D24 BE2# applies processor data bits D23-D16 BE1# applies processor data bits D15-D8 BE0# applies processor data bits D7-D0 byte enables used external system generate address bits well byte-high (D15-D8) byte-low (D7-D0) enables. These needed interpret 16-bit external data bus. Data Lines. D7-D0 define least significant byte data bus; D15-D8 define most significant byte data bus. These signals must meet setup hold times proper operation reads. These pins driven during second subsequent clocks write cycles. There Data Parity each byte data bus. Data parity generated write data cycles with same timing data driven embedded Intel486 processor. Even parity information must driven back into processor data parity pins with same timing read information ensure that correct parity check status indicated processor. signals read these pins affect program execution. Input signals must meet setup hold times t23. must connected VCCP through pull-up resistor systems that parity. active HIGH driven during second subsequent clocks write cycles.
ADDRESS A31-A4 A3-A2
BE3# BE2# BE1# BE0#
DATA D15-D0
Embedded Ultra-Low Power Intel486GX Processor
Table Embedded Intel486GX Processor Descriptions (Sheet Symbol PCHK# Type Name Function Parity Status driven PCHK# clock after ready read operations. parity status data sampled previous clock. parity error indicated PCHK# being LOW. Parity status only checked enabled bytes indicated byte enable signals. PCHK# valid only clock immediately after read data returned processor. other times PCHK# inactive (HIGH). PCHK# never floated. Memory/Input-Output, Data/Control Write/Read lines primary definition signals. These signals driven valid ADS# signal asserted. M/IO# D/C# W/R# Cycle Initiated Interrupt Acknowledge HALT/Special Cycle (see details below) Read Write Code Read Reserved Memory Read Memory Write HALT/Special Cycle Cycle Name Shutdown HALT Stop Grant cycle LOCK# BE3# BE0# 1110 1011 1011 A4-A2
CYCLE DEFINITION M/IO# D/C# W/R#
Lock indicates that current cycle locked. embedded Intel486 processor does allow hold when LOCK# asserted (address holds allowed). LOCK# goes active first clock first locked cycle goes inactive after last clock last locked cycle. last locked cycle ends when Ready returned. LOCK# active driven during hold. Locked read cycles transformed into cache fill cycles when KEN# returned active. Pseudo-Lock indicates that current transaction requires more than cycle complete. embedded Intel486 processor, examples such operations segment table descriptor reads bits) cache line fills (128 bits). embedded Intel486 processor drives PLOCK# active until addresses last cycle transaction driven, regardless whether RDY# BRDY# have been returned. PLOCK# should sampled only clock which Ready returned. PLOCK# active driven during hold.
PLOCK#
CONTROL ADS# Address Status output indicates that valid cycle definition address available cycle definition lines address bus. ADS# driven active same clock which addresses driven. ADS# active driven during hold.
Symbol RDY# Type
Embedded Ultra-Low Power Intel486GX Processor
Table Embedded Intel486GX Processor Descriptions (Sheet Name Function Non-burst Ready input indicates that current cycle complete. RDY# indicates that external system presented valid data data pins response read that external system accepted data from embedded Intel486 processor response write. RDY# ignored when idle first clock cycle. RDY# active during address hold. Data returned embedded Intel486 processor while AHOLD active. RDY# active provided with internal pull-up resistor. RDY# must satisfy setup hold times proper chip operation. BURST CONTROL BRDY# Burst Ready input performs same function during burst cycle that RDY# performs during non-burst cycle. BRDY# indicates that external system presented valid data response read that external system accepted data response write. BRDY# ignored when idle first clock cycle. BRDY# sampled second subsequent clocks burst cycle. Data presented data strobed into embedded Intel486 processor when BRDY# sampled active. RDY# returned simultaneously with BRDY#, BRDY# ignored burst cycle prematurely aborted. BRDY# active provided with small pull-up resistor. BRDY# must satisfy setup hold times t17. BLAST# Burst Last signal indicates that next time BRDY# returned, burst cycle complete. BLAST# active both burst non-burst cycles. BLAST# active driven during hold. Reset input forces embedded Intel486 processor begin execution known state. processor cannot begin executing instructions until least after VCCP, have reached their proper specifications. RESET must remain active during this time ensure proper processor operation. However, warm resets, RESET should remain active least periods. RESET active HIGH. RESET asynchronous must meet setup hold times recognition specific clock. Maskable Interrupt indicates that external interrupt been generated. When internal interrupt flag EFLAGS, active interrupt processing initiated. embedded Intel486 processor generates locked interrupt acknowledge cycles response INTR going active. INTR must remain active until interrupt acknowledges have been performed ensure processor recognition interrupt. INTR active HIGH provided with internal pull-down resistor. INTR asynchronous, must meet setup hold times recognition specific clock.
INTERRUPTS RESET
INTR
Embedded Ultra-Low Power Intel486GX Processor
Table Embedded Intel486GX Processor Descriptions (Sheet Symbol Type Name Function Non-Maskable Interrupt request signal indicates that external non-maskable interrupt been generated. rising-edge sensitive must held least four periods before this rising edge. provided with internal pull-down resistor. asynchronous, must meet setup hold times recognition specific clock. Soft Reset duplicates functionality RESET except that SMBASE register retains previous value. soft resets, SRESET must remain active least periods. SRESET active HIGH. SRESET asynchronous must meet setup hold times recognition specific clock. System Management Interrupt input invokes System Management Mode (SMM). SMI# falling-edge triggered signal which forces embedded Intel486 processor into completion current instruction. SMI# recognized instruction boundary each iteration repeat string instructions. SMI# does break LOCKed cycles cannot interrupt currently executing SMM. embedded Intel486 processor latches falling edge pending SMI# signal while executing existing SMI#. nested SMI# recognized until after execution Resume (RSM) instruction. System Management Interrupt Active, active output, indicates that embedded Intel486 processor operating SMM. asserted when processor begins execute SMI# state save sequence remains active until processor executes last state restore cycle SMRAM. Stop Clock Request input signal indicates request made turn change input frequency. When embedded Intel486 processor recognizes STPCLK#, stops execution next instruction boundary (unless superseded higher priority interrupt), empties internal pipelines write buffers, generates Stop Grant cycle. STPCLK# active LOW. STPCLK# asynchronous signal, must remain active until embedded Intel486 processor issues Stop Grant cycle. STPCLK# de-asserted time after processor issued Stop Grant cycle. Request signal indicates that embedded Intel486 processor internally generated request. BREQ generated whether processor driving bus. BREQ active HIGH never floated. Hold Request allows another master complete control embedded Intel486 processor bus. response HOLD going active, processor floats most output input/output pins. HLDA asserted after completing current cycle, burst cycle sequence locked cycles. embedded Intel486 processor remains this state until HOLD de-asserted. HOLD active HIGH provided with internal pull-down resistor. HOLD must satisfy setup hold times proper operation.
SRESET
SMI#
SMIACT#
STPCLK#
ARBITRATION BREQ
HOLD
Symbol HLDA Type
Embedded Ultra-Low Power Intel486GX Processor
Table Embedded Intel486GX Processor Descriptions (Sheet Name Function Hold Acknowledge goes active response hold request presented HOLD pin. HLDA indicates that embedded Intel486 processor given another local master. HLDA driven active same clock that processor floats bus. HLDA driven inactive when leaving hold. HLDA active HIGH remains driven during hold. Backoff input forces embedded Intel486 processor float next clock. processor floats pins normally floated during hold HLDA asserted response BOFF#. BOFF# higher priority than RDY# BRDY#; both returned same clock, BOFF# takes effect. embedded Intel486 processor remains hold until BOFF# negated. cycle progress when BOFF# asserted cycle restarted. BOFF# active must meet setup hold times proper operation. Address Hold request allows another master access embedded Intel486 processor's address cache invalidation cycle. processor stops driving address clock following AHOLD going active. Only address floated during address hold, remainder remains active. AHOLD active HIGH provided with small internal pull-down resistor. proper operation, AHOLD must meet setup hold times t19. External Address This signal indicates that valid external address been driven onto embedded Intel486 processor address pins. This address used perform internal cache invalidation cycle. EADS# active provided with internal pull-up resistor. EADS# must satisfy setup hold times proper operation. Cache Enable used determine whether current cycle cacheable. When embedded Intel486 processor generates cycle that cached KEN# active clock before RDY# BRDY# during first transfer cycle, cycle becomes cache line fill cycle. Returning KEN# active clock before RDY# during last read cache line fill causes line placed on-chip cache. KEN# active provided with small internal pull-up resistor. KEN# must satisfy setup hold times proper operation. Cache Flush input forces embedded Intel486 processor flush entire internal cache. FLUSH# active need only asserted clock. FLUSH# asynchronous setup hold times must recognition specific clock.
BOFF#
CACHE INVALIDATION AHOLD
EADS#
CACHE CONTROL KEN#
FLUSH#
Embedded Ultra-Low Power Intel486GX Processor
Table Embedded Intel486GX Processor Descriptions (Sheet Symbol Type Name Function Page Write-Through Page Cache Disable pins reflect state page attribute bits, PCD, page table entry, page directory entry control register (CR3) when paging enabled. When paging disabled, embedded Intel486 processor ignores bits assumes they zero purpose caching driving pins. have same timing cycle definition pins (M/IO#, D/C#, W/R#). active HIGH driven during hold. masked cache disable (CD) Control Register Address Mask pin, when asserted, causes embedded Intel486 processor mask physical address (A20) before performing lookup internal cache driving memory cycle bus. A20M# emulates address wraparound Mbyte, which occurs 8086 processor. A20M# active should asserted only when embedded Intel486 processor real mode. This asynchronous should meet setup hold times recognition specific clock. proper operation, A20M# should sampled HIGH falling edge RESET. Test Clock, input embedded Intel486 processor, provides clocking function required JTAG Boundary scan feature. used clock state information (via TMS) data (via TDI) into component rising edge TCK. Data clocked component (via TDO) falling edge TCK. provided with internal pull-up resistor. Test Data Input serial input used shift JTAG instructions data into processor. sampled rising edge TCK, during SHIFT-IR SHIFT-DR controller states. During other Test Access Port (TAP) controller states, "don't care." provided with internal pull-up resistor. Test Data Output serial output used shift JTAG instructions data component. driven falling edge during SHIFT-IR SHIFT-DR controller states. other times driven high impedance state. Test Mode Select decoded JTAG select test logic operation. sampled rising edge TCK. guarantee deterministic behavior controller, provided with internal pull-up resistor. Reserved reserved future use. This MUST connected external pull-up resistor circuit. recommended resistor value kOhms.
PAGE CACHEABILITY
ADDRESS MASK A20M#
TEST ACCESS PORT
RESERVED PINS RESERVED
Name BREQ HLDA BE3#-BE0# PWT, W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# PCHK# A3-A2 SMIACT# Active Level HIGH HIGH HIGH HIGH/LOW HIGH
Embedded Ultra-Low Power Intel486GX Processor
Table Output Pins Output Signal Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States1 Previous State HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State Previous State
NOTE: term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Input/Output Pins Output Signal Name D15-D0 DP1, A31-A4 Active Level HIGH HIGH HIGH Floated During Address Hold Floated During Hold During Stop Grant Stop Clock States1,2 Level-Keeper Level-Keeper Previous State
NOTES: term "Level-Keeper" means that processor maintains most recent logic level applied signal pin. This conserves power preventing signal from floating. system component, other than processor, temporarily drives these signal pins then floats them, processor forces maintains most recent logic levels that were applied system component. level keepers always enabled. term "Previous State" means that processor maintains logic level applied signal just before processor entered Stop Grant state. This conserves power preventing signal from floating.
Table Test Pins Name Input Output Input Input Output Input Sampled/ Driven Rising Edge Failing Edge Rising Edge
Embedded Ultra-Low Power Intel486GX Processor
Synchronous/ Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Internal Pull-Up/ Pull-Down
Table Input Pins Name RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# KEN# RDY# BRDY# INTR RESERVED SMI# STPCLK# HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Active Level
ARCHITECTURAL FUNCTIONAL OVERVIEW
Testability Debugging Support Instruction Summary Differences Between Intel486 Processors Intel386Processors Exceptions these sections datasheet are: embedded Intel486 processor 16-bit external data data parity signals. While four byte-enable signals (BE3#-BE0#), external system must generate address bits well enables each byte 16-bit external data bus. More information about byte enables provided this datasheet. information pertaining dynamic sizing external data does apply. embedded Intel486 processor does have BS8# signal pin.
embedded Intel486 processor architecture essentially same Intel486 processor with clock (CLK) input. Refer Intel486Processor Family datasheet (242202) description Intel486 processor. With some minor exceptions, following datasheet sections apply embedded Intel486 processor: Architectural Overview Real Mode Architecture Protected Mode Architecture On-Chip Cache System Management Mode (SMM) Architectures Hardware Interface Operation
Embedded Ultra-Low Power Intel486GX Processor
embedded Intel486 processor bursts data cycles similar Intel486 processor with bus-sizing BS16# active. References Upgrade Power Down Mode apply. embedded Intel486 processor does have signal does support Intel OverDrive® processor. References "VCC" called "VCCP" embedded Intel486 processor when supply voltage pertains processor's external interface drivers receivers. term "VCC pertains only processor core supply voltage embedded Intel486 processor. Information about split-supply voltage provided this datasheet. Phase-Locked Loop (PLL) circuit clock (CLK) input been replaced proprietary Differential Delay Line (DDL) circuit that faster recovery time. Datasheet references recovery time replaced with circuit eight-CLK recovery time. Information about circuit recovery time provided this datasheet. embedded Intel486 processor level-keeper circuits external 16-bit data (D15-D0) data parity (DP1, DP0) signals. Intel486 processor floats these signals instead. More information about level-keeper circuitry provided this datasheet. datasheet describes processor supplycurrent consumption Auto HALT Power Down, Stop Grant, Stop Clock states. This supply-current consumption embedded Intel486 processor much less than that Intel486 processor. Information about power consumption these states provided this datasheet. Boundary-Scan (JTAG) boundary-scan register bits embedded Intel486 processor this datasheet. embedded Intel486 processor reserved possible future use. This input signal, 166. called RESERVED must connected 10-K pull-up resistor.
Separate Supply Voltages
embedded Intel486 processor separate voltage-supply planes internal coreprocessor circuits external driver/receiver circuits. supply voltage internal core processor named supply voltage external circuits named VCCP. single-supply voltage design, embedded Intel486 processor functional this type system design, processor's VCCP pins must tied same power plane. Even though VCCP must processor's external-output circuits drive TTLcompatible components. However, processor's external-input circuits allow connection TTL-compatible components. Section 5.2, Specifications (pg. contains specifications processor's input output signals. lower-power operation, separate, lower voltage chosen, VCCP must voltage value between chosen guaranteed processor operation MHz. embedded Intel486 processor also operate MHz, provided value chosen between Section 5.2, Specifications (pg. defines supply voltage specifications. systems with separate VCCP power planes, processor-core voltage supply must always less than equal processor's external-interface voltage supply; e.g., system design must guarantee: Violating this relationship causes excessive power consumption. Limited testing shown component damage when this relationship violated. However, prolonged violation recommended component integrity guaranteed. VCCP relationship must also guaranteed system design during power-up power-down sequences. Refer Figure Even though must less than equal VCCP, recommended that system's power-on sequence allows quickly achieve opera-
Embedded Ultra-Low Power Intel486GX Processor
tional level once VCCP achieves operational level. Similarly, power-down sequence should allow VCCP power down quickly after below operational voltage level. These recommendations given keep power consumption minimum.
Deviating from recommendations does create component reliability problem, power consumption processor's external interface circuits increases beyond normal operating values.
VCCP
VCCP
VCCP
TIME
POWER POWER
Figure Example Supply Voltage Power Sequence
Fast Clock Restart
embedded Intel486 processor integrated proprietary differential delay line (DDL) circuit internal clock generation. driven input signal provided external system. During normal operation, external system must guarantee that signal maintains frequency that clock period deviates more than ps/CLK. This state, called Normal State, shown Figure increase decrease frequency more quickly than this, system must interrupt processor with STPCLK# signal. Once processor indicates that Stop Grant State, system adjust signal frequency, wait minimum eight periods, then force processor return normal operational state deactivating STPCLK# interrupt.
This wait eight periods much faster than wait required earlier Intel486 processor products. While Stop Grant State, external system deactivate signal processor. This forces processor Stop Clock State state which processor consumes least power. Once system reactivates signal, processor transitions Stop Grant State within eight periods. Normal operation resumed deactivating STPCLK# interrupt signal. Here again, embedded Intel486 processor recovers from Stop Clock State much faster than recovery earlier Intel486 processors.
Auto HALT Power Down State
Running mWatts
Embedded Ultra-Low Power Intel486GX Processor
HALT asserted HALT cycle generated
Normal State
Normal Execution
INTR, NMI, SMI# RESET, SRESET STPCLK# asserted Stop Grant cycle generated
EADS# STPCLK# deasserted HALT cycle generated STPCLK# asserted Stop Grant cycle generated
STPCLK# deasserted
EADS#
Stop Grant State
Running mWatts
Stop Clock Snoop State
Clock PowerUp Perform Cache Invalidation
Stop
Start plus Startup Latency
Stop Clock State
Internal Powerdown Stopped µWatts
Figure Stop Clock State Diagram with Typical Power Consumption Values
Level-Keeper Circuits
obtain lowest possible power consumption during Stop Grant Stop Clock states, system designers must ensure that: input signals with pull-up resistors driven input signals with pull-down resistors driven HIGH Table Input Pins (pg. list signals with internal pull-up pull-down resistors. other input pins except A31-A4, D15-D0, DP1, must driven power supply rails ensure lowest possible current consumption.
During Stop Grant Stop Clock states, most processor output signals maintain their previous condition, which level they held when entering Stop Grant state. response HOLD driven active during Stop Grant state when input running, embedded Intel486 processor generates HLDA floats output input/output signals which floated during HOLD/HLDA state. When HOLD deasserted, processor signals which maintain their previous state return state they were prior HOLD/HLDA sequence. data (D15-D0) parity bits also maintain their previous states during Stop Grant Stop Clock states, differently, described following paragraphs.
Embedded Ultra-Low Power Intel486GX Processor
Low-Power Features
embedded Intel486 processor's data pins (D15-D0) data parity pins have level keepers which maintain their previous states while Stop Grant Stop Clock states. response HOLD driven active during Stop Grant state when input running, embedded Intel486 processor generates HLDA floats D15-D0, throughout HOLD/HLDA cycles. When HOLD deasserted, processor's D15-D0, signals return states they were prior HOLD/HLDA sequence. other times during Stop Grant Stop Clock states, processor maintains logic levels D15-D0, DP0. When external system circuitry drives D15-D0, different logic levels, processor flips D15-D0, logic levels match ones driven external system. processor maintains (keeps) these levels even after external circuitry stops driving D15-D0, DP0. some system designs, external resistors required D15-D0, (they required previous Intel486 processor designs). System designs that never request Hold during Stop Grant Stop Clock states might require external resistors. system design uses Hold during these states, processor disables level-keepers floats data bus. This type design would require some kind data termination minimize power consumption. strongly recommended that D15-D0, pins have network resistors connected. External resistors used system design must sufficient resistance value "flip" level-keeper circuitry eliminate potential paths. level-keeper circuits always enabled, while level-keeper circuits D15-D0 enabled only during Stop Grant Stop Clock states. level-keeper circuit designed allow external 27-K pull-up resistor switch D15-D0, circuits logic-HIGH level even though level-keeper attempts keep logicLOW level. general, pull-up resistors smaller than used well those greater than equal Pull-down resistors, when connected D15-D0, DP0, should least
with other Intel486 processors, embedded Intel486 processor minimizes power consumption providing Auto HALT Power Down, Stop Grant, Stop Clock states (see Figure embedded Intel486 processor Auto Clock Freeze feature that further conserves power judiciously deactivating internal clocks while Normal Execution Mode. power-conserving mechanism designed such that does degrade processor performance require changes timing specifications. 4.4.1 Auto Clock Freeze
reduce power consumption, during following cycles under certain conditions processor slows-up freezes some internal clocks: Data-Read Wait Cycles (Memory, Interrupt Acknowledge) Data-Write Wait Cycles (Memory, I/O) HOLD/HLDA Cycles AHOLD Cycles BOFF Cycles Power conserved during wait periods these cycles until appropriate external-system signals sent processor. These signals include: READY NMI, SMI#, INTR, RESET BOFF# FLUSH# EADS# KEN# transitions embedded Intel486 processor also reduces power consumption temporarily freezing clocks internal logic blocks. When logic block idle wait state, clock frozen.
4.5.1
Embedded Ultra-Low Power Intel486GX Processor
Interface Operation
16-Bit Data
must meet setup hold times, t23. systems using parity, must connected VCCP through pull-up resistor. data parity pins have level-keeper circuits which described later. 4.5.3 Data Transfer Mechanism
bi-directional lines, D15-D0, form data embedded Intel486 processor. D7D0 define least-significant byte D15-D8 most-significant byte. Data transfers possible only 16-bit devices. Bus-sizing 8-bit devices (BS8# signal pin) supported processor. some cases, external circuitry needed processor interface with 8-bit devices. example when external circuitry needed 8-bit port that mapped byte address. Here only part 16-bit data word meant device BS8# needed. D15-D0 active HIGH. reads, D15-D0 must meet setup hold times, t23. D15-D0 driven during read cycles hold. 4.5.2 Parity
Parity operation same rest Intel486 processor family, with these exceptions: data parity pins processor. There parity signal each byte external data bus. Input signals
Data transfers operate manner similar data transfers 32-bit data members Intel486 processor family with BS16# driven active. 32-bit data-bus family members, such 16bit data transfers involve bits their external data busses four parity bits. Since embedded Intel486 processor 16-bit external data bus, data transfers occur order data bits, through D15. Parity generated checked DP1. Dynamic Data Sizing (BS16#, BS8#) supported. address bits (A31-A2) byte enables (BE0#, BE1#, BE2#, BE3#) supported. Address bits generated from byte-enable signals same manner other Intel486 processors. Typically 16-bit data designs, byte-low enable (BLE), byte-high enable (BHE) needed generated from four byteenable signals. Figure shows logic that used generate BHE#, BLE#.
BE0# BE1#
BE1# BE3#
BHE#
BE0# BE2# BLE#
BE0#
BE1#
Figure Logic Generate BHE# BLE#
Embedded Ultra-Low Power Intel486GX Processor
Table contains list valid byte-enable combinations 16-bit external data interpreted. Table Valid Byte-Enable Cycles Byte Enables Case BE3# BE2# BE1# BE0# From External Circuitry (Note BHE# External Data D7-D0, valid valid valid valid valid valid
BLE# D15(A0) valid valid valid valid valid valid valid valid
NOTE: external system indicates processor that read cacheable, processor initiates cacheline fill. this case, external system should ignore BE3#, BE2#, BE1#, BE0# force BHE# logic level first cycle transfer. This forces memory read start from data address having least significant digit (hex). byte-enable decodes subsequent cycles line fill follow table information listed.
Except initial transfer cache-line fill, Byte Enables BE3#, BE2#, BE1#, BE0# cases indicate either one-, two-byte data transfer that accomplished 16-bit data cycle. Except initial transfer cache-line fill, Byte Enables BE3#, BE2#, BE1#, BE0# cases indicate transfer two, three, four data bytes that cannot accomplished 16-bit data cycle. these cases, processor attempts complete partial transfer using additional data cycle. additional cycle could burst processor (processor could respond with BLAST# unasserted case This true both memory reads writes. There more information about bursting later sections. During write cycles, valid data only driven onto external data pins corresponding active byte enables. Other pins data driven contain valid data.
NOTE:
Unlike Intel386processor, embedded Intel486 processor does duplicate write data onto parts data which corresponding byte enable inactive.
4.5.3.1 Multiple Burst Cycle Transfers embedded Intel486 processor, like other Intel486 processors, requires more than data cycle read write data having widths greater than Examples this data cache lines (128 bits) instruction prefetches (128 bits). addition, embedded Intel486 processor requires multiple data cycles transfer data having widths greater than example doubleword operand bits). Transferring misaligned 16-bit words also requires multiple data cycles.
Embedded Ultra-Low Power Intel486GX Processor
multiple data cycle memory-read I/O-read data transfer, processor could burst cycles perform transfer. processor could also burst misaligned 16-bit 32-bit memory-write I/Owrite data transfers. designing memory port controller embedded Intel486 processor, knowledge address sequence burst cycles used provide high-speed data access (minimal number wait states). following sections describe this sequence.
4.5.3.2 Cacheable Cycles embedded Intel486 processor uses burst cycles perform cache line fill. Because 16-bit external data bus, processor bursts eight data cycles read 128-bit (16-byte) cache line from system memory. During first cycle cache line transfer, external system must ignore BE3#, BE2#, BE1#, BE0# presented processor proceed BHE# were logic-low levels (0). This forces memory read start from data address having least significant hexadecimal digit byte enables presented processor subsequent cycles decoded usual external system. sequences data addresses shown Table Like rest Intel486 processor family, initial value A31-A4, M/IO#, W/R#, D/C# presented processor throughout cache line fill. Also, burst sequence terminated processor time with active BLAST# signal.
Embedded Ultra-Low Power Intel486GX Processor
Address Expected Read Data D15-D8, D7-D-0,
Table Address Sequence Cache Line Transfers Instruction Prefetches Starting Address (Least significant hexadecimal digit) Signals from Processor Data Cycle Byte Enables BE3#-BE0# A3-A0 (Hex) BLAST#
Embedded Ultra-Low Power Intel486GX Processor
Whenever cache circuitry busy, processor uses this same bursting mechanism prefetching instructions (128 bits, bytes), even instructions indicated cacheable external system. Instruction prefetches occur that address sequencing shown Table initial value A31-A4, M/IO#, W/R#, D/C# presented processor throughout 128bit prefetch burst. possible processor prefetch instructions needed. burst sequence terminated processor time with active BLAST# signal. 4.5.3.3 Non-Cacheable Cycles memory data transfers, embedded Intel486 processor determines many data cycles required transfer based internal information. This information includes byte-length data, transfer's starting data address, data alignment. memory reads, processor resorts 128-bit cache-line address sequence described above external system
indicates data cacheable. Otherwise, processor uses internal information determine whether burst data cycles multiple-cycle transfer. some cases, transfer performed entirely burst cycles. other cases, combination burst cycles single cycles required perform data transfer. There also cases which burst cycles cannot used transfer consists multiple cycles, each beginning with ADS# signal. Writes, Reads, Memory Writes processor initiates bursting (BLAST# inactive) during Write, Read Memory Write, duration burst maximum four bytes bits). possible burst situations listed Table cases, burst data cycles. control signals M/IO#, D/C#, W/R#, address bits A31-A4 well remain constant throughout each two-cycle burst.
Table Valid Burst Cycle Sequences Reads Writes Starting Address (Least significant hexadecimal digit) Data Cycle Signals from Processor Byte Enables BE3#-BE0# A3-A0 (Hex) BLAST# Address Expected Read Data D15-D8, D7-D-0,
Embedded Ultra-Low Power Intel486GX Processor
Non-Cacheable Memory Reads When processor initiates bursting, duration burst maximum bytes (128 bits). Non-cacheable instruction prefetches bytes duration. possible burst sequences same cache-line transfers listed Table burst sequence terminated time with active BLAST# signal. length burst transfer eight, fewer than eight bytes. burst lengths eight less, entire burst transfer confined quad-word (eight-byte) data boundary system memory. A31-A3 remain constant throughout this type burst transfer.
4.5.3.4 Burst Transfer Address Prediction processor provides data address (A31-A2) byte enables (BE3#-BE0#) first data cycle while ADS# inactive. initial values BHE# BLE# (A0) derived from byte enables. bursting anticipated, next data address predicted this time used memory controller perform burst data transfers with minimal wait states. Rather than list burst mode address combinations, general algorithm provided Figure This algorithm holds true burst transfers including cache-line fills, instruction prefetches, memory-write data transfers described earlier sections.
Embedded Ultra-Low Power Intel486GX Processor
Begin when ADS# active
Define initial values
Cacheable?
Indicate "cacheable data" processor
BE3# BE0# xx11?
Data Cycle First Transfer MA3=LA3 MA2=LA2 MA1=0 Next Transfer (After processor returns BLAST#=1) MA3=LA3 MA2=LA2 MA1=1 Data Cycle First Transfer MA3=LA3 MA2=LA2 MA1=1 Next Transfer (After processor returns BLAST#=1) MA3=LA3 MA2=Not [LA2] MA1=0
BLAST#
BLAST#
Data Cycle Next Transfer MA3=LA3 MA2=Not [LA2] MA1=0
BLAST#
Continued
Figure Address Prediction Burst Transfers
Embedded Ultra-Low Power Intel486GX Processor
Continued from previous figure
Data Cycle Next Transfer MA3=LA3 MA2=Not [LA2] MA1=1
BLAST#
Data Cycle Next Transfer MA3=Not [LA3] MA2=LA2 MA1=0
BLAST#
Data Cycle Next Transfer MA3=Not [LA3] MA2=LA2 MA1=1
BLAST#
Data Cycle Next Transfer MA3=Not [LA3] MA2=Not [LA2] MA1=0
BLAST#
Continued
Figure Address Prediction Burst Transfers
Embedded Ultra-Low Power Intel486GX Processor
Continued from previous figure
Data Cycle Next Transfer MA3=Not [LA3] MA2=Not [LA2] MA1=1
BLAST#
Data Cycle This last transfer. There need predict next address
Figure Address Prediction Burst Transfers figure, MA3, MA2, memory address bits. saved, initial values respectively. term "MA2 [LA2]" means that opposite logic state saved initial value. MA31-MA4 derived directly from A31-A4, which remain constant throughout burst transfer. M/IO#, W/R#, D/C# also remain constant. BLE# (A0) shown, always active (LOW) throughout transfer. BHE#, also shown, cannot predicted last data cycle burst transfer must decoded from byte enable bits last burst cycle (follows BLAST# Otherwise BHE# always active (LOW) throughout burst. processor defines "cacheable data" case where inactive (LOW) LOCK# inactive (HIGH) KEN# active (LOW). change value this flag, CPUID instruction available. actual state Flag irrelevant provides significance hardware. This cleared (reset zero) upon device reset (RESET SRESET) compatibility with Intel486 processor designs that support CPUID instruction. CPUID-instruction details provided here embedded Intel486 processor. Refer Intel Application Note AP-485 Intel Processor Identification with CPUID Instruction (Order 241618) description that covers aspects CPUID instruction pertains other Intel processors. 4.6.1 Operation CPUID Instruction
CPUID Instruction
embedded Intel486 processor supports CPUID instruction (see Table 12). Because Intel processors support CPUID instruction, simple test determine instruction supported. test involves processor's Flag, which EFLAGS register. software
CPUID instruction requires software developer pass input parameter processor register. processor response returned registers EAX, EBX, EDX, ECX.
Embedded Ultra-Low Power Intel486GX Processor
Description Vendor (Intel) String Processor Identification Undefined Use)
Table CPUID Instruction Description CODE Instruction CPUID Processor Core Clocks Parameter passed
(Input Value)
Vendor String When parameter passed (zero), register values returned upon instruction execution shown following table. 31-24 High Value Vendor String (ASCII Characters) (75) (49) (6C) 23-16 (6E) (65) (65) 15-8 (65) (6E) (74) (47) (69) (6E)
values EBX, indicate Intel processor. When taken proper order, they decode string "GenuineIntel." Processor Identification When parameter passed (one), register values returned upon instruction execution are: 31-14 13,12 11-8 Processor Signature Use) Intel Reserved Processor Type 0100 Family 0010 Model XXXX Stepping
(Intel releases information about stepping numbers needed) 31-0 Intel Reserved Use) Intel Reserved Intel Reserved 31-2 Feature Flags
Identification After Reset
XXXX Stepping
Processor Identification Upon reset, register contains processor signature: 31-14 13,12 11-8 Processor Signature Use) Intel Reserved Processor Type 0100 Family 0010 Model
(Intel releases information about stepping numbers needed)
4.8.1
Embedded Ultra-Low Power Intel486GX Processor
Boundary Scan (JTAG)
Device Identification
Table shows 32-bit code embedded Intel486 processor which loaded into Device Identification Register. Table Boundary Scan Component Identification Code Version
0=5V 1=3.3
Part Number Intel Architecture Type Family 0100 Intel486 Family Model 00100 embedded Intel486 processor 16-12 00100
009H Intel
31-28 XXXX
26-21 000001
20-17 0100
11-1 00000001001
(Intel releases information about version numbers needed) Boundary Scan Component Identification Code x828 4013 (Hex) 4.8.2 Boundary Scan Register Bits Order floated pins three-state, selected input they bidirectional. WRCTL controls D15-D0, ABUSCTL controls A31-A2 BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, D/C#, PWT, MISCCTL controls PCHK#, HLDA, BREQ following order embedded Intel486 processor boundary scan register:
boundary scan register contains cell each well cells control bidirectional three-state pins. There "Reserved" bits which correspond no-connect (N/C) signals embedded Intel486 processor. Control registers WRCTL, ABUSCTL, BUSCTL, MISCCTL used select direction bidirectional three-state output signal pins. these cells designates that associated bits
RESERVED, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, DP1, D10, D11, D12, D13, D14, D15, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, Reserved, Reserved, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL
Embedded Ultra-Low Power Intel486GX Processor
Table Absolute Maximum Ratings +110 +150 -0.5 VCCP -0.5 +4.6 -0.5 +4.6
ELECTRICAL SPECIFICATIONS Maximum Ratings
Case Temperature under Bias Storage Temperature
Table stress rating only. Extended exposure Maximum Ratings affect device reliability. Furthermore, although embedded Intel486 processor contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields. Functional operating conditions given Section 5.2, Specifications Section 5.3, Specifications.
Voltage with Respect Ground Supply Voltage with Respect Supply Voltage VCCP with Respect
Specifications
following tables show operating supply voltages, specifications, component power consumption embedded Intel486 processor.
Table Operating Supply Voltages Product VCCP Range1 Max. Frequency Range2 ±0.2 +0.3 V/-0.2 ±0.3 Fluctuation
FA80486GXSF-33
NOTES: cases, VCCP must VCC. voltage within Range. setting determines allowed Fluctuation.
Embedded Ultra-Low Power Intel486GX Processor
Table Specifications TCASE=0 Symbol Parameter Input Voltage Input HIGH Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage -2.0 -100 COUT CCLK Input Leakage Current Input Leakage Current Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Capacitance VCCP -0.2 -400 Note Note Note Note Note Note Min. -0.3 VCCP -0.6 Max. +0.8 VCCP +0.3 VCCP +0.3 Unit Note Notes
NOTES: inputs except CLK. This parameter inputs without pull-up pull-down resistors VCCP. This parameter inputs with pull-down resistors 2.4V, level-keeper pins V=0.4V. This parameter inputs with pull-up resistors 0.4V, level-keeper pins V=2.4V. FC=1 MHz. 100% tested.
Embedded Ultra-Low Power Intel486GX Processor
Table Active Values TCASE=0 Symbol Parameter Frequency ICC1 Active (VCC pins) ICC2 Active pins)
NOTE: These parameters
Supply Voltage VCCP VCCP VCCP VCCP
Typical
Max.
Notes
Embedded Ultra-Low Power Intel486GX Processor
Table Clock Stop, Stop Grant, Auto HALT Power Down Values TCASE= Symbol Parameter Frequency Supply Voltage ICCS0 Stop Clock (VCC pins) ICCS2 Stop Clock (VCCP pins) Stop Grant, ICCS1 Auto HALT Power Down (VCC pins) Stop Grant, Auto HALT Power Down (VCCP pins) VCCP VCCP VCCP VCCP VCCP Typical Max. Note Notes
ICCS3
NOTE: Stop Clock specification refers value once processor enters Stop Clock state. input signals, levels must equal VCCP respectively, meet Stop Clock specifications.
Embedded Ultra-Low Power Intel486GX Processor
Specifications
specifications embedded Intel486 processor given this section. Table Characteristics (Sheet valid over operating supply voltages listed Table Operating Supply Voltages (pg. 30). TCASE=
Symbol Parameter Frequency
2.0V 2.2V 2.2V 2.4V 2.4V 2.7V 2.7V 3.3V
62.5
Unit
Notes Note Note Note 0.8V 0.8V Note 0.8V Note
Period Period Stability High Time Time Fall Time Rise Time A2-A31, PWT, PCD, BE0#-BE3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT# Valid Delay A2-A31, PWT, PCD, BE0#-BE3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay BLAST#, PLOCK# Float Delay D0-D15, DP0, Write Delay D0-D15, DP0, Float Delay EADS# Setup Time EADS# Hold Time KEN# Setup Time KEN# Hold Time RDY#, BRDY# Setup Time RDY#, BRDY# Hold Time HOLD, AHOLD Setup Time
ps/CLK
Note
Note Note
2.0V 2.2V
Embedded Ultra-Low Power Intel486GX Processor
Table Characteristics (Sheet valid over operating supply voltages listed Table Operating Supply Voltages (pg. 30). TCASE=
Symbol Parameter BOFF# Setup Time HOLD, AHOLD, BOFF# Hold Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Hold Time D0-D15, DP0, DP1, A4A31 Read Setup Time D0-D15, DP0, DP1, A4A31 Read Hold Time
2.2V 2.4V 2.4V 2.7V 2.7V 3.3V
Unit
Notes
t18a
NOTES: operation tested guaranteed STPCLK# Stop Grant cycle protocol. operation confirmed design characterization, 100% tested production. Specification available only when frequency changed without STPCLK# STOP GRANT cycle protocol. 100% tested, guaranteed design characterization. reference voltage timing measurement except through Other signals measured
Embedded Ultra-Low Power Intel486GX Processor
Table Specifications Test Access Port Symbol Parameter Frequency Period High Time Time Rise Time Fall Time TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Outputs (except TDO) Valid Delay Outputs (except TDO) Float Delay Inputs (except TDI, TMS, TCK) Setup Time Inputs (except TDI, TMS, TCK) Hold Time Unit Figure Note 2.0V @0.8V Note Note Note Note Note Notes Note Notes Note Note Notes
NOTES: period period. Rise/Fall Times measured between Rise/Fall times relaxed increase period. Parameter measured from TCK. 100% tested, guaranteed design characterization.
Embedded Ultra-Low Power Intel486GX Processor
input setup times input hold times, output float, valid hold times Figure Waveform
EADS#
KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A4-A31 (READ)
Figure Input Setup Hold Timing
Embedded Ultra-Low Power Intel486GX Processor
RDY#, BRDY#
D15-D0, DP0,
Figure Input Setup Hold Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID
VALID
D15-D0, DP0,
VALID
VALID
BLAST#, PLOCK#
VALID
VALID
Figure Output Valid Delay Timing
Embedded Ultra-Low Power Intel486GX Processor
RDY#, BRDY#
D0-D15 DP0,
VALID
PCHK#
VALID
Figure PCHK# Valid Delay Timing
A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ
VALID
D15-D0, DP0,
VALID
BLAST#, PLOCK#
VALID
Figure Maximum Float Delay Timing
Embedded Ultra-Low Power Intel486GX Processor
Figure Waveform
OUTPUT INPUT VALID VALID VALID VALID VALID
Figure Test Signal Timing Diagram
Capacitive Derating Curves
nom+7 nom+6 nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom-1 nom-2
Embedded Ultra-Low Power Intel486GX Processor
following graphs capacitive derating curves embedded Intel486 processor.
Capacitive Load (pF) NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table. Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions Low-toHigh Transition
nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom-1 nom-2 Capacitive Load (pF)
NOTE: This graph will linear outside capacitive range shown. nominal value from Characteristics table. Figure Typical Loading Delay versus Load Capacitance under Worst-Case Conditions High-toLow Transition
Embedded Ultra-Low Power Intel486GX Processor
MECHANICAL
This section describes packaging dimensions thermal specifications embedded Intel486 processor.
Package Dimensions
26.0 0.40 24.0 0.10
0.10 0.10
0.60 0.20
0.50 0.10
0.10 0.10 1.50 0.20
0.16 0.28
Note* Height Measurements same Width Measurements
Units:
Figure Package Mechanical Specifications Lead TQFP Package
Embedded Ultra-Low Power Intel486GX Processor
Package Thermal Specifications
embedded Intel486 processor specified operation when case temperature (TC) within range 85°C. measured environment determine whether processor within specified operating range. ambient temperature (TA) calculated from from following equations:
Where equals Junction, Ambient Case Temperature respectively. equals Junction-to-Case Junction-to-Ambient thermal Resistance, respectively. Maximum Power Consumption defined (typ) (max) [VCC (typ) ICC1 (max)] [VCCP (typ) ICC2(max)] where: ICC1 supply current ICC2 VCCP supply current Values given following tables each product maximum operating frequencies.
Table Thermal Resistance (°C/W) 176-Lead TQFP Package (°C/W) (°C/W) with airflow 33.6
following table shows maximum ambient temperatures embedded Intel486 processor each product maximum operating frequencies. These temperatures calculated using ICC1 ICC2 values measured during component-validation testing using VCCP=3.6 worst-case values. Table Maximum Ambient Temperature (TA) 176-Lead TQFP Package Frequency (°C) with airflow
Embedded Ultra-Low Power Intel486GX Processor

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