APPENDIX FEATURE DETERMINATION CPUID Instruction Military In

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APPENDIX FEATURE DETERMINATION CPUID Instruction Military In

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MILITARY Intel486 PROCESSOR FAMILY
APPENDIX FEATURE DETERMINATION
CPUID Instruction
Military Intel486 processor implements CPUID instruction that makes information available system software about family model stepping processor which executing Support this instruction indicated ability system software write read position EFLAGS referred EFLAGS actual state EFLAGS irrelevant provides significance hardware This reset zero upon device reset (RESET SRESET) compatibility with older Military Intel486 processor designs
0100 Family 0000 Intel Reserved 00000000 00000000 on-chip Intel Reserved
Operation
CPUID instruction requires software developer pass input parameter processor register processor response returned registers When parameter passed zero register values returned upon instruction execution
value returned after CPUID instruction execution identical value loaded into upon device reset Software must avoid dependency upon state reserved processor bits When parameter greater than register values returned upon instruction execution
00000000 00000000 00000000 00000000
756E6547
``Genu'' with ``G'' nibble 49656E69 ``inel'' with ``i' nibble
Flags Affected
flags affected
``ntel'' with ``n'' nibble values indicate Intel processor When taken proper order they decode string ``GenuineIntel When parameter passed register values returned upon instruction execution xxxx Stepping
6C65746E
Exceptions
None
More Information
Refer Intel application note AP-485 Intel Processor Identification with CPUID Instruction more details
xxxx
Model Table CPUID Instruction Description
OPCODE
Instruction CPUID
Processor Core Clocks
Input Value greater than
Description Processor Identification Intel String Null Registers
MILITARY Intel486 PROCESSOR FAMILY
APPENDIX BUFFER MODELS
processor speeds above MHz) capacitive derating curves guaranteed speeds buffer modeling techniques should used accurately simulate (and predict) behavior processor signals particular environment This appendix presents sample buffer model parameters IntelDX4 processor first section presents overview signal buffer type catagorization second section presents graphical representation IBIS Buffer Information Sheet) data each input input output output buffers types processor third section provides text listing data presented IBIS format buffer model information available Military Intel486 processors described this datasheet Contact your Intel representative latest buffer models IntelDX4 other members Military Intel486 processor family
Buffer Models IntelDX4 Processor
Each valid delay 50-MHz specified load system designer should buffer modeling account signal delays loading Table lists buffer type used each signal external interface
Table External Interface Signal Buffer Assignment Device IntelDX4 Processor Signals A20M AHOLD BOFF BRDY BS16 FLUSH HOLD IGNNE INTR RESET EADS STPCLK SRESET CLKMUL D16-D0 DP2-DP0 D31-D17 A31-A4 BLAST A3-A2 FERR -BE0 PCHK LOCK HLDA BREQ PLOCK SMIACT Type Drive Buffer TYPE Receiver Buffer Type
Sample IBIS Files IntelDX4 Processor
following pages present sample IBIS file outputs IntelDX4 processor
MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
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MILITARY Intel486 PROCESSOR FAMILY
Sample Text Listing IBIS Files IntelDX4 Processor
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MILITARY Intel486 PROCESSOR FAMILY
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APPENDIX FEATURE DETERMINATION CPUID Instruction Military In

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