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IDT79R3715 ADVANCE INFORMATION System Controller pin-compatible R


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SINGLE-CHIP SYSTEM CONTROLLER
IDT79R3715 ADVANCE INFORMATION
System Controller pin-compatible R30xx family processors DRAM Controller directly, banks directly Device depth supported: 256K Non-interleave Controller 20MB, Address-space support bank size: Support standard burst ROMs Support interleave non-interleave Direct Interface external master follows 8/16-bit Intel 80186 style Controller 8-bit 16-bit external channels non-DMA access 8-bit channels 8-32 packing, 32-8 unpacking logic access 16-32 packing, 32-16 unpacking CPU/ external master coprocessor accesses Round robin arbitration Programmable timing control signals Little Endian support PCMCIA Support Through 16-bit bus, using simple glue logic 16-bit 32-bit packing 32-bit 16-bit unpacking Little Endian support 256MB address space dedicated PCMCIA slots 24-bit Timer/Counter, In-Circuit testing capability Centronics Interface Bi-directional Centronics, compliant with IEEE1284 Supports controlled transfers Supports following modes: Compatible; Nibble; Byte; ECP; Interrupt Controller external level interrupts (through pins) internal interrupts Individual interrupt mask capability, enabling polling interrupt-driven systems General Purpose programmable Input (interrupts) Output pins
DRAM/ROM Control DRAM
Engine Interface
General Purpose R3041, R3051, R3052, R3071, R3081 RISController Serial
Bidirectional Centronics External Master
Master Interface
IDT79R3715
IDT79R3715 System Organization
3715-20
logo registered trademark R3715 trademark
COMMERCIAL TEMPERATURE RANGE
1995
April 1995
DSC- 9089/-
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
OVERVIEW
IDT79R3715 single-chip System Controller designed complement IDT's R30xx family 32-bit embedded processors. features necessary maximize performance RISC-based system reduce overall system chip count. R3715 move large amounts data quickly without need processor intervention. also achieves significant reduction system cost high level integration. Additional savings come from architecture controller, which allows utilization cost peripheral components (disk controller, network controller, etc.), while attaining higher level performance only associated with costlier components.
Some architectural characteristics that result very high performance include: incorporating tightly coupled interface R30xx RISC CPUs minimizing latency critical resources partitioning system balanced attain efficient shared resources enabling several simultaneous operations system R3715 ideal modular design laser printers because allows high level programmability incorporates control logic industry standard interface peripherals. This gives OEMs ability offer several products from same basic design, well ability upgrade systems field. block diagram that follows shows R3715 configuration.
IDT79R3715
Memory System
DRAM Control
3-Channel
Peripherals Modes: Compatible Nibble Byte e.g. Serial Network
Control System Arbiter Interface External Master Interrupt Controller External Master Interface Timer/ Counter
Bidirectional Centronics IEEE1284
Programmable
3715-21
IDT79R3715 Block Diagram
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
FUNCTIONAL DESCRIPTION
Processor Interface R3715 glueless interface R3041/51/52/71/81 family RISC processors. supports these devices both slave master modes operation. slave, they support access memory devices, master, handle accesses bus. slave R3715 supports processor single transfer read write, well burst read access. Each supports processor access ROM, DRAM, devices bus, R3715 internal registers. Burst read supported only DRAM read access. ACK* RDCEN* timing fixed R3715 registers. DRAM access extended clock, access timing programmable. master R3715 will request asserting BUSREQ* when source (internal external) needs transfer data from DRAM Channel. priority between sources following descending order: Access process External master will ownership least cycle after four accesses. This assumes that each external master (external agent) possession counted one, regardless number transfers executes bus. default state, when there request, owned CPU. Figure shows CPU-to-R3715 interface.
AD(31:0) Addr(3:2) Burst* SysClk* Ack* RdCEn* BusReq* BusGnt* Int* DataEn*
R3041, R3051, R3052, R3071, R3081
External Master Interface R3715 simple interface external master coprocessor. supports external master operation slave master modes. slave supports processor read write accesses external master, master enables access DRAM, ROM, (for font cartridges). R3715 directly controls data buffers address buffer needed isolate external master from bus. R3715 decodes access external master asserts ECS*, EAS*, EDS*. address latched into external transparent latch (373-type) when processor asserts driven into multiplexed (DAL[31:0]) EATOE*. Data driven from external master transceivers controlled EADDIR* EADOE*. external master cycle R3715 asserts RDCEN* ACK* when external master asserts EDTACK*. external master mode, external master requests asserting EBREQ*. R3715 will grant asserting EBGNT* (provided other device requested provided also that granted R3715). external master will assert EAS* first, then EDS*, initiate access system resource (e.g. DRAM). R3715 will assert EADOE* EADDIR* drive external master address, latch data phase will assert EADDIR* EADOE* according access direction (Read Write). cycle R3715 will assert EDTACK* external master. When does require longer external master will release deasserting EBREQ* External access DRAM takes clocks from EAS* EDTACK*. Frequencies above need additional clock cycle. clock added this interval using ExtCas DRAM control register. Figure following page shows typical implementation external master interface.
IDT79R3715
3715 03.1
Figure RISController R3715 Interface
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Address/Data
EADOE FCT16245 EADDir
FCT162373X2
BCAdr BReq
Back Channel SRAM 71256
EATOE EBReq EBGnt EDTAck EAAck
BCData BCRW BCOE BCCS WRCPU IReq RESET SYSClk External Master Interface
BGnt DTAck AAck
RESET SYSClk IDT79R3715
3715 10.1
Figure External Master Coprocessor Implementation
controller supports Mbyte memory with several device types system configurations. support these system device options, assertion time RDCEN* ACK* R3715 programmed, thus accommodating different types memory architectures, including standard ROMs, interleaved ROMs, burst ROMs. There three signals support three banks ROM. Each bank either non-interleaved interleaved (composed leaves differentiated ADDR[2]). ROMCS[2]* controls boot bank fixed address space Mbyte. Address space ROMCS[1]* ROMCS[0]* programmable Mbyte. R3715 puts bank address ranges contiguous address space. other words, start address next ROMCS[x]* will follow last address previous ROMCS[x-1]*. interleaved support, ROMOE* provided control interleave multiplexer. R3715 also supports burst
ROM, made write space (for flash debug) with additional glue logic. After reset, R3715 configured with maximum number wait states between each data transfer clocks between each RDCEN*) clocks between ROMCS[x]* ACK*. initial (reset) space size ROMCS[1]* ROMCS[0]* Mbyte, 4Mbytes ROMCS[2]*. Figure following page shows configuration ROM/DRAM memory system.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
IDT79R3715 EPROM/ROM
Address
Addr(10:0) DRAM
EPROM/ROM
RAS(2:0)
CAS(3:0) ROMCS(2:0) ROMOE FCT16373 Data
FCT16245
OEMAD
Address/Data
Figure R3715 ROM/DRAM Memory System
3715 04.1
DRAM DRAM controller supports directly Mbytes DRAM, with three non-interleaved banks. address space starts physical address DRAM device types supported have following attributes: page mode, early write, "CAS before RAS" refresh. DRAM controller supports single transfer reads writes burst reads. Various DRAM device depths supported address space continuous selected configuration. DRAM controller configured support different device depth base bank (RAS[0]*) extension banks (RAS[1]* RAS[2]*). systems running high frequency there option extend CAS* signals additional cycle. external master sample data rising edge SYSCLK*, falling edge. possible extend CAS* cycle external master accesses. minimize refresh penalty recommends that program refresh frequency according value SYSCLK*. initial values R3715 control registers reset shown tables Section Port Each PIO[5:0] pins individually programmed output input writing Control register. When programmed input used level (active LOW) interrupt. pins synchronized pulled internally. reset, PIOs initialized inputs.
Interrupt Controller Each interrupt source R3715 maskable. Cause register will reflect cause interrupt, writing into will acknowledge internal interrupt. example "BandInt" active, should write `fffB' into Cause register, order reset interrupt flag. external interrupts, PIO[5:0], acknowledged source interrupt (the interrupt flag deasserted when inactive), corresponding bits Interrupt Cause register read only. reset, interrupts masked mask register. DMA-Based Serial Interface DMA-supported channels used support protocols such AppleTalk directly, with only addition external communication controller, such 85C30 85C230, interface devices requires. R3715 FIFO Burst capabilities separating real-time demands protocols such AppleTalk from realtime demands engine interface, without cost implications external buffering.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Figure shows configuration AppleTalk port.
Figure shows configuration general purpose device interface.
(Address)
IOData(7:0)
26LS32 26LS32
IOData(15:0) IORd IOWr IOCS(1:0) IODReq(1:0) IODAck(1:0) IOWait IOBE0 IOBE1 IOGPCS(1:0) IOA1 IDT79R3715
3715 06.1
IORd IOWr IOCS(0) IODReq(0) IDT79R3715
26LS30 26LS30
85C30 85C30 85230 85230
Device
3715 07.1
Figure DMA-Supported AppleTalk Port
Programmable Timer/Counter general purpose timer/counter programmed function timer counter. counter, will cause interrupt stop counting when reaches terminal count. Writing value counter will start counter Enable active. timer terminal count, will cause interrupt, reload with value stored Timer/Counter Value register continue count. Timer/Counter counting enabled disabled enable bit. value should written Counter order count clocks. reset, counter disabled. R3715 supports 8-bit (IOCS[1:0]*) 16-bit (IOGPµCS[1:0]*) external channels that share IODATA[15:0] pins. 8-bit channels first 16-bit channel (IOGPCS[0]*) each Mbyte address space. second channel (IOGPCS[1]*) Mbyte address space. Timing control signals channel programmable. user specify length IORD* IOWR* signals. IOCS[1:0]*, IOGPCS[1:0]* DMAACK[1:0]* asserted cycle before IORD* IOWR* signals become active, remain active cycle after IORD* IOWR* dasserted. RDCEN* ACK* will asserted R3715 processor EDTACK* external master) cycle.
Figure General Purpose Device Interface
8-bit Channels R3715 supports processor byte accesses (reads writes) devices located channels. These accesses made using four bytes data bus. R3715 will transfer correct byte (according Byte Enables) (IODATA[7:0]). channel unit R3715 operates controller with channels. operations between devices DRAM supported. Eight data packed unpacked during access into register read write respectively. Operations Processor requests have priority over requests. priority operations round robin Centronics external 8-bit engines. DMAREQ[1:0]* masked writing enable channel. channel will participate arbitration channel disabled (Bus Interface Unit) owned another channel. emptied into memory read access under following conditions: full, there request (DMAREQ[1:0]) from channel which owns time period, byte count reaches zero. write direction DMAREQ* from channel that owns active time period, empty, arbitration will resume bus. time period clocks. clock period value cannot changed, only enabled disabled.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
16-bit Channels R3715 supports processor external master accesses (reads writes) devices located 16-bit channels. 16-bit devices, read write byte half word. Processor external master access 16-bit channels with combination byte enables active, will performed consecutive cycles case byte accesses. cycles, data will packed unpacked from 32-bit register read write respectively. Conversion between little endian supported 16-bit devices.
applies modes. That Byte Nibble modes only interrupt driven. There support special character detection Centronics incoming data. Control data characters like detected will interrupted. Figure shows configuration IEEE P1284 bidirectional centronics port. Negotiation R3715 defaults after reset Compatible mode. negotiation phase starts when host sets CSELECTIN* HIGH CAUTOFD* LOW. R3715 interrupts asserting CentWrInt interrupt. interrupt routine includes reading extensibility request value from Centronics External register, writing Centronics Control register specify supported mode. Note that interpretation CenRdInt CentWrInt interrupts, interrupt handler response, will different each mode. Table summarizes values host requests interrupt routine response.
LS646
IOData(7:0) CAck CBusy CPrErr CSel CFault
D(7:0) Bidirectional Centronics Interface
ACKNLG BUSY PAPEROUT SELECT FAULT
CStrobe CAutoFeed CInit CSelIn
DSTROBE AUTOFEED INPRM SELECTIN
Request mode Extensibility link first byte with
Request value 1000 0000 xxxx xxxx 0100 0000 0011 0000 0001 0000 0000 0100 0000 0101 0001 0100 0011 0100 0000 0001 0000 0000
Interrupt response: Modesupported value 1110 1xxx 1100 1011 1011 1001 1010 1011 1011 1010 0001
Interrupt response: Mode-notsupported value 0111 0110 0111 0111 0111 0111 0111 0111 0111 0111 1111
IDT79R3715
3715 08.1
Figure IEEE P1284 Bidirectional Centronics Port
Centronics IEEE 1284 Communication IDT's Centronics implementation meets IEEE 1284 definition compliant device. supports following modes: Compatible, Nibble, Byte, EPP, well negotiation necessary transition between different modes. Support Compatible mode includes following three variations: Standard, Epson, Classic. Note: urges designers review IEEE1284 Rev. specification complete discussion this Centronics standard. There ways handle Centronics protocol. first option, data transferred fashion only applicable Compatible, ECP, modes. second option interrupt driven,
Device -Nibble -Byte -ECP with -ECP without Byte Nibble
Table Interrupt Responses During Negotiation Phase
Compatible Mode needs configure Compatible mode three supported modes: IBM, Classic Standard, data transfer option (DMA interrupt byte). Setting modes options done writing mode register (values specified Centronics Mode register table). interrupt byte mode, will read data
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
responds CentRdInt interrupt. mode will initialize registers (addresses 1d0000a0, 1d000080 1d00098) before starting operation. R3715 will assert interrupt CentDMAInt when counter will reach terminal count. host request return Compatible mode from other modes indicated assertion CentRstInt interrupt. Nibble Mode R3715 will interrupt asserting CentWrInt when host requests byte transfer. will respond writing data Nibble data register. R3715 sends byte host over control lines consecutive nibble transactions. Byte Mode R3715 will interrupt asserting CentWrInt when host requests byte transfer. will respond writing data Centronics External register. Extensibility Link Assertion CentWrInt interrupt while Compatible. mode indicates extensibility request. will read from Centronics External register extensibility request value, write control register next mode proper response. Mode interrupt byte options supported mode. interrupt byte option, R3715 will assert CentRdInt host read requests, will assert CentWrInt host write requests. will read write from Centronics External register response interrupt. reverse transfer, response CentWrInt*, must first write Centronics status register Busy bit). This indicates whether sends command data byte, then write data Centronics External register. forward transfer, response CentRdInt needs read from Centronics host register (Autofeed bit) know whether host sending data command, then read data from Centronics register. Note: compression supported only interrupt byte mode. transfer option, data will transferred long direction host requests matches direction DMA. CentWrInt* will asserted when host requests data DmaDir Mode register indicates read direction (From IEEE1284 port memory). CentRdInt will asserted
when host sends data DmaDir indicates write direction when host sends command byte. Mode interrupt byte options supported mode, follows: interrupt byte option, R3715 will assert CentRdInt host read requests, will assert CentWrInt host write requests. will read write from Centronics External register response interrupt. will distinguish between data address contents strobe Selectin AutoFd bits host buffer. transfer option, data will transferred long direction host requests matches direction DMA. CentWrInt will asserted: when host requests data, DmaDir Mode register indicates read direction (from Centronics port memory), when host asks address byte. CentRdInt will asserted: when host sends data DmaDir indicates write direction, when host sends address byte. Control This mode enables values Centronics status register, communicate with host compatible mode. Character Detection. value three CentDetect 8-bit registers constantly compared Centronics incoming data. When match occurs interrupted. Characters detected during Centronics operations respond without need wait operation. Programmable Timing allow higher than specified IEEE1284 standard) data rates, minimum delay programmed values lower than minimum required this standard.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
INFORMATION
Logic Symbols
Signals marked with asterisk active when low. Dashed arrows figure indicate MUX'ed signals.
IODATA (15-0)
DMAREQ (1-0)
DADR (10-0)
(3-0)*
(2-0)*
DMAACK (1-0)*
IOCS (1-0)*
IOGPCS (1-0)*
IOBE (1-0)*
DWR*
DRAM ROMCS (2-0)* ROMOE*
Parallel Interface PSTROBE
IOA1
IOWAIT*
IORD*
IOWR*
CSELECT CFAULT* CACK* CWOE* OEMAD* Buffer Control Bidirectional Centronics CPERROR CAUTOFD* CROE* CWSTROBE CBUSY CRSTROBE CSTROBE* CINIT* CSELECTIN* (5-0)
TEST RESET* SYSCLK
Miscellaneous Interface External Master Interface
(31-0) ADDR (3-2) BURST* ACK* RDCEN* BUSREQ* BUSGNT* INT* DATAEN*
EADOE* EADDIR* EDTACK* EDS* EBREQ* EBGNT* EAS* ECS* EAACK* EATOE*
3715-23
Figure Logic Symbol R3715
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Assignment Table
names with trailing asterisk identify pins that active when low. Pull Pull P.U.
Name Interface A/D[31:0]
Type
Drive
Description Address/Data: Multiplexed address data bus. Address phase: A/D[31:4] address, A/D[3:0] Byte Enable[3:0]. During external Master cycles, A/D[3:2] contain address bits Byte Enables. Data phase: Data[31:0] Multiplexed Address: Connected ADDR[3:2]. cycles R3715 drives these lines. Burst Transfer: Used only during read cycles, BURST* signal indicates that current read requesting block four contiguous words from memory. connects CPU's BURSTWRNEAR* signal. cycles R3715 drives this signal HIGH. Address Latch Enable: Used indicate that contains valid address information transaction. During external master cycles, R3715 asserts capture address supplied external master. System Clock: Connected directly SYSCLK* output. Read: Indicates read access CPU. cycles R3715 drives signal HIGH. Write: Indicates write access external master. non-external master cycle R3715 drives this signal HIGH. negation indicates read access external master (during external master). Acknowledge: Indicates that memory system sufficiently processed transaction i.e. that either terminate write cycle process read data. Read Buffer Clock Enable: Indicates that there valid data bus. Used during read cycles only. Request: R3715 requests which required External DMA's. Grant: Indicates that relinquished bus. Interrupt: "OR's" internal external interrupt sources. Data Enable: indicates data phase read cycles. R3715 asserts DATAEN* when ROM/DRAM drives data onto A/D[31:0]. Chip Select: Select banks. They connected ROM's Chip Select Output Enable. ROMCS[2]* connected boot ROM, with starting physical address 0x1fc00000. Output Enable: Asserted when there access banks. Used output- enable data systems where there buffer between DRAM data bus; when using interleaved configuration.
ADDR[3:2] BURST*
P.U. P.U.
P.D.
SYSCLK P.U. P.U.
ACK*
RDCEN* BUSREQ* BUSGNT* INT* DATAEN*
ROMCS*[2:0]
ROMOE*
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name DRAM DADR[10:0] RAS[2:0]* CAS[3:0]*
Pull Pull
Type
Drive
Description DRAM Address: Multiplexed column address connected DRAM address. Adress Select: Directly connected, bank basis, with RAS* inputs DRAMs. Supports three banks DRAMs. Column Address Select: Directly connected, byte basis (can across banks), CAS* inputs DRAMs. Connects CAS* each four bytes every bank. DRAM Write: Connects write each DRAMs.
DWR* External Master Interface EBREQ* EBGNT* P.U.
12mA
External Master Request: external master request make system resource access master mode. External Master Grant: R3715 asserts EBGNT* grant external master. Once EBGNT* asserted, remains until EBREQ* deasserted. External Master Address Strobe: Master Mode (input) coprocessor indicates that driving valid data bus. Slave mode (output) R3715 indicates that driving valid data
EAS*
P.U.
EDS*
External Master Data Strobe: Master mode (input) during Write indicates that there valid data bus. During Read indicates data phase. Slave mode (output) R3715 drives EDS* indicate that ready accept data during reads that valid data available during write bus.
EDTACK*
P.U.
External Master Data Acknowledge: Master mode (output) R3715 asserts EDTACK* indicate that system receiving driving requested data to/from bus. Slave mode (input) external master asserts EDTACK* signal that supplied received data bus.
EAACK*
External Master Address Acknowledge: R3715 asserts EAACK* same clock that asserts external master. This insures that external master continues driving address until latched system. External Master Chip Select: When accesses external master, R3715 asserts ECS*. active clock before R3715 asserts EAS*. External Master Output Enable: R3715 asserts EADOE* when external master drives address bus, data phases external master. External Master Direction: R3715 asserts EADDIR* (LOW) when external master drives bus.
ECS*
EADOE*
EADDIR*
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name EATOE*
Pull Pull
Type
Drive
Description External Master Address Output Enable: R3715 asserts EATOE* address phase cycles which accesses external master.
Buffer Control OEMAD* Output Enable between Memory A/D: Output enable data path transceiver between memory system (ROM DRAM) bus. Input/Output Device Data: Bidirectional 16-bit Data bus. Input/Output Device Read: Active during Read from device. Input/Output Device Write: Active during Write device. Input/Output Device Chip Select: Chip selects channels Input/ Output Device Chip Select: Chip selects channels Request: Requesting service 8-bit channels Acknowledge: Indicating that access granted 8-bit channels Input/Output Device Address Provides half word bit) address bus. Input/Output Device Byte Enable: Indicates which byte data valid bus. IOBE[1]* corresponds IODATA[15:8] IOBE[0] corresponds IODATA[7:0]. IOWAIT* PIO[5:0] Bidirectional Centronics CWOE* CROE* Centronics Write Output Enable: Controls Output Enable signal data register from printer host. Centronics Read Output Enable: Controls Centronics external register direction from host printer (the IODATA[7:0] bus). Centronics Write Strobe: Clocks data from IODATA[7:0] into Centronics register (from printer host). Centronics Read Strobe: Clocks data from host into Centronics register (from host printer). P.U. P.U. Input/Output Device Wait: Indicates R3715 that transfer cycle needs extended. Programmable Input/Output: Individually programmed pins inputs, interrupt inputs outputs.
IODATA[15:0] IORD* IOWR* IOCS[1:0]* IOGPCS[1:0]* DMAREQ[1:0]* DMAACK[1:0]* IOA1 IOBE[1:0]* P.D. P.U. 12mA 12mA
CWSTROBE CRSTROBE
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name CSTROBE*
Pull Pull P.U.
Type
Drive
Description Centronics Strobe: Host driven. Compatibility mode: active transfer data into peripheral device's input latch. Data valid while signal low. Negotiation phase: active transfer extensibility request value into peripheral device's input latch. Data valid leading (falling) edge HostClk (CSTROBE*). Reverse data transfer phase: high during Nibble Mode transfers avoid latching data into peripheral device. Pulsed during Byte Mode transfers acknowledge transfer data from peripheral. peripheral device shall ensure that this pulse does transfer data byte into peripheral's input latch. mode: Used closed-loop handshake with PeriphAck (CBUSY) transfer data address information from host peripheral device. mode: denote address data write operation peripheral device. high denote address data read operation from peripheral device. more detailed description refer section IEEE P1284 D2.00 specification.
CACK*
Centronics acknowledge: Peripheral device driven. Compatibility mode: Pulsed peripheral device acknowledge transfer data byte from host. Negotiation phase: acknowledge 1284 support, then high indicate that Xflag (CSELECT) data available flags read. Reverse data transfer phase: Used both Nibble Byte Modes qualify data being sent host. Reverse idle phase: then high peripheral device cause interrupt indicating host that data available. mode: Used closed-loop handshake with HostAck (CAUTOFD*) transfer data from peripheral device host. mode: Used peripheral device interrupt host. This signal active high positive edge triggered. more detailed description refer section IEEE P1284 D2.00 specification.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name CBUSY
Pull Pull
Type
Drive
Description Centronics Busy: Peripheral device driven. Compatibility mode: Driven high indicate peripheral device ready receive data. Negotiation phase: Reflects present state peripheral device's forward channel. Reverse data transfer phase: Nibble mode: Data bits then then forward channel busy status. Byte mode: Forward channel busy status. Reverse idle phase: Forward channel busy status. mode: Used peripheral flow control forward direction. PeriphAck (CBUSY) also provides ninth data used determine whether command data information present data signals reverse direction. mode: Driven inactive positive acknowledgment from peripheral device that transfer data address completed. Signal active when low, should driven active indication that device ready next address data transfer. more detailed description refer section IEEE P1284 D2.00 specification.
CPERROR
Centronics Printer Error: Peripheral device driven. Compatibility mode: Driven high indicate that peripheral device encountered error paper path. Note that this signal's meaning varies among peripheral devices. Peripherals shall nFault (CFAULT*) whenever they Perror (CPERROR) high. Negotiation phase: high indicate 1284 support, then follows nDataAvail (CFAULT*). Reverse data transfer phase: Nibble mode: Data bits then Byte mode: Same nDataAvail (CFAULT*). mode: peripheral drives this signal acknowledge nReverseRequest (CINIT*). host relies upon nAckReverse (CPERROR) determine when permitted drive data signals. mode (User Defined manufacturer-specific signal. more detailed description refer section IEEE P1284 D2.00 specification.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name CSELECT
Pull Pull
Type
Drive
Description Centronics Select: Peripheral device driven. Compatibility mode: high indicate that peripheral device online. Negotiation phase: Used peripheral device reply requested extensibility byte sent host during negotiation phase. Affirmative response indicated with signal high request values except Nibble Mode Reverse Channel Transfer, which indicated affirmative with signal low. Reverse data transfer phase: Nibble mode: Data bits then Byte mode: Same negotiation phase. Reverse idle phase: Same negotiation phase. mode: Same negotiation phase. mode (User Defined manufacturer-specific signal. more detailed description this signal refer section IEEE P1284 D2.00 specification. more details about negotiation phase refer section same specification.
CAUTOFD*
P.U.
Centronics Autofeed: Host driven. Compatibility mode: Interpretation varies among peripheral devices. host some printers into auto line feed mode. Also used data, parity, command/data control bit. Negotiation phase: conjunction with 1284 Active (CSELECTIN*) being high request 1284 mode, then high after peripheral device sets PtrClk (CACK*) low. Reverse data transfer phase: Nibble mode: indicate host receive peripheral device host data, then high acknowledge receipt that nibble. Byte mode: Same Nibble mode request acknowledge bytes. Following reverse channel transfer, interface transitions idle phase when HostBusy (CAUTOFD*) peripheral device data available. Reverse idle phase: high response PtrClk (CACK*) pulse re-enter reverse data transfer phase. high with 1284 Active (CSELECTIN*) being low, 1284 idle phase aborted interface returns Compatibility mode. mode: host drives this signal flow control reverse direction. used interlocked handshake with PeriphClk (CACK*). HostAck (CAUTOFD*) also provides data used determine whether command data information present data signals forward direction. mode: Used denote data cycle, active when low. more detailed description refer section IEEE P1284 D2.00 specification.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name CINIT*
Pull Pull P.U.
Type
Drive
Description Centronics Initialize: Host driven. Compatibility mode: Pulsed conjunction with 1284 Active (CSELECTIN*) reset interface force return Compatibility mode idle phase. Negotiation phase: high. Reverse data transfer phase: high. mode: Driven place channel reverse direction. While this mode peripheral allowed drive only bidirectional data signals when nReverseRequest (CINIT*) 1284 Active (CSELECTIN*) high. mode: When driven active (low), initiates termination cycle that returns interface Compatibility mode. more detailed description refer section IEEE P1284 D2.00 specification.
CFAULT*
Centronics Fault: Peripheral device driven. Compatibility mode: peripheral device indicate that error occurred. meaning this signal varies among peripheral devices. Negotiation phase: high acknowledge 1284 compatibility. Nibble Byte mode then indicate peripheral device host data available following host setting HostBusy (CAUTOFD*) high. Reverse data transfer phase: Nibble mode: indicate that peripheral device data ready send host, then used send data bits then Byte mode: Used indicate that data available. mode: this mode peripheral drive this request communication with host. request only suggestion host, ultimate control over transfer direction. Typically used generate interrupt host, also provides mechanism peer-to-peer communication. Signal valid both forward reverse directions. mode (User Defined Manufacturer-specific signal. more detailed description refer section 4.10 IEEE P1284 D2.00 specification.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Name CSELECTIN*
Pull Pull P.U.
Type
Drive
Description Centronics Select Input: Host driven. Compatibility mode: host select peripheral device. Negotiation phase: high conjunction with HostBusy (CAUTOFD*) being request 1284 mode. Reverse data transfer phase: high indicate that direction peripheral device host. terminate 1784 mode direction host peripheral device. Reverse idle phase: Same Reverse data transfer phase. mode: Driven high host while mode. host terminate mode return link Compatibility mode. mode: Used denote address cycle, active low. more detailed description refer section 4.11 IEEE P1284 D2.00 specification.
Parallel Port Control PSTROBE* POE* Parallel Strobe: Clocks 8-bit 16-bit parallel data from IODATA[15:0]. Parallel Output Enable: When active (LOW) controls output enable data buffer 8-bit 16-bit wide parallel data into IODATA[15:0]. Master Output Enable: When TEST HIGH RESET* active, device outputs I/Os tri-stated system, TEST should pulled down GND). Reset: Will reset R3715 initial state. (+/-5%) Ground
Misc. TEST P.D.
RESET*
NOTE: Pull Up/Pull identifies pins with internal Pull (P.U.) Pull Down (P.D.) resistors. P.U./P.D. values 35K-150Kohm depending process variation.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
TIMING CHARACTERISTICS
(TC= 0-70oC; VDD= +5V,
Symbol SYSCLK SYSCLK SYSCLK RESET* Reserved BUSREQ*, ACK*, RDCEN* A/D[31:0], OEMAD*, EADOE* A/D[31:0], ADDR[3:2], WR*, PIO[5:0], EAS*, EDS*, EDTACK* A/D[31:0] A/D[31:0] A/D[31:0] BURST*, RD*, DATAEN*, WR*, ADDR[3:2], BUSGNT* ALE, BURST*, RD*, DATAEN*, INT*, PIO[5:0], IODATA[15:0], EAS*, EDS*, EDTACK* ALE, BURST*, RD*, DATAEN*, PIO[5:0] ALE, BURST*, RD*, DATAEN*, IOGPCS*, ROMCS*[2:0], IORD*, IOWR*, ROMOE*, IOA1, IOBE*[1:0], INT*, DMAACK*[1:0], PIO[5:0], ADDR[3:2], WR*, EAS*, EDS*, EDTACK*, ECS*, EBGNT*, EAACK* ADDR[3:2], DADR[10:0] DADR[10:0] RAS*[2:0], DWR* CAS*[3:0] CAS*[3:0] IODATA[15:0] IODATA[15:0] IODATA[15:0] IOWAIT* DMAREQ*[1:0], PIO[5:0] Reserved Reserved Reserved TEST, EBREQ* EAS*, EDS*, EDTACK* EADDIR*, EATOE* Setup SYSCLK rising Setup SYSCLK rising Valid from SYSCLK rising Valid from SYSCLK rising Valid from SYSCLK falling Driven from SYSCLK rising Tri-state from SYSCLK rising Set-up SYSCLK falling Set-up falling Set-up SYSCLK falling Set-up SYSCLK rising Tri-state from SYSCLK rising Driven from SYSCLK rising Valid from SYSCLK rising Signal(s) Description Pulse Width High Pulse Width Clock period Pulse Width from Valid Unit
Tri-state from SYSCLK rising Valid from address valid Valid from SYSCLK rising Valid from SYSCLK rising SYSCLK rising CAS* SYSCLK falling CAS* HIGH Hold from IOWR* rising Set-up SYSCLK rising Driven from SYSCLK rising Set-up SYSCLK rising Asynchronous Inputs
Asynch
Note: Internal VCLK frequency (divided not) should lower than SYSCLK frequency. Valid only SYSCLK during which IODATA sampled.
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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ELECTRICAL SPECIFICATIONS
(TC= 0-70oC; VDD= +5V, Symbol CINCLK Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Input Leakage Current 3-State Output Leakage current Operating Current Input Capacitance Input Capacitance Min. -0.5 Max. VDD+0.5 Unit VOUT Ta=25C Conditions
REGISTER TABLES-R3715
register tables this section, please note: Reads Writes from R3715 internal registers should word (32-bit) accesses. notations indicate hexadecimal values, notations language. least significant bit.
REGISTER
Description Configuration Value Control Read Pins Timer/Counter Value Timer/Counter Control Interrupt Cause Interrupt Mask Interrupt Write Test DRAM Control Address Address Centronics Address Physical Address 0x1d000000 0x1d000040 0x1d000044 0x1d00005c 0x1d000048 0x1d00004c 0x1d000050 0x1d000054 0x1d000060 0x1d000064 0x1d000058 0x1d000080 0x1d000084 0x1d000088 Description Count Count Centronics Count Channel Timing Centronics Status Centronics Control Centronics Nibble Data Centronics Host Centronics Mode Centronics Minimum Delay Centronics Data Detect Centronics Data Detect Centronics Data Detect Physical Address 0x1d000090 0x1d000094 0x1d000098 0x1d0000a0 0x1d000100 0x1d000104 0x1d000108 0x1d00010c 0x1d000110 0x1d000114 0x1d0000a4 0x1d0000a8 0x1d0000ac
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
REGISTER TABLES
remainder this section contains register tables R3715.
Configuration
This register used address space configurable banks (ROMCS[1:0]*) number wait state cycles inserted between data phases.1 Address: 1d000000
Bits
Field name
First
Function
(number cycles) from ROMCS* active first RDCEN*. 0000 cycle 0001 cycles cycles cycles range) between first RDCEN* second RDCEN* 0000 cycle 0001 cycles cycles cycles range) between second RDCEN* third RDCEN*. 0000 cycle 0001 cycles cycles cycles range) between third RDCEN* fourth RDCEN* 0000 cycle 0001 cycles cycles cycles range) from ROMCS* active AckTime block read 000000 cycle 000001 cycles cycles cycles range) ROMCS[1:0]* address space size (ROMCS[2] fixed Mbyte address space) Mbyte Mbyte Mbyte Mbyte
Initial Value
Gap1
8-11
Gap2
12-15
Gap3
16-21
AckTime
0x3f
22-23
SpaceSize
NOTE: user's responsibility AckTime timing correctly.
Value
This register used value those pins configured Control register outputs. Address: 1d000040 Bits Field name Value Function Value pins configured outputs Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Control
This register sets direction pins. Address: 1d000044 Bits Field name Control Function Sets direction corresponding pin: Output Input Must Initial Value 0x3f
Reserved
Read Pins
This address used read inputs from pins. Address: 1d00005C Bits Field name Input Value Function Value pins Initial Value
Timer/Counter Value
This register used number clocks counted Timer/Counter. Address: 1d000048 Bits 0-23 Field name Value Function Number clocks count. count Initial Value 0x000000
Timer/Counter Control
This register used enable disable Timer/Counter select specific mode use. Address: 1d00004c Bits Field name Enable Function Timer/Counter count enable Disable Enable Select mode operation Counter Timer Initial Value
Select
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Interrupt Cause
This register used identify source behind interrupt; also used polling specific interrupt interrupts. value indicates assertion interrupt. This register also used clear internal interrupts, writing will reset corresponding internal interrupt. Writing will have effect interrupt. External interrupts should cleared external mechanism. Address: 1d000050 Bits Field name Reserved Reserved Reserved Reserved TimInt IODMAInt[1:0] Timer/Counter interrupt Channel end-of-DMA interrupts Channel Channel Centronics end-of-DMA interrupt Function Initial Value
14-16
CentDMAInt Reserved Reserved Reserved CentRstInt CentWrInt CentRdInt EqualInt
Centronics reset interrupt Centronics write interrupt Centronics read interrupt Centronics equal interrupts Centronics Data Detect Centronics Data Detect Centronics Data Detect Programmable external interrupts (read only) PIOInt[0], etc.
17-19 20-25
Reserved PIOInt[5:0]
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Interrupt Mask
This interrupt used mask (disable) specific interrupt sources, both internal external (PIO). interrupts maskable. value masks corresponding interrupt. Address: 1d000054 Bits Field name Reserved Reserved Reserved Reserved TimInt IODMAInt[1:0] Timer/Counter interrupt Channel end-of-DMA interrupts Channel Channel Centronics end-of-DMA interrupt Function Initial Value
14-16
CentDMAInt Reserved Reserved Reserved CenRstInt CentWrInt CentRdInt EqualInt
Centronics reset interrupt Centronics write interrupt Centronics read interrupt Centronics equal interrupts Centronics Data Detect Centronics Data Detect Centronics Data Detect Programmable external interrupts (read only) PIOInt[0], etc.
17-19 20-25
Reserved PIOInt[5:0]
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Interrupt Write
This register used write Interrupt Cause register. This register should used interrupt testing only. Address: 1d000060 Bits Field name Reserved Reserved Reserved Reserved TimInt IODMAInt[1:0] Timer/Counter interrupt Channel end-of-DMA interrupts Channel Channel Centronics end-of-DMA interrupt Function Initial Value
14-16
CentDMAInt Reserved Reserved Reserved CentRstInt CentWrInt CentRdInt EqualInt
Centronics reset interrupt Centronics write interrupt Centronics read interrupt Centronics equal interrupts Centronics Data Detect Centronics Data Detect Centronics Data Detect
Test
reading writing from/to this address. Doing result improper generation this device. Address: 1d000064
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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DRAM Control
This register used desired DRAM device depth, access time (both external master) refresh frequency. Address: 1d000058 Bits Field name DevDepth Bank Function Depth DRAM device used, words. 256K 512K Depth DRAM device used, words. 256K 512K duration both external master accesses. active half cycles active half cycles duration external master accesses only. active external master accesses half cycles active external master accesses half cycles SYSCLK frequency. 15.6 refresh time 16MHz 15.6 refresh time 20MHz 15.6 refresh time 25MHz 15.6 refresh time 33MHz Initial Value
DevDepth Bank
ExtCas
ExtCas
RefFreq
Address
This register used first DRAM address used channel operations. Address: 1d000080 Bits 0-25 Field name DmaAddr0 Function First address channel Initial Value
Address
This register used first DRAM address used channel operations. Address: 1d000084 Bits 0-25 Field name DmaAddr1 Function First address channel Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Centronics Address
This register used first DRAM address used Centronics operation. Address: 1d000088 Bits 0-25 Field name DmaAddrCent Function First address Centronics DMA. Initial Value
Count
This register used number bytes transferred channel operation. Address: 1d000090 Bits 0-15 Field name DmaCnt0 Function count channel Load with transfer Initial Value
Count
This register used number bytes transferred channel operation. Address: 1d000094 Bits 0-15 Field name DmaCnt1 Function count channel Load with transfer Initial Value
Centronics Count
This register used number bytes transferred Centronics operation. Address: 1d000098 Bits 0-15 Field name DmaCntCen Function Centronics count. Load with transfer Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Channel Timing
This register used configure parameters, including signal timing; enabling, time-out, direction; endianess 16-bit channels. DevTime fields specify number cycles IORD* IOWR* asserted access. Time Enable (TOEn) field chooses between inserting clock cycles between arbitration cycles not; normally, enabling this results better system performance. Address: 1d00000a0
Bits Field name DevTime0 Function 8-bit channel (IOCS0*) access time. 0000 cycle 0001 cycles nn+1 cycles cycles range) DmaEn0 DmaR/W0 DevTime1 enable 8-bit channel disable write enable read Read Write 8-bit channel 8-bit channel (IOCS1*) access time. 0000 cycle 0001 cycles nn+1 cycles cycles range) 12-15 DmaEn1 DmaR/W1 CenTime enable 8-bit channel disable write enable read Read Write 8-bit channel Centronics external register access time. 0000 cycle 0001 cycles nn+1 cycles cycles range) 18-21 DmaEnCen DmaR/WCen DevTime3 Centronics enable. disable write enable read Read Write Centronics interface. 16-bit channel (IOGPCS0*) access time. 0000 cycle 0001 cycles nn+1 cycles cycles range) 22-25 DevTime4 16-bit channel (IOGPCS1*) access time. 0000 cycle 0001 cycles nn+1 cycles cycles range) BigEndian0 BigEndian1 TOEn Little Endian 16-bit channel Endian Endian Little Endian Little Endian Little Endian 16-bit channel Time Enable both channels Time disabled, time clocks Time enabled, time clocks Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Centronics Status
This register used implement Centronics hand-shake protocol software CPU. Address: 1d000100 Bits Field name Busy Function Busy indication Ready Busy Acknowledge acknowledge Normal Fault Fault indication Fault Normal Select Select line line Perror Paper Error indication error Error Initial Value
Centronics Control
This register used Centronics transfer mode IEEE 1284 specification Rev. Address: 1d000104 Bits Field name Mode Function IEEE 1284 modes Compatible Nibble Byte control extensibility link termination NegRep Negotiation Reply modes except nibble mode: mode requested host supported peripheral mode requested supported Nibble mode: mode requested host supported peripheral mode requested supported Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Centronics Nibble Data
This register used post data transferred nibble mode. Address: 1d000108 Bits Field name NibData Function Nibble mode Centronics data sent host Initial Value
Centronics Host
This register used read inputs from host Centronics protocol pins. Address: 1d00010c Bits Field name Strobe SelectIn Init AutoFd Function compatible mode) host transfer data host select printer Pulsed with SelectIn active reset Centronics interface host printer auto-feed mode. Initial Value
Centronics Mode
This register used Centronics parameters select protocol options Compatible mode. Address: 1d000110 Bits Field name Application Function IEEE 1284 standard details Standard Epson Reserved Classic DmaEn DmaDir transmission executed transmission executed write reads Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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Centronics Minimum Delay
This register contains values that needed each operating frequency comply with IEEE 1284 standard (minimum 500ns 2500ns). However systems with higher performance requirements, possible program minimum delays lower values. Address:1d000114 Bits Field name 2500ns Function 16MHz 0x28 20MHz 0x32 25MHz 0x3f 33MHz 0x53 7-13 500ns 16MHz 0x08 20MHz 0x0a 25MHz 0x0d 33MHz 0x11 Initial Value
Centronics Data Detect
This register used hold value compared against incoming bytes. case match, interrupt will issued. corresponding interrupt masked Interrupt Mask register. Address: 1d0000a4 Bits Field name DataDet0 Function Data used comparison with incoming data. Initial Value
Centronics Data Detect
This register used hold value compared against incoming bytes. case match, interrupt will issued. corresponding interrupt masked Interrupt Mask register. Address: 1d0000a8 Bits Field name DataDet1 Function Data used comparison with incoming data. Initial Value
Centronics Data Detect
This register used hold value compared against incoming bytes. case match, interrupt will issued. corresponding interrupt masked Interrupt Mask register. Address: 1d0000ac Bits Field name DataDet2 Function Data used comparison with incoming data. Initial Value
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
EXTERNAL ADDRESS SPACE
address space allocated different resources system shown Table 4.1. Bits 29-31 decoded that physical aliases Mbyte created. This enables software access same system resource using different attributes (i.e cached space uncached space, kernel user).
Description DRAM ROMCS[2]*. ROMCS[1]* ROMCS[0]* channel channel channel channel Centronics external register External master address space Internal registers
Table Note: 1This
Size 256M
column specifies maximum range.
Physical Address Range1 0X00000000: 0x027FFFFF 0x1FC00000: 0x1FFFFFFF 0x1F400000: 0x1FBFFFFF 0x1EC00000: 0x1F3FFFFF 0x08000000: 0x08FFFFFF 0x09000000: 0x09FFFFFF 0x0B000000: 0x0BFFFFFF 0x0C000000: 0x1BFFFFFF 0x0A000000: 0x0A0FFFFF 0x1C000000: 0x1CFFFFFF 0x1D000000: 0x1DFFFFFF
Table External Address Space
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
IMPLEMENTATION EXAMPLES
Full Implementation
possible implementation fully featured system shown Figure 5.1. This system includes 2-way interleaved array, uses external multiplexers (FCT257x8) that controlled MUX_ADDR[2] choose bank other. R3715 directly provides output enable signal these multiplexers (ROMOE*), well chip select signal banks (ROMCS*[2:0]). control DRAM banks provided directly signals coming R3715. These signals directly control banks DRAM 40MB. This
implementation supports external master, extra latches transceivers used accommodate control signals necessary provide master slave operations external master provided. Multiplexing between external master done BUSGNT*. R3715 video/engine interface processes line page synchronization signals from engine provides with serial video data stream. R3715 also generates control signals necessary transfer parallel byte word data from parallel interface (POE* PSTROBE*).
LATCH_ADDR
ROMCS*[2:0]
MUX_ADDR[2] MUX_ADDR[3,2]
257x8
ROMOE*
DADR[10:0] EADDR[3:2] R30xx ADDR[3:2] DATAEN* A/D[31:0] BUSREQ* BUSGNT* EATOE* 373x1 16245x2 EADOE* EADDIR* R3715 COE* CSTROBE* C*** C*** Centronics Connector 16373x2 16245x2 OEMAD* DWR* DRAM CAS*[3:0] RAS[2:0]*
DAL[31:0] EAS* EDS* External Master EDTACK* ECS* EBGNT* EBREQ* EAACK* LATCH_ADDR[29:2]
IODATA[15:0] Control Expansion Connector
SYSCLK, INTERRUPTS, ETC.
Figure Note: C***=Centronics Control Signals
Figure Full Implementation With Interleaved
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
full complement signals provided R3715 implement IEEE1284 bi-directional Centronics interface. 80186-style interfaces connector that used expand features adding standard industry peripherals like SCSI, PCMCIA cards, UARTs, Ethernet, etc.
Minimal Implementation
Figure shows minimal implementation. this case, show lower R3051 Family, R3041. simple non-interleaved subsystem used this case, with only bank boot bank ROMCS[2]*. DRAM system contains only bank mentioned before, R3715 directly provides necessary signals.
Since coprocessor used this case, interface very simple. balance features shown same, this could conceivably include simpler implementations each, like less peripherals IODATA bus, lower video rate that could associated with engine with less dots inch less pages minute. Both full minimal implementations shown demonstrate flexibility R3715 common block that enables modular designs designs that upgraded field.
LATCH_ADDR ROMCS[2]*
DADR[10:0] DRAM R3041 ADDR[3:2] DATAEN* A/D[31:0] BUSREQ* BUSGNT* CAS[3:0] RAS[0]*
16373x2
DWR*
COE* CSTROBE* C*** C*** IODATA[15:0] Control Centronics Connector
79R3715
Expansion Connector
Figure Note: C***=Centronics Control Signals
Figure Minimal Implementation
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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PINOUT TABLE
Signal Name AD(14) AD(13) AD(12) AD(11) AD(10) AD(9) AD(8) AD(7) AD(6) AD(5) AD(4) AD(3) AD(2) AD(1) AD(0) BURST* ADDR(3) ADDR(2) DATAEN* BUSGNT* RESET* ACK* RDCEN* BUSREQ* INT* EADOE* EADDIR* EATOE* EDTACK* EDS* EBREQ* EBGNT* Signal Name EAS* ECS* EAACK* PIO(0) PIO(1) PIO(2) PIO(3) PIO(4) PIO(5) CSELECTIN* CINIT* CSTROBE* CRSTROBE CBUSY SYSCLK CWSTROBE CROE* CAUTOFD* CPERROR CSELECT CWOE* CACK* CFAULT* POE* PSTROBE* N.C. N.C. N.C. N.C. IOWAIT* DMAACK(1)* DMAACK(0)* IOWR* IORD* IOA1 Signal Name IOBE(1)* IOBE(0)* IOGPCS[1]* IOGPCS[0]* IOCS(1)* IOCS(0)* DMAREQ(0) DMAREQ(1) IODATA(15) IODATA(14) IODATA(13) IODATA(12) IODATA(11) IODATA(10) IODATA(9) IODATA(8) IODATA(7) IODATA(6) IODATA(5) IODATA(4) IODATA(3) IODATA(2) IODATA(1) IODATA(0) DADR(10) DADR(9) DADR(8) DADR(7) DADR(6) DADR(5) DADR(4) DADR(3) DADR(2) DADR(1) DADR(0) Signal Name RAS*[0] RAS(1)* RAS(2)* CAS(0)* CAS(1)* CAS(2)* CAS(3)* DWR* ROMCS(2)* ROMCS(1)* ROMCS(0)* ROMOE* Reserved Reserved Reserved Reserved AD(31) AD(30) AD(29) AD(28) AD(27) AD(26) AD(25) AD(24) AD(23) AD(22) AD(21) AD(20) AD(19) AD(18) AD(17) AD(16) AD(15) OEMAD* TEST
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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TIMING DIAGRAMS
This section contains timing diagrams R3715 signals. SYSCLK
A/D[31:0]
addr
data
DATAEN*
ROMCS*[2:0]
OEMAD*
ACK* RDCEN* first
Read (Programmable)
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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SYSCLK ADDR[3:2] A/D[31:0] BURST* ACK* time ACK* RDCEN* DATAEN* ROMCS*/ ROMOE* first addr
Interleaved Burst Read (Programmable)
SYSCLK A/D[31:0] addr DADR[10:0] address RAS* CAS* OEMAD* ACK* RDCEN* CAS* column addr data
DRAM Read (Programmable)
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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SYSCLK A/D[31:0] addr address column address data addr
DADR[10:0]
RAS*
CAS*
DWR*
OEMAD*
ACK*
DRAM Write
SYSCLK A/D[31:0] BURST* DADR[10:0] RAS* CAS* OEMAD* RDCEN* ACK* addr column addr addr
DRAM Burst Read
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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SYSCLK A/D[31:0] ADDR[3:2] ACK* RDCEN* IOGPCS* IORD* IOWAIT* IODATA[15:0] IOBE[1:0]* IOA1
ZZZZ FFFF ZZZZ FFFF ZZZZ FFFF0010 FFFFFFFF
devtime
devtime
Read 16-Bit
SYSCLK IOGPCS* IOWR* IOA1 IOBE* IODATA[15:0] data data
Write 24-Bit
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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SYSCLK
IOGPCS* IOWAIT*
IOWR*
IODATA[15:0]
Write (With Wait State)
SYSCLK DMAREQ
DMAACK*
IORD*
IODATA[7:0]
Read
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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SYSCLK ADDR[3:2] A/D[31:0] EBREQ* EBGNT* EAS* EAACK* EDS* EDTACK* EADDIR* IODATA[15:0] IORD*
addr address
External Master- Master Read
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
2900000
2950000
3000000
3050000
SYSCLK AD[31:0] ADDR[3:2] BURST* ACK* RDCEN* BUSREQ* BUSGNT* EADOE* EADDIR* EDTACK* EDS* EBREQ* EBGNT* EAS* ECS* EAACK* EATOE* RAS[2:0]* CAS[3:0]* DADR[10:0] DWR*
00000017 44660000 44661199
External Master- Master Read
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
3090000
3100000
3110000
3120000
3130000
3140000
3150000
SYSCLK AD[31:0] ADDR[3:2] BURST* ACK* RDCEN* BUSREQ* BUSGNT* EADOE* EADDIR* EDTACK* EDS* EBREQ* EBGNT* EAS* ECS* EAACK* EATOE* RAS[2:0]* CAS[3:0]* DADR[10:0] DWR*
0000FEA0 00000015 20134048 44661199
External Master- Master Write
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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2560000
2570000
2580000
2590000
2600000
2610000
SYSCLK AD[31:0] ADDR[3:2] BURST* ACK* RDCEN* BUSREQ* BUSGNT* EADOE* EADDIR* EDTACK* EDS* EBREQ* EBGNT* EAS* ECS* EAACK* EATOE* RAS[2:0]* CAS[3:0]* DADR[10:0] DWR*
A8000018 1C000000 00000000
External Master- Slave Read
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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2580000
2585000
2590000
2595000
2600000
2605000
2610000
SYSCLK AD[31:0] ADDR[3:2] BURST* ACK* RDCEN* BUSREQ* BUSGNT* EADOE* EADDIR* EDTACK* EDS* EBREQ* EBGNT* EAS* ECS* EAACK* EATOE* RAS[2:0]* CAS[3:0]* DADR[10:0] DWR*
00000000 1C000000
External Master- Slave Write
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
SYSCLK BUSREQ* BUSGNT* OEMAD* DWR* A/D[31:0] DADR[10:0] RAS* CAS*
data word column
Write
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
105000 SYSCLK AD[31:0] ADDR[3:2] BUSREQ* BUSGNT* DATAEN* OEMAD cselectin* cautofd* cstrobe* cbusy cack* croe* cwoe* crstrobe cwstrobe dmareq[1:0] RAS[2:0]* CAS[3:0]* DADR[10:0] IOWR* IORD* IODATA[15:0]
110000
115000
120000
125000
130000
135000
Centronics Compatible DMA-Standard
(Application=00)
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
1500000
1520000
1540000
1560000
1580000
1600000
SYSCLK AD[31:0] ADDR[3:2] BUSREQ* BUSGNT* DATAEN* OEMAD cselectin* cautofd* cstrobe* cbusy cack* croe* cwoe* crstrobe cwstrobe dmareq[1:0] RAS[2:0]* CAS[3:0]* DADR[10:0] IOWR* IORD* IODATA[15:0]
ZZZZ ZZZZ ZZZZ 00080000 00080000 00080000 00080000
Forward Transfer
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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196000
198000
200000
202000
204000
SYSCLK AD[31:0] ADDR[3:2] BUSREQ* BUSGNT* DATAEN* OEMAD cselectin* cautofd* cstrobe* cbusy cack* croe* cwoe* crstrobe cwstrobe dmareq[1:0] RAS[2:0]*
00080000 00080000 00080000
CAS[3:0]* DADR[10:0] IOWR* IORD* IODATA[15:0]
ZZZZ ZZ9D
ZZZZ
ZZ6D
Reverse Transfer
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
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PACKAGE
160-Pin Quad Flat Package (QFP, EIAJ)
31.2
28.0
+0.102
31.2
28.0
0.26 -0.551
0.65 0.152
1.325 REF.
Figure 10.1 160-Pin Quad Flat Package
3134
79R3715 SINGLE-CHIP SYSTEM CONTROLLER
ADVANCE INFORMATION
Quad Flat Package-Expanded View (QFP, EIAJ)
31.2
0°-7° Typ. 0.26 -0.551
+0.102
Typ. 3.33
+0.551 -0.102
0.15 Ref.
Seating Plane
3134
Figure 10.2 Expanded View Figure 10.1 Detail
VALID COMBINATIONS
79R3715PF
160-pin PQFP

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