Compatible with MCS-51Products Kbytes In-System Reprogrammable Flash M

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Compatible with MCS-51Products Kbytes In-System Reprogrammable Flash M

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AT89LV51
Compatible with MCS-51Products Kbytes In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Operating Range Fully Static Operation: Three-Level Program Memory Lock 8-Bit Internal Programmable Lines 16-Bit Timer/Counters Interrupt Sources Programmable Serial Channel Power Idle Power Down Modes
Description
AT89LV51 low-voltage, high-performance CMOS 8-bit microcomputer with Kbytes Flash Programmable Erasable Read Only Memory (PEROM). device manufactured using Atmel's high density nonvolatile memory technology compatible with industry standard MCS-51instruction pinout. on-chip Flash allows program memory reprogrammed in-system conventional nonvolatile memory programmer. combining versatile 8-bit with Flash monolithic chip, Atmel AT89LV51 powerful microcomputer which provides highly flexible cost effective solution many embedded control applications. AT89LV51 provides following standard features: Kbytes Flash, bytes RAM, lines, 16-bit timer/counters, five vector two-level interrupt architecture, full duplex serial port, on-chip oscillator clock circuitry. addition, AT89LV51 (continued)
8-Bit Microcontroller with Kbytes Flash
Configurations
XTAL XTAL
PDIP
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN (A11
PQFP/TQFP
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN
XTAL XTAL (A11
INDEX CORNER
INDEX CORNER
PLCC
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN
XTAL XTAL (A11
0303C
3-49
Block Diagram
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AT89LV51
AT89LV51
Description (Continued)
designed with static logic operation down zero frequency supports software selectable power saving modes. Idle Mode stops while allowing RAM, timer/counters, serial port interrupt system continue functioning. Power Down Mode saves contents freezes oscillator disabling other chip functions until next hardware reset. written Port pins they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because pullups. Port also serves functions various special features AT89LV51 listed below: Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions (serial input port) (serial output port) INT0 (extenal interrupt INT1 (extenal interrupt (timer extenal input) (timer external input) (extenal data memory write strobe) (external data memory read strobe)
Description
Supply voltage.
Ground.
Port
Port 8-bit open drain bidirectional port. output port each sink eight inputs. When written port pins, pins used high-impedance inputs. Port also configured multiplexed low-order address/data during accesses external program data memory. this mode internal pullups. Port also receives code bytes during Flash programming, outputs code bytes during program verification. External pullups required during program verification.
Port
Port also receives some control signals Flash programming programming verification.
Reset input. high this machine cycles while oscillator running resets device.
ALE/PROG
Port 8-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When written Port pins they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because internal pullups. Port also receives low-order address bytes during Flash programming program verification.
Port
Address Latch Enable output pulse latching byte address during accesses external memory. This also program pulse input (PROG) during Flash programming. normal operation emitted constant rate oscillator frequency, used external timing clocking purposes. Note, however, that pulse skipped during each access external Data Memory.
PSEN
Port 8-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When written Port pins they pulled high internal pullups used inputs. inputs, Port pins that externally being pulled will source current (IIL) because internal pullups. Port emits high-order address byte during fetches from external program memory during accesses external data memory that 16-bit addresses (MOVX DPTR). this application uses strong internal pullups when emitting During accesses external data memory that 8-bit addresses (MOVX RI), Port emits contents Special Function Register. Port also receives high-order address bits some control signals during Flash programming verification.
Port
Program Store Enable read strobe external program memory. When AT89LV51 executing code from external program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external data memory.
EA/VPP
External Access Enable. must strapped order enable device fetch code from external program memory locations starting 0000H FFFFH. Note, however, that lock programmed, will internally latched reset. should strapped internal program executions. This also receives 12-volt programming enable voltage (VPP) during Flash programming, when 12-volt programming selected.
XTAL1
Input inverting oscillator amplifier input internal clock operating circuit.
XTAL2
Port 8-bit bidirectional port with internal pullups. Port output buffers sink/source four inputs. When
Output from inverting oscillator amplifier.
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Oscillator Characteristics
XTAL1 XTAL2 input output, respectively, inverting amplifier which configured onchip oscillator, shown Figure Either quartz crystal ceramic resonator used. drive device from external clock source, XTAL2 should left unconnected while XTAL1 driven shown Figure There requirements duty cycle external clock signal, since input internal clocking circuitry through divide-bytwo flip-flop, minimum maximum voltage high time specifications must observed. Figure Oscillator Connections
XTAL2
XTAL1
Idle Mode
idle mode, puts itself sleep while on-chip peripherals remain active. mode invoked software. content on-chip special functions registers remain unchanged during this mode. idle mode terminated enabled interrupt hardware reset. should noted that when idle terminated hardware reset, device normally resumes program execution, from where left off, machine cycles before internal reset algorithm takes control. On-chip hardware inhibits access internal this event, access port pins inhibited. eliminate possibility unexpected write port when Idle terminated reset, instruction following that invokes Idle should that writes port external memory.
Notes: Crystals Ceramic Resonators
Figure External Clock Drive Configuration
XTAL2
Power Down Mode
power down mode oscillator stopped, instruction that invokes power down last instruction executed. on-chip Special Function Registers retain their values until power down mode terminated. only exit from power down hardware reset. Reset redefines SFRs does change on-chip RAM. reset should activated before restored normal operating level must held active long enough allow oscillator restart stabilize.
EXTERNAL OSCILLATOR SIGNAL
XTAL1
Status External Pins During Idle Power Down
Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External PSEN PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
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AT89LV51
AT89LV51
Program Memory Lock Bits
chip three lock bits which left unprogrammed programmed obtain additional features listed table below: When lock programmed, logic level sampled latched during reset. device powered without reset, latch initializes random value, holds that value until reset activated. necessary that latched value agreement with current logic level that order device function properly.
Lock Protection Modes(1)
Program Lock Bits
Note:
Protection Type program lock features. MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory, sampled latched reset, further programming Flash disabled. Same mode also verify disabled. Same mode also external execution disabled.
lock bits only erased with chip erase operation.
Programming Flash
AT89LV51 normally shipped with on-chip Flash memory array erased state (i.e. contents=FFH) ready programmed. programming interface accepts either high-voltage (12-volt) low-voltage (5-volt) program enable signal. voltage programming mode provides convenient program AT89LV51 inside user's system while high-voltage programming mode compatible with conventional third party Flash EPROM programmers. AT89LV51 shipped with either High-Voltage Low-Voltage programming mode enabled. respective topside marking device signature codes listed below:
Top-Side Mark
array lock bits. byte-write cycle self-timed typically takes more than Repeat steps through changing address data entire array until object file reached. Data Polling: AT89LV51 features Data Polling indicate write cycle. During write cycle, attempted read last byte written will result complement written data PO.7. Once write cycle been completed, true data valid outputs, next cycle begin. Data Polling begin time after write cycle been initiated. Ready/Busy: progress byte programming also monitored RDY/BSY output signal. P3.4 pulled after goes high during programming indicate BUSY. P3.4 pulled high again when programming done indicate READY. Program Verify: lock bits have been programmed, programmed code data read back address data lines verification. lock bits cannot verified directly. Verification lock bits achieved observing that their features enabled. Chip Erase: entire Flash array lock bits erased electrically using proper combination control signals holding ALE/PROG code array written with "1"s. chip erase operation must executed before code memory re-programmed. Reading Signature Bytes: signature bytes read same procedure normal verification locations 030H 031H, except that P3.6 P3.7 need pulled logic low. values returned are: (030H) indicates manufactured Atmel (031H) indicates 89LV51 (032H) (High-Voltage) (Low-Voltage) programming mode
Signature
AT89LV51 xxxx yyww (030H)=1EH (031H)=61H (032H)=FFH
AT89LV51 xxxx-5 yyww (030H)=1EH (031H)=61H (032H)=05H
AT89LV51 code memory array programmed byte-bybyte either programming mode. program non-blank byte on-chip PEROM Code Memory, entire memory must erased using Chip Erase Mode. Programming Algorithm: Before programming AT89LV51, address, data control signals should according Flash programming mode table Figures program AT89LV51, following sequence should followed: Input desired memory location address lines. Input appropriate data byte data lines. Activate correct combination control signals. Raise EA/VPP 12-V high-voltage programming mode. Pulse ALE/PROG once program byte Flash
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Programming Interface
Every code byte Flash array written entire array erased using appropriate combination control signals. write operation cycle self-timed once initiated, will automatically time itself completion. major programming vendors offer worldwide support Atmel microcontroller series. Please contact your local programming vendor appropriate software revision.
Flash Programming Modes
Mode Write Code Data Read Code Data Write Lock PSEN ALE/ PROG H/12V(1) H/12V P2.6 P2.7 P3.6 P3.7
H/12V
H/12V
Chip Erase Read Signature Byte
H/12V
Notes: signature byte location 032H designates whether should used enable programming.
Chip Erase requires PROG pulse.
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AT89LV51
AT89LV51
Figure Programming Flash
Figure Verifying Flash
AT89LV51
ADDR. OOOOH/OFFFH FLASH PROGRAMMING MODES TABLE P2.0 P2.3 P2.6 P2.7 P3.6 P3.7 XTAL VIH/VPP PROG
FLASH PROGRAMMING MODES TABLE
AT89LV51
DATA
ADDR. OOOOH/OFFFH P2.0 P2.3 P2.6 P2.7 P3.6 P3.7 XTAL DATA (USE PULLUPS)
4-20
4-20
XTAL
PSEN
XTAL
PSEN
Flash Programming Verification Characteristics
21°C 27°C, Symbol VPP(1) IPP(1) 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL(1) tGLGH tAVQV tELQV tEHQV tGHBL
Note:
Parameter Programming Enable Voltage Programming Enable Current Oscillator Frequency Address Setup PROG Address Hold After PROG Data Setup PROG Data Hold After PROG P2.7 (ENABLE) High Setup PROG Hold After PROG PROG Width Address Data Valid ENABLE Data Valid Data Float After ENABLE PROG High BUSY Byte Write Cycle Time
11.5 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL
12.5
Units
48tCLCL 48tCLCL
48tCLCL
Only used 12-volt programming mode.
3-55
Flash Programming Verification Waveforms High Voltage Mode
P1.0 P1.7 P2.0 P2.3 PORT tAVGL ALE/PROG tSHGL
PROGRAMMING ADDRESS VERIFICATION ADDRESS
tAVQV
DATA DATA
tDVGL
tGHDX
tGHAX tGHSL
LOGIC LOGIC
tGLGH
EA/VPP tEHSH P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY)
tELQV
tEHQZ
BUSY
READY
Flash Programming Verification Waveforms Voltage Mode
P1.0 P1.7 P2.0 P2.3 PORT tAVGL ALE/PROG tSHGL EA/VPP tEHSH P2.7 (ENABLE) tGHBL P3.4 (RDY/BSY)
BUSY READY PROGRAMMING ADDRESS VERIFICATION ADDRESS
tAVQV
DATA DATA
tDVGL
tGHDX
tGHAX
tGLGH
LOGIC LOGIC
tELQV
tEHQZ
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AT89LV51
AT89LV51
Absolute Maximum Ratings*
Operating Temperature. -55°C +125°C Storage Temperature. -65°C +150°C Voltage with Respect Ground -1.0 +7.0 Maximum Operating Voltage Output Current 15.0
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
D.C. Characteristics
-40°C 85°C, (unless otherwise noted) Symbol Parameter VIL1 VIH1 VOL1 Input Voltage Input Voltage (EA) Input High Voltage Input High Voltage Output Voltage (Ports 1,2,3)
Condition (Except (Except XTAL1, RST) (XTAL1, RST) -800 -300 0.45 0.45
-0.5 -0.5 VCC+0.9
VCC-0.1 VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45
Units
Output Voltage(1) (Port ALE, PSEN) Output High Voltage (Ports 1,2,3, ALE, PSEN) Output High Voltage (Port External Mode) Logical Input Current (Ports 1,2,3) Logical Transition Current (Ports 1,2,3) Input Leakage Current (Port Reset Pulldown Resistor Capacitance Power Supply Current
0.75 0.75 -650 20/5.5
VOH1
RRST
Test Freq. MHz, 25°C Active Mode, MHz, Idle Mode, MHz,
Power Down Mode(2)
Notes: Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin:10 Maximum 8-bit port: Port 0:26 Ports 1,2, 3:15 Maximum total output pins:71
exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. Minimum Power Down
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A.C. Characteristics
Under operating conditions, load capacitance Port ALE/PROG, PSEN load capacitance other outputs
External Program Data Memory Characteristics
Oscillator Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH Parameter Oscillator Frequency Pulse Width Address Valid Address Hold After Valid Instruction PSEN PSEN Pulse Width PSEN Valid Instruction Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN Address Valid Address Valid Instruction PSEN Address Float Pulse Width Pulse Width Valid Data Data Hold After Data Float After Valid Data Address Valid Data Address Data Valid Transition Data Valid High Data Hold After Address Float High High tCLCL-25 3tCLCL-50 4tCLCL-75 tCLCL-30 7tCLCL-120 tCLCL-25 tCLCL+25 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 tCLCL-8 5tCLCL-80 tCLCL-25 tCLCL-25 3tCLCL-45 3tCLCL-60
Variable Oscillator
Units
2tCLCL-40 tCLCL-25 tCLCL-25
4tCLCL-65
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AT89LV51
AT89LV51
External Program Memory Read Cycle
tLHLL tAVLL PSEN tPLAZ tLLAX PORT
tLLPL
tLLIV tPLIV
tPLPH
tPXAV tPXIZ tPXIX
INSTR
tAVIV PORT
External Data Memory Read Cycle
tLHLL tWHLH PSEN tLLDV tRLRH tLLWL tAVLL PORT tLLAX tRLAZ
DATA
tRLDV
tRHDZ tRHDX
FROM INSTR
FROM
tAVWL tAVDV PORT
P2.0 P2.7 FROM FROM
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External Data Memory Cycle
tLHLL tWHLH PSEN tLLWL tAVLL PORT tWLWH
tLLAX tQVWX tQVWH
DATA
tWHQX
FROM INSTR
FROM
tAVWL PORT
P2.0 P2.7 FROM FROM
External Clock Drive Waveforms
tCHCX
tCHCX tCLCH tCHCL
0.45 tCLCX tCLCL
External Clock Drive
-40°C 85°C Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Time Rise Time Fall Time 83.3 62.5 Units
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AT89LV51
AT89LV51
Serial Port Timing: Shift Register Mode Test Conditions
(VCC Load Capacitance Symbol tXLXL tQVXH tXHQX tXHDX tXHDV Parameter Serial Port Clock Cycle Time Output Data Setup Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge Input Data Valid Variable Oscillator 12tCLCL 10tCLCL-133 2tCLCL-117 10tCLCL-133 Units
Shift Register Mode Timing Waveforms
INSTRUCTION CLOCK
tXLXL tQVXH
WRITE SBUF OUTPUT DATA CLEAR INPUT DATA
tXHQX
VALID VALID VALID VALID VALID
tXHDV
VALID VALID
tXHDX
VALID
Testing Input/Output Waveforms
TEST POINTS 0.45
Float Waveforms
VLOAD+ VLOAD VLOAD -0.1
-0.1 Timing Reference Points
Note:
Inputs during testing driven logic 0.45 logic "0". Timing measurements made logic logic "0."
Note:
timing purposes, port longer floating when change from load voltage occurs. port begins float when change from loaded VOH/VOL level occurs.
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AT89LV51
(mA)
TYPICAL (ACTIVE)
(MHz)
AT89LV51
(mA)
TYPICAL (IDLE)
(MHz)
3-62
AT89LV51
AT89LV51
AT89LV51
TYPICAL VOLTAGE POWER DOWN (85°C)
3.0V
4.0V
VOLTAGE
5.0V
6.0V
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Ordering Information
Speed (MHz) Power Supply Ordering Code AT89LV51-12AC AT89LV51-12JC AT89LV51-12PC AT89LV51-12QC Package 40P6 Operation Range Commercial (0°C 70°C)
Ordering Information
Package Type
40P6
Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) Lead, Plastic J-Leaded Chip Carrier (PLCC) Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Lead, Plastic Gull Wing Quad Flatpack (PQFP)
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AT89LV51

Compatible with MCS-51Products Kbytes In-System Reprogrammable Flash M

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