Parallel E2PROM Memory word) Gate Array Logic Design Voltage Operation

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Parallel E2PROM Memory word) Gate Array Logic Design Voltage Operation

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Logic
Parallel E2PROM Memory word) Gate Array Logic Design Voltage Operation (2.7 Volts) Single Voltage Supply Operation Performs Page Write Function Manufactured Using Power CMOS Technology Write Erase Time: Maximum Temperature Range from -40°C 85°C Immunity Volts High Reliability Endurance: 10,000 Write/Erase Cycles Years Data Retention Ideal Portable, Secure Applications Including PCMCIA Cards, Smart Cards, Tags, Keys, etc.
Logic Serial Parallel E2PROM with Gate Array
Block Diagram
POWER RESET
EEPROM
AT88SC150 AT88SC200 AT88SC220 AT88SC250 AT88SC410 AT88SC450 AT88SC8100 AT88SC1610
GATE ARRAY LOGIC GATES LOGIC
Preliminary
Description
AT88SCXXX provides bits E2PROM (Electrically Erasable Programmable Read Only Memory) with CMOS usable gates personalization, security, glue logic. AT88SCXXX ideal portable applications requiring E2PROM with custom logic. outputs AT88SCXXX sink source There buffer sites which configurable inputs, outputs, bidirectional, CMOS operation. device also provides pull-down pull-up capability floating signals. AT88SCXXX manufactured using low-power CMOS technology features internal high voltage pump single voltage supply operation. devices guaranteed 10,000 erase/write cycles years data retention.
0319B
Atmel customer personalize gate array described Figure customer's design accepted three formats: Functional Description Schematic
Compatible Netlist Compatible netlists generated from MentorTM, CadenceTM, ViewlogicTM. personalized devices available wafer, die, standard packages.
Logic Family
Device Name AT88SC150 AT88SC200 AT88SC220 AT88SC250 AT88SC410 AT88SC450 AT88SC8100 AT88SC1610 EEPROM Bits 1,024 2,048 2,048 2,048 4,096 4,096 8,192 16,384 Number Usable Gates 5,000 2,000 5,000 1,000 5,000 10,000 1,000 Number Package Type PQFP/TQFP/PLCC PDIP/SOIC PQFP/TQFP/PLCC PQFP/TQFP/PLCC PDIP/SOIC PQFP/TQFP/PLCC PQFP/TQFP/PLCC PDIP/SOIC
Figure AT88SCXXX Design Flow
Customer
Functional Description, Schematics, Specifications, Compatible Netlist Test Vectors
Schematic Capture Design Synthesis Simulation
Atmel
Preliminary Design Review
Customer
Agreement Netlist, Simulation Results Electrical/Product Specification
Atmel
Test Program Generation
Atmel
Customer
Final Design Review
Atmel
Customer
Deliver Design Verification Units (DVS)
Atmel
Cadence, Mentor, Viewlogic trademarks others.
Logic
Logic
Absolute Maximum Ratings*
Operating Temperature .-55°C +125°C Storage Temperature .-65°C +150°C Voltage with Respect Ground .-0.6 +0.6 Maximum Operating Voltage .6.1
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics
TAMB -40°C +85°C, 10%, (unless otherwise specified)
Symbol Characteristics Supply Current (tAMB 25°C) (open output buffers) Supply Current during E2PROM Program (tAMB 25°C). Input Voltage CMOS Input Voltage Input High Voltage CMOS Input High Voltage Output Level (IOL Output High Level (IOH Leakage Current Unit
ICCP
Packaging
Atmel logic memory available wafer, die, standard packaging. Back grinding option.
Packaging Options
Package Type PQFP TQFP PLCC PDIP SOIC Tested Tested Count 100, 120, 100, 120, Waffle Packs Wafer Form

Parallel E2PROM Memory word) Gate Array Logic Design Voltage Operation

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