Converting FPGAs PLDs Atmel Gate Arrays Atmel only companies that
|
|
|
Top Searches for this datasheet
CMOS ASIC
Converting FPGAs PLDs Atmel Gate Arrays
Atmel only companies that designs manufactures field programmable gate arrays (FPGAs), programmable logic devices (PLDs) high performance gate arrays. Atmel offers seamless, direct conversion path designs implemented most PLDs FPGAs gate array families. potential benefits system designer such capability fourfold: Component cost savings. Atmel's conversion process will convert single FPGA into lower cost gate array that pin-for-pin compatible replacement. Board space savings. Atmel converts true gate array, hardwired FPGA/PLD. Multiple FPGAs PLDs converted consolidated into single gate array, reducing system component count providing even more cost savings. Enhanced performance. Conversion gate array grants designer access macrocells functions contained cell library. Included higher order logic functions, inclusion SRAM, other buffers testability improvement circuitry that cannot realized FPGA PLD. Gate array routing schemes allow greater degree flexibility optimize timing performance logic area. Reduction design cycle time. ASIC design using programmable logic migrated gate array production without time cost redesign.
FPGA/PLD Gate Array Conversion Application Note
cases, Atmel uses existing FPGA design database that little additional engineering effort required from customer. This application note discusses some factors consider when deciding convert, describes conversion process, details required information selected FPGA products.
Density
Gate Array FPGA CPLDs PALs
Simple State Machines Controller Logic State Machines Counters Memory Control Interfaces Math Functions Apps FIFOs Buffers High Gate Count Logic High Volume Cost
0145C
ATL80 Array Organization CMOS
Device Number ATL80/2 ATL80/5 ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/150 ATL80/220 ATL80/280 ATL80/350 ATL80/450 ATL80/600
Notes:
Gates 2,000 5,000 10,000 17,000 26,000 39,000 50,000 75,000 94,000 150,000 220,000 280,000 350,000 450,000 600,000
Routable Gates 1,000 3,000 6,000 10,200 15,600 23,400 30,000 45,000 60,000 75,000 110,000 140,000 175,000 225,000 300,000
Count
Pins
Gate(1) Speed
Nominal input NAND gate with volts.
ATLV Array Organization
Device Number ATLV2 ATLV3 ATLV5 ATLV7 ATLV10 ATLV15 ATLV20 ATLV35
Notes:
Gates 2,000 3,000 5,000 7,000 10,000 15,000 22,000 35,000
Routable Gates 1,400 1,600 2,800 4,400 6,600 8,000 12,000 18,000
Count
I/O(1) Pins
Gate(2) Speed
Absolute maximum pins maximum count minus Additional power ground pins assumed required support simultaneous switching outputs count increases. Nominal input NAND gate with volts.
CMOS ASIC
CMOS ASIC
Programmable Logic Gate Array
Programmable logic devices have enjoyed tremendous popularity growth over last several years, primarily because user saves both time money. Designers work with multiple design tools that inexpensive platforms. Designs implemented hours modified easily, allowing system performance evaluation same week. This instant feedback allows designers validate system operation rectify errors without additional expense. Programmable logic devices provide ideal solution moderate production volumes fast prototyping more complex logic designs. volumes increase, however, programmable devices become prohibitively expensive. Gate arrays provide efficient implementation design. They offer superior performance, higher density, lower cost-per-gate production volumes when compared programmable logic devices. Design tools that support gate arrays typically more comprehensive expensive than FPGA/PLD design tools. However, many ASIC design platforms support FPGA design. ability simulate both programmable device gate array same design environment allows designer compare verify conversion. However, while gate array prototypes delivered days weeks, that still much longer period than verification cycle programmable logic device. Gate array designs typically require nonrecurring expense design implementation, design revisions require additional time expense. Time Market Versus Cost Reduction. Using programmable device logic verification prototyping then converting gate array gives designer best both worlds fast, accurate design cycle cost component production. Higher Performance. Gate arrays have lower standby operating current, plus offer greater speed than FPGA/ PLD. designer also greater selection buffer types, drive currents, wide selection higher order logic memory (SRAM) functions. Integration. Converting several FPGAs PLDs consolidating logic into single gate array uses less printed circuit board space, reduces component count, consumes less power, improves reliability system.
Atmel Conversion Process
Summary Conversion Process Atmel's FPGA/PLD gate array conversion process intended minimize amount additional engineering effort required from system designer. Figure outlines conversion process flow. database inputs conversion process flow will vary depending upon manufacturer FPGA(s) PLD(s) covered following sections. conversion programmable device's netlist into Atmel cell library netlist accomplished SynopsysTM. Synopsys tools read variety formats, including preferred formats EDIFand VerilogTM. Figure outlines process which Synopsys converts FPGA netlist into Verilog-XLformat. database input proprietary Atmel mapping file translation into Atmel cells. When design mapped entirety, Verilog netlist Atmel cells produced. this point design process (Preliminary Design Review through Final Design Review, outlined later this application note) same other gate array design.
Convert?
There four instances when converting from programmable logic device gate array offers user direct benefit. Save Money High Volumes. cost year's supply programmable devices approximates cost nonrecurring expense plus initial year's supply gate array device, serious consideration should given conversion. After nonrecurring expense amortized, cost savings become even more dramatic.
Database Requirements your logic design philosophy includes conversion progammable device gate array, effort should dedicated generation test vectors during design programmable device. While test vectors required verify programmable logic device, gate array cannot verified without them. final approval vectors used falls upon original designer; best served produce verify test vectors prior database submission than attempt reconstruct them after fact. designer will supply database that unique specific choice FPGA/PLD part conversion process, well information that independent FPGA/PLD choice. exact files required from system used develop given manufacturer's device listed following sections, however, general list database requirements include: Netlist. preferred netlist format EDIF, Verilog also acceptable. Other formats, such those generated Viewlogicor Mentorplatforms, will ultimately converted EDIF with Synopsys. Test Vectors. vectors must same five groups (Input, Output, Tri-stateTM, Bi-directional, Enable) have stated purpose. Outputs sampled once clock cycle cycle point. Test vectors must include wafer probe speed" final test. speed" with certain critical paths identified testing speed". Test vectors must pass Atmel's Test Vector Checker (tvc), tool provided with libraries verify format vector set.
Figure FPGA/PLD Gate Array Conversion
Customer
Database Acceptance
Atmel
Database Conversion, Simulation Verification
Atmel
Customer
Preliminary Design Review (PDR)
Atmel
Physical Design Verification
Atmel
Customer
Final Design Review (FDR)
Atmel
Customer
Prototype Delivery
Atmel
CMOS ASIC
CMOS ASIC
Specifications. Operating conditions voltage temperature System loading requirements Operating clock speed number clocks definition including enable Tristate bi-directional buffers Identification critical paths Definition asynchronous behavior Documentation. Full hierarchical schematics Clock tree reset diagram Timing diagrams showing relationship clocks data applied valid outputs Database requirements will depend upon manufacturer design platform FPGA device. These requirements will also dependent whether multiple devices combined into single gate array, performance expectations. actual approach that Atmel takes conversion process will driven these items. Atmel's gate array families allow designer flexibility placement. Eight power ground pins, located corners die, only dedicated pins. other pads fully programmable input, output, bidirectional, Tri-state, power, ground.
Figure FPGA Conversion
FPGA Netlist (EDIF) Synopsys
Verilog Netlist
Mapping File
Hierarchical Verilog Netlist
Synopsys
Flattened Verilog Netlist
Verilog Netlist Atmel Cells
Converting FPGAs
FPGAs similar gate array both design physical implementation, making conversion process relatively simple. Most FPGAs only logic blocks which typically found most gate array cell libraries. This allows FPGA netlist mapped directly into gate array primitive cells, simulated, validated, routed standard gate array design flow. optimization that required meet performance objectives also implemented. Mentor Files .MIF (Mentor Interface File Netlist) .LOG (Simulation File) .LIST (Simulation Listing File) .FORCE (Simulation Force File) Synopsys files Altera- .RPT files Simulation/Test Vector Format
Required Database
Design Database Format EDIF 2.0.0 Viewlogic Files .CMD (Simulator Command File) .EDN (EDIF Netlist) .SCH (Schematics) .SYM (Symbols) .WIR (Wire List) ViewdrawTM.INI CadenceVerilog-XL Files EDIF Netlist
ASCII format vector line, time stamp left column Print-on-change format Bi-directional signals must defined input output 1MHz wafer probe at-speed final test Verified Atmel's Test Vector Checker (tvc) Tables list recommended Atmel gate arrays conversion from various ActelTM, Alteraand Xilinxprogrammable devices.
CMOS ASIC
CMOS ASIC
Table Actel FPGA/Atmel Gate Array Cross Reference
Actel FPGA Equivalent Usable Gates Pins Target Atmel(1) Gate Array ATL80 Series 11010 1,200 ATL80/2 ATL80/5 ATL80/5 ATL80/10 ATL80/5 ATL80/10 ATL80/15 ATL80/25 ATL80/25 ATL80/40 ATL80/10 ATL8015 ATL80/15 ATL80/25 ATL80/40 ATL80/50 ATL80/50 ATL80/75 ATL80/95 ATL80/150 ATLV Series ATLV2 ATLV3 ATLV3 ATLV5 ATLV5 ATLV7 ATLV7 ATLV10 ATLV15 ATLV20 ATLV5
1020
2,000
2
1225
2,500
1240
4,000
3
1280
8,000
1415
1,500
1425
2,500
ATLV7 ATLV10 ATLV15 ATLV20 ATLV20 ATLV35
1440
4,000
1460
6,000
14100
10,000
Note:
Target array dependent number pins used, pinout.
Table Xilinx EPLD/FPGA Atmel Gate Array Cross Reference
Xilinx EPLD Equivalent Usable Gates Pins Target Atmel(1) Gate Array ATL80 Series XC7236A 1,600 ATL80/2 ATL80/5 XC7272A 3,200 ATL80/5 ATL80/10 XC7318 ATL80/2 ATL80/5 XC7336 1,000 ATL80/2 ATL80/5 XC7354 2,200 ATL80/5 ATL80/10 XC7372 3,000 ATL80/10 ATL80/15 XC73108 4,600 ATL80/15 ATL80/25 ATL80/40 XC73144 6,200 ATL80/25 ATL80/40 ATL80/50 ATL80/75
Note: Target array dependent number pins used, pinout.
ATLV Series ATLV2 ATLV3 ATLV3 ATLV5 ATLV2 ATLV3 ATLV2 ATLV3 ATLV3 ATLV5 ATLV5 ATLV7 ATLV10 ATLV15
ATLV15 ATLV20 ATLV35
CMOS ASIC
CMOS ASIC
Table (continued). Xilinx EPLD/FPGA Atmel Gate Array Cross Reference
Xilinx FPGA Equivalent Usable Gates Pins Target Atmel(1) Gate Array ATL80 Series XC2064/L XC2018/L XC3020, XC3120 0.6K 1.0K 1.0K 1.5K 1.3K 1.8K ATL80/5 ATL80/10 ATL80/5 ATL80/10 XC3030, XC3130 2.0K 2.7K ATL80/10 ATL80/15 XC3042, XC3142 3.7K ATL80/15 ATL80/25 XC3064, XC3164 4.0K 5.5K ATL80/25 ATL80/40 XC3090, XC3190 5.0K 7.5K ATL80/40 ATL80/50 XC3195 6.0K 9.0K ATL80/50 ATL80/75
Note: Target array dependent number pins used, pinout.
ATLV Series ATLV3 ATLV5 ATLV3 ATLV5 ATLV5 ATLV7 ATLV7 ATLV10 ATLV10 ATLV15 ATLV15 ATLV20 ATLV20 ATLV35
Table (continued). Xilinx EPLD/FPGA Atmel Gate Array Cross Reference
Xilinx FPGA Equivalent Usable Gates Pins Target Atmel(1) Gate Array ATL80 Series XC4002A 1.6K 2.0K ATL80/5 ATL80/10 XC4003, XC4003A 2.5K 3.0K ATL80/10 ATL80/15 XC4003H 2.5K 3.0K ATL80/50 ATL80/75 XC4004A 3.2K 4.0K ATL80/15 ATL80/25 XC4005, XC4005A 4.0K 5.0K ATL80/15 ATL80/25 XC4005H 4.0K 5.0K ATL80/75 ATL80/95 XC4006 5.0K 6.0K ATL80/25 ATL80/40 XC4008 6.5K 8.0K ATL80/40 ATL80/50 XC4010, XC4010D 8.0K 10.0K ATL80/50 ATL80/75 XC4013 10.0K 13.0K ATL80/75 ATL80/95 XC4020 16.0K 20.0K ATL80/95 ATL80/150 XC4025 20.0K 25.0K ATL80/150 ATL80/220
Note: Target array dependent number pins used, pinout.
ATLV Series ATLV3 ATLV5 ATLV5 ATLV7 ATLV20 ATLV35 ATLV7 ATLV10 ATLV7 ATLV10 ATLV35
ATLV10 ATLV15 ATLV15 ATLV20 ATLV20 ATLV35 ATLV35
ATLV35
ATLV35
CMOS ASIC
CMOS ASIC
Table Altera FPGA/PLD/Atmel Gate Array Cross Reference
Altera 5032 5064 5128, 5128A 5130 Equivalent Usable Gates 1,200 2,400 Pins Target Atmel(1) Gate Array ATL80 Series 5000ATL80/2 ATL80/2 ATL80/5 ATL80/10 ATL80/5 ATL80/10 ATL80/5 ATL80/10 ATL80/5 ATL80/10 ATL80/5 ATL80/10 ATL80/15 ATL80/25 ATL80/25 ATL80/40 ATL80/25 ATL80/40 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATLV3 ATLV5 ATLV5 ATLV7 ATLV3 ATLV5 ATLV5 ATLV7 ATLV10 ATLV Series ATLV2 ATLV2
2,400
5192, 5192A
3,750 1,500
7000
7096
7128E
2,500
7160E
3,200
ATLV10
7192E
3,800
ATLV10
7256E
5,000
128,
ATLV10 ATLV15 ATLV20 ATLV35
Note:
Target array dependent number pins used, pinout.
Table (continued). Altera FPGA/PLD/Atmel Gate Array Cross Reference
Altera Equivalent Usable Gates 9320 6,000 Pins 112, 128, Target Atmel(1) Gate Array ATL80 Series ATLV Series ATLV10 ATLV15 ATLV20 ATLV35
9000
ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/150 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/150
9400
8,000
135, 128,
ATLV10 ATLV15 ATLV20 ATLV35
9480
10,000
113, 142, 171,
ATLV20 ATLV35
9560
12,000
149, 187,
ATLV20 ATLV35
Note:
Target array dependent number pins used, pinout.
CMOS ASIC
CMOS ASIC
Table (continued). Altera FPGA/PLD/Atmel Gate Array Cross Reference
Altera FPGA Flex 80008282, 8282A, 8282AV, 8282AV 8452, 8452A Equivalent Usable Gates 2,500 Pins Target Atmel(1) Gate Array ATL80 Series ATL80/5 ATL80/10 ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/25 ATL80/40 ATL80/50 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/75 ATL80/95 ATL80/150 ATL80/220 ATL80/280 ATL80/350 ATL80/450 ATLV Series ATLV5
4,000
ATLV7 ATLV10 ATLV15
8636A
7,000
106,
ATLV7 ATLV10 ATLV15
8820, 8820A
9,000
116,
ATLV20
81188, 81188A
12,000
144,
ATLV20
81500, 81500A
16,000
177,
ATLV20
8050M
50,000
ATLV35
Note:
Target array dependent number pins used, pinout.
Atmel FPGAs/PLDs Required Database specific file requirements converting from Atmel FPGA quite straightforward. Table cross reference Atmel PLD/FPGA gate arrays. JEDEC Files (PLD) ABEL CUPL LOGIC Viewlogic File (PLD, FPGA) .GDF (Graphic File) Table Atmel FPGA/Atmel Gate Array Cross Reference
Atmel PLD/FPGA AT22V10 AT18V8 ATV750 ATV2500 Equivalent Usable Gates 2,500 Pins ATL80/2 ATL80/2 ATL80/2 ATL80/2 ATL80/5 ATL80/5 ATL80/10 Target Atmel(1) Gate Array ATL80 Series ATLV Series ATLV2 ATLV2 ATLV2 ATLV5
.TDF (Text File) .HIF, .FIT (Fitter File) .POF (Programmer Object File) .SNF (Simulation Netlist File) .VEC (Simulation Vector File) File (FPGA) .CDB
AT3000 ATV5000
3,000 5,000
ATLV5 ATLV7
FPGA
AT6002
2,000
ATL80/5 ATL80/10 ATL80/15 ATL80/5 ATL80/10 ATL80/25 ATL80/10 ATL80/15 ATL80/25 ATL80/15 ATL80/25 ATL80/40 ATL80/50
ATLV5 ATLV7
AT6003
3,000
ATLV7 ATLV10
AT6005
5,000
ATLV7 ATLV10
ATL6010
10,000
ATLV15 ATLV20
Note:
Target array dependent number pins used, pinout.
CMOS ASIC
CMOS ASIC
Converting PLDs
different methods used when converting from PLDs gate arrays, each which intended provide optimal solution specific concern. These methods deterministic timing matching. Each method involves trading gate array utilization matching timing original design, seen Table Deterministic Conversion PLDs have uniform, deterministic architecture. Every signal within traverses constant length path avoids race conditions. converted design drop-in replacement, then must meet same specifications original design, including minimum maximum signal arrival times, set-up hold times. These system requirements become particularly critical when driving chip with positive hold time. Figure demonstrates, reduction clock-to-output time will cause hold time failure within system. Table Gate Array Conversion Methodologies
Conversion Methodology Deterministic Timing Matching Gate Utilization Moderate Lowest Timing Match Moderate High
Using deterministic approach, gate array logic implemented using blocks similar structure those used PLD, i.e., product terms terms. This methodology eliminates possibility introducing timing problem described above moderately efficient terms gate utilization timing matching. Timing Matching Conversion design completely synchronous, timing optimization techniques used find minimum propagation delay each path. This information then used adjust delay paths until maximum signal arrival time path, implemented gate array, matches that PLD. name this approach implies, this method offers best timing match between gate array PLD, expense additional buffers adjust specific path timing.
Comments Eliminates internal timing concerns. Eliminates both internal system timing concerns.
Figure System Timing Concerns (Positive Hold Times)
System Clock Output Hold Time Next Chip
discussed earlier, type conversion approach that selected will determine many particular onto array. Atmel's ATL80/5 array, featuring 3,000 routable gates pads, used target array following example. deterministic conversion, percentage utilization given formula: utilization (0.15x 0.008y 1.5z) where number product terms, number pins, number registers. timing matching conversion, percentage utilization given utilization (0.35x 0.08y 1.5z)
Figure shows range number designs which will onto ATL80/5, selected members Atmel's ATLV family both deterministic timing matching approaches. There will often wide range utilization within given system configuration. value shown "median" will provide good benchmark when considering converting multiple PLDs into gate array. maximum number shown typically function number pins required.
Figure Number Specific Designs which will ATL80/5 (Min, Median, Max)
22V10, Deterministic Median 22V10, Timing Matching V750, Deterministic V750, Timing Matching
CMOS ASIC
V2500, Timing Matching
V2500, Deterministic
CMOS ASIC
Gate Array Implementation
After database acceptance, design database converted into equivalent netlist primitive cells from Atmel's gate array library. vectors from original FPGA design also converted used functional simulation vectors validate gate array netlist. these vectors used perform timing simulation form core gate array tester program, vitally important that accurate complete vector provided. After FPGA databases have been converted validated, additional circuitry, such memory blocks, testability improvement elements, higher order logic functions, incorporated into netlist. optimization that necessary match timing improve performance performed this point well. this point, boundary internal scan added ATPG vectors generated. Preliminary Design Review then held with customer review approve results design conversion. Preliminary Design Review (PDR) following items reviewed PDR: Confirm Netlist Checker (v3) Test Vector Checker (tvc) files correct buffer listing bonding diagram Preliminary testability compiler report Route clock tree analysis worst case best case delay Verilog simulation at-speed -nominal, worst case, best case (with timing violations) Review critical path information (tSU, tHOLD, tPD) -Verilog Veritime estimates electrical specifications Electromigration calculation routed, post-route simulation performed, checks performed verify conformance with electrical design rules, confirm Logic Versus Schematic (LVS) correct. held with customer review approve post route data, authorize mask making prototype fabrication. last joint review between Atmel customer before committing prototypes. Prior this meeting, both Atmel customer will have reviewed post-route Verilog-XL simulation incorporating back annotation data. customer receive back annotation data complete post-route simulation their systems. Atmel guarantees silicon performance equal better than that predicted post-route Verilog-XL simulations. items reviewed follows: Updates cell mapping timing any) Post-route netlist check (v3) -post-route netlist changes Post-route timing simulation specification -review clock timing speed -clock skew required) -listing timing warnings with explanation Static path analysis specified) Electromigration calculation Bonding diagrams list -bond plot LVS/DRC/ERC
Prototype Delivery Atmel will deliver prototypes ceramic TQFP packages customer. units verify functionality electrical performance gate array.
Final Design Review (FDR) Beyond this point, design process follows that traditionally designed gate array. cells placed
Synthesis from Hardware Description Language (HDL) There been increase HDLs design FPGAs PLDs more design platforms offer this capability. most popular languages VHDL Verilog-HDL. Using logic synthesis technique, behavioral level description FPGA mapped into functionally equivalent gate array netlist. Both hardware description languages supported Synopsys Design Compiler. This FPGA/PLD gate array conversion methodology requires least amount data conversion allows flexibility incorporate such features memory, testability, higher order logic functions into gate array. This technique also effective when need consolidate several FPGA designs into gate array exists. Synthesis from offers most efficient utilization gate array, expense timing matching. Should user require them, VHDL descriptions converted FPGAs PLDs, well gate array implementation, provided exporting netlists through Synopsys. Testability Improvement Automatic Test Pattern Generation incorporation testability improvement circuitry into ASIC design becomes more important density design increases. same said conversion consolidation large numbers dense FPGAs PLDs into gate array. insertion scan paths within ASIC testing ATPG provide easy means screening manufacturing-related defects during testing, with relatively small silicon usage penalty. Using ATPG only supplement functional test vectors, replacement. process consists replacing existing flip-flops with scan flip-flops connecting them form scan chains. input output must identified each scan chain. general, scan chains should exceed flipflops length. Thus, design with flip-flops, input pins their corresponding output pins must identified. Existing pins multiplexed this design limited. Additional pins required Test Enable (TE) signal Test Mode (TM) signal. used control flip-flops, placing them either normal mode scan mode. required bypass violations testability guidelines, example which would gated clocks. During testing, flip-flops scan chains must toggle same clock. gated clocks exist design, logic must designed that bypasses this gating when Test Mode active. Since Test Mode active only during ATPG test, basic function design unaffected. Table outlines other testability rules suggested workarounds utilizing Test Mode signal. When test guidelines followed, testability insertion vector generation easily accomplished. Past experience shown extremely high fault coverage 99%) with small ATPG vector sets. these rules followed closely, incorporating scan ATPG require several weeks. highly recommended that FPGA designed using rules Table customer intends someday convert gate array scan/ATPG.
CMOS ASIC
CMOS ASIC
Table Synopsys Test Compiler Guidelines
Testability Rule Synchronous Design cross coupled gates unregistered feedback Single Edge Clocking Effects Infraction Associated logic untestable Workaround Break feedback path with test mode
Clocked device allowed scan chain reduced fault Clocked device allowed scan chain reduced fault coverage allowed scan chain, reduced fault coverage
test mode, create single edge clocking with inverters MUXs data disable flip-flops instead clock enables, disable gating test mode alternate test methods, force latches transparent mode with test mode Reset OR'd with test mode
Clock Gating
Latches
Single External Reset asynchronous resets presets generated chip combinational logic reset path Internal Tri-state Buses
allowed scan chain, reduced fault coverage
Reduced fault coverage, possible Tri-state contention during scan test
MUXs gates, insert gating controls prevent contention
Direct Connections
Dynamic Hazard
Abel, Actel, Act, Altera, Cupl, Cadence, Cadence/Concept, EDIF, Flex, Logic, Max, Mentor, Synopsys, Tri-state, Verilog, Verilog-XL, Viewlogic Xilinx registered trademarks others.
Other recent searches
UP04215G - UP04215G UP04215G Datasheet
ADSP-TS101S - ADSP-TS101S ADSP-TS101S Datasheet
ADSPTS101S - ADSPTS101S ADSPTS101S Datasheet
2SD1996 - 2SD1996 2SD1996 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
