drawn (0.6 effective) gate length combined with triple level metal pro
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ATL80
drawn (0.6 effective) gate length combined with triple level metal provides outstanding speed/density performance. ATL80 arrays operate volts volts lowpower applications. ATL80 series also operate mixed voltage environment. Design translation existing ASIC, FPGA designs provide easy alternate sourcing with equivalent performance. Product testability improved using techniques such serial boundary scan, ATPG, built-in self test JTAG. ATL80 arrays screened MIL-STD-883.
Description
high-performance ATL80 Series CMOS gate arrays offer superior system performance, flexibility, testability board utilization. ATL80 gate arrays employ advanced technology µ-drawn, triple-level metal, Si-gate, CMOS technology processed U.S.-based, manufacturing facility. Atmel's efficient routing scheme combined with tight spacing three metal layers allows Atmel provide more gates faster speeds. With fine pitch bond pads standard feature, high gate arrays easily accommodated. ATL80 gate array have volt volt core, combined with volt and/or volt same chip. Atmel's personalized accept volt input signal into volt buffer. Atmel's flexible design system uses industry design standards compatible with popular CAD/CAE software hardware packages. macro cell libraries upward compatible with existing libraries design utilities.
ATL80 Series Gate Arrays Micron ATL80/2 ATL80/5 ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/150 ATL80/220 ATL80/280 ATL80/350 ATL80/450 ATL80/600
ATL80 Array Organization
Device Number ATL80/2 ATL80/5 ATL80/10 ATL80/15 ATL80/25 ATL80/40 ATL80/50 ATL80/75 ATL80/95 ATL80/150 ATL80/220 ATL80/280 ATL80/350 ATL80/450 ATL80/600
Note:
Gates 2,000 5,000 10,000 17,000 26,000 39,000 50,000 75,000 94,000 150,000 220,000 280,000 350,000 450,000 600,000
Routable Gates 1,000 3,000 6,000 10,200 15,600 23,400 30,000 45,000 60,000 75,000 110,000 140,000 175,000 225,000 300,000
Count
Pins
Gate(1) Speed
Nominal Input NAND Gate With
ATL80 Design
Design Systems Supported
Atmel supports major CAE/CAD software systems with complete macro cell libraries (symbols, timing function), well utilities checking netlist accurate pre-route delay simulations. Atmel uses Cadence's Verilog-XL golden simulator. following design systems supported: Cadence/Composer Mentor Viewlogic Synopsys
Design Flow
While Atmel provides four options implementing gate array design, they have same flow. Data base acceptance first milestone. This occurs when Atmel receives accepts complete design data base. Preliminary design review occurs when performance design based Cadence simulation. Final design review last review design before making masks. back annotation data incorporated into simulations. After final design review masks released prototypes, ceramic packages, delivered.
ATL80 Gate Array Design Flow
Customer
Atmel Cell Library Gate Array Design Translation Design FPGA/PLD Synthesis Conversions -VHDL -Verilog-HDL
Atmel
Data Base Acceptance
Atmel
Simulation Verification
Atmel
Customer
Preliminary Design Review
Atmel
Physical Design, Simulation Verification
Atmel
Customer
Final Design Review
Atmel
Customer
Prototype Delivery
Atmel
ATL80
ATL80
Design Options
Schematic Capture
Schematic capture simulation performed customer using Atmel supplied macro cell library. customer also receive complete back annotation delay data post-route simulation. NEC, Motorola, Fujitsu, SMOS, others) into gate arrays. These designs have been optimized speed, gate count, modified logic memory, replicated pin-for-pin compatible, drop-in replacement.
VHDL/Verilog-HDL
Atmel accept Register Transfer Level (RTL) designs VHDL (MIL-STD-454, IEEE 1076) VerilogHDL format. Atmel fully supports Synopsys VHDL simulation well synthesis. Design VHDL Verilog-HDL preferred method performing gate array design.
FPGA Conversions
Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx, Actel, Altera, Atmel) into gate arrays. design optimized speed power consumption, modified logic memory replicated pin-for-pin compatible, drop-in replacement. Atmel frequently combines several devices onto single gate array.
ASIC Design Translation
Atmel successfully translated dozens existing designs from most major ASIC vendors (LSI Logic, Oki,
ATL80 Series Cell Library
Atmel's ATL80 series gate arrays cells from accurately modeled highly flexible library. cell library contains over hard-wired data path elements been characterized extensive SPICE modeling transistor level verified through measurements made fabricated test arrays. Characterization been performed over military temperature voltage ranges ensure that simulation accurately predicts performance finished product. Atmel continually expanding ATL80 series cell library with both soft hard macros. Check with your sales representative most recent additions.
Cell Guide
Buffers Inverters Buffer Buffer Tri-state Buffer Tri-state Buffer with Enable Buffer Buffer Buffer Buffer Buffer Delay Buffer Delay Buffer Delay Buffer AND, NAND, Gates input input with High Drive input input with High Drive input input with High Drive input input NAND Dual 2-input NAND input NAND with High Drive input NAND input NAND with High Drive input NAND input NAND with High Drive input NAND input NAND with High Drive input NAND input NAND with High Drive input NAND input NAND with High Drive input Dual input input with High Drive input input with High Drive input input with High Drive input input input input with High Drive input input with High Drive input input with High Drive input Inverter Dual Inverter Quad Inverter Quad Tristate Inverter Inverter Tri-state Inverter Inverter Inverter Inverter Inverter Voltage Level Shifter Voltage Level Shifter with Power Supply Isolation
ATL80
ATL80
Cell Guide
Multiplexers with High Drive Inverting Buffered Inputs Inverting Buffered Inputs, High Drive with Enable Quad with Enable Quad Inverting Buffered Inputs Inverting Buffered Inputs, High Drive AND/OR, OR/AND Gates input INVERT input INVERT with High Drive input INVERT input INVERT with High Drive input INVERT with inputs input INVERT input INVERT with High Drive Exclusive OR/NOR Gates Adder with Buffered Outputs input Carry Lookahead input Exclusive Decoders Decoder Decoder with Enble Flip-flops/Latches Flip-flop Flip-flop with Clear/Preset Flip-flop with Clear Flip-flop with Reset Flip-flop with Flip-flop with Set/Reset Flip-flop Flip-flop with Clear Flip-flop with Clear/Preset LATCH LATCH with Complementary Outputs Inverted Gate Signal LATCH with High Drive Complementary Outputs LATCH with Reset LATCH with LATCH with Reset Decoder with Enable input Exclusive with High Drive input Exclusive input Exclusive with High Drive input INVERT input INVERT with High Drive input INVERT input INVERT with High Drive input INVERT with inputs input INVERT Buffered Inputs Buffered Inputs, High Drive with High Drive with Enable Buffered Inputs High Drive
Cell Guide
Scan Cells Set-scan Flip-flop Set-scan Flip-flop with Reset Scan Flip-flop with Options Input, Output, Bidirectional, Tristate Output, Internal Clock Driver Oscillator Output Drive Value Programmable from increments with Slew Rate Control CMOS Operation Schmitt Trigger (Bidirectional, Input) Inverting Non-inverting Input Buffers (Bidirectional, Input) Pullup Resistor 372K Pulldown Resistor 3.5K 108.5K 74XX Series Soft Macros cells available Scan Flip-flop with Reset Scan Flip-flop with Preset
ATL80
ATL80
CMOS/TTL Input Interface Characteristics
Interface CMOS Logic High Minimum Minimum Logic Maximum Maximum Switchpoint Typical Typical
Absolute Maximum Ratings*
Operating Temperature .-55°C +125°C Storage Temperature .-65°C +150°C Voltage with Respect Ground .-2.0 +7.0 V(1) Maximum Operating Voltage .6.0
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Notes: Minimum voltage -0.6 which undershoot -2.0 pulses less than Maximum output voltage 0.75 which overshoot +7.0 pulses less than
Volt Characteristics
Applicable over recommended operating range from -55°C +125°C, (unless otherwise noted)
Symbol Parameter Input Leakage High Input Leakage pull-up) 108K pull-up (U9) Output Leakage pull-up) Input Voltage CMOS Input Voltage Input High Voltage CMOS Input High Voltage Switching Threshold CMOS Switching Threshold 25°C 25°C Test Condition VDD, VSS, VSS, VSS, -125 0.01 -0.01 0.01 Units
Output Voltage rated Output buffer stages drive capability with stage. Output High Voltage rated Output buffer stages drive capability with stage. Output Short Circuit Current Buffer)(2) VOUT VOUT
-100
Note: This specification Output Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
Volt Characteristics
Applicable over recommended operating range from -55°C +125°C, (unless otherwise noted)
Symbol Parameter Input Leakage High Input Leakage pull-up) 108K pull-up (U9) Output Leakage pull-up) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold 25°C Test Condition VDD, VSS, VSS, VSS, 0.01 -0.01 0.01 Units
Output Voltage rated Output buffer stages drive capability with stage. Output High Voltage rated Output buffer stages drive capability with stage. Output Short Circuit Current Buffer)(2) VOUT VOUT
Note: This specification Output Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (Die) Capacitance, Output Buffer (Die) Capacitance, Bi-Directional Test Condition Units
Schmitt Trigger Positive Threshold CMOS Positive Threshold Negative Threshold CMOS Negative Threshold Hysteresis CMOS Hysteresis CMOS Positive Threshold CMOS Negative Threshold CMOS Hysteresis 25°C, 25°C, 25°C, 25°C, 25°C, 25°C, 25°C, 25°C, 25°C,
Buffers
Programmable output drive IOL, 3,000 volts protection Built-in configurable test logic
ATL80 series input/output ring contains buffer circuitry capable sourcing sinking currents responds CMOS logic levels. outputs switched high impedance state. locations this ring accommodate bidirectional cells.
ATL80
ATL80
Characteristics
Delay
Prop Delay (ps)
Delay Fanout
Volts
Volts Volts
Prop Delay (ns)
Volts Volts
input NAND Temp 25°C
Fanout
input NAND Temp 25°C
Delay Temperature
Prop Delay (ps)
Output Buffer Load
Prop Delay (ns) Temperature (°C) Capacitive Load (pF)
Volts Volts
input NAND
Volts Volts
PDO4 Output Buffer Temp 25°C
Design Testability
Atmel supports full range Design-for-Test improvement techniques which reduce design prototype debug time, production test time, board system test time. These techniques also improve system level test diagnostic capability. ATL80 arrays support Joint Test Action Group (JTAG) boundary scan architecture. required soft hard macros implement IEEE 1149.1 compliant architecture available macro cell library. JTAG allows scan testing with only additional pins required. Atmel also provide automatic high fault coverage test pattern generation (ATPG) Synopsys Test Compiler. following design rules, Test Compiler automatically insert scan cells generate test vectors providing greater than fault coverage. This easiest least expensive method designing testability into gate array design.
Advanced Packaging
Atmel supports wide variety standard packages ATL80 series, also offers ATL80 series gate arrays packages that custom designed maintain performance obtained silicon. Atmel's standard packages have been characterized thermal electrical performance. When standard package can't meet customer's needs, Atmel's package design center develop package precisely application. company delivered custom-designed packages wide variety configurations.
Packaging Options
Package Type PQFP TQFP PLCC CPGA CQFP Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 225,
ATL80
ATL80
Military Product Flow Chart
MIL-STD-883 Class
SPC, Monitors Wafer Fabrication
SPC, Monitors
Wafer Sort Electrical Test
SPC, Monitors
Saw, Attach Wire Bond
SPC, Monitors
Internal Visual Method 2010 Condition Mechanical Tests Method 2011 Method 2019
Monitors
Seal Topside Mark
Monitors
Environmental Preconditioning Temperature Cycling Method 1010 Condition Constant Acceleration Method 2001 Condition Fine Gross Leak Method 1014
Monitors
Burn-In Electrical Screening
Monitors
Burn-In Method 1015 Condition
100% Final Electrical Screening PDA=5% +25°C -55°C, +125°C
Monitors
100% External Visual Method 2009
Group Inspection Method 5005 Review Groups Quality Conformance Inspection Documentation
Pre-Ship Inspection
Shipment
Actel, Altera, AMD, AMI, Cadence, Fujitsu, Logic, Mentor, NEC, Oki, SPICE, Synopsys, Verilog-XL, Viewlogic, Xilinx registered trademarks others.
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