significant number digital systems must deal with inputs synchronized

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significant number digital systems must deal with inputs synchronized

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Metastability
significant number digital systems must deal with inputs synchronized their internal clocks. These asynchronous signals arise from various asynchronous protocols which often used designs; they result trying share signals from systems with different clocks; they response system user, course synchronized with system. result metastability, problem which plague unwary designers. newly discovered phenomenon, normally dealt with somewhat qualitatively, and, unfortunately, usually ignored much possible.
CAUSES METASTABILITY
flip-flop setup time parameter that most often root metastability. setup time requirement that data made available input flip-flop before clock signal arrives. data must only there, must also stable. PLD, array data adds setup time. data passes through array flip-flop (Figure clock signal, other hand, goes directly from clock flip-flop. path much shorter than data path. setup time requirement that data signal must given more time flip-flop before clock signal. published setup time satisfied, data arrives flip-flop well before clock, output flip-flop will change desired (Figure setup time violated, then guarantee made about what output will output could normal, since published setup time worst-case number. However, timing between clock data just right, output will unstable some time before settles into some state. Neither time output remains unstable final state predictable (Figure This condition metastability.
Array Buffer Buffer
14104D-001
General Information
Figure
Clock Data Paths
Publication# 14104 Amendment/0
Rev: Issue Date: November 1998
Data Clock
Outputs
14104D-002
Figure
Output Response When Setup Time Satisfied
Data Clock
Outputs
14104D-003
Figure
Possible Output Response When Setup Time Violated
SOLUTIONS METASTABILITY
most common dealing with this problem synchronize inputs with extra flip-flop (Figure first flip-flop goes metastable, hopefully delay between clock pulses will allow ringing down before clocking into next flip-flop. This improves chances having good data second flip-flop.
Metastability
Extra Flip-Flop Synchronization
14104D-004
Figure
Dual Synchronizer
This method without costs. Each extra stage flip-flop means extra clock delay data which must absorbed system. Moreover, foolproof. possibility metastability reduced, eliminated. flip-flop metastable preceding stage does recover quickly enough. best avoid metastability avoid synchronization when possible. Many applications, such arbitration schemes, synchronization because synchronization itself necessary, because provides only convenient store data. This unfortunately takes system that inherently asynchronous adds some synchronizing elements middle.
SUMMARY
Metastability occur number different kinds asynchronous systems, usually inability guarantee that setup time flip-flops will satisfied. standard synchronous systems where setup time (along with other timing requirements) specifically designed metastability will never problem. some situations, metastability caused need interface systems with different clocks. this case, will never possible completely eliminate possibility metastability. Instead, designer must take steps reduce probability system failure metastability. General Information
Metastability
Metastability

significant number digital systems must deal with inputs synchronized

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