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PENTIUM® PROCESSOR MHz, MHz,
Separate dedicated external system bus, dedicated internal full-speed cache separate data instruction, non-blocking, level cache Available with integrated non-blocking, level cache package Data integrity reliability features include ECC, Fault Analysis/Recovery, Functional Redundancy Checking Upgradable Future OverDrive® processor
Available MHz, MHz, 200MHz core speeds Binary compatible with applications running previous members Intel microprocessor family Optimized 32-bit applications running advanced 32-bit operating systems Dynamic Execution microarchitecture Single package includes Pentium® processor CPU, cache system interface Scalable four processors memory
Pentium® processor family Intel's next generation performance high-end desktops, workstations servers. family consists processors higher easily scalable four microprocessors multiprocessor system. Pentium processor delivers more performance than previous generation processors through innovation called Dynamic Execution. This next step beyond superscalar architecture implemented Pentium processor. This makes possible advanced visualization interactive capabilities required today's high-end commercial technical applications tomorrow's emerging applications. Pentium processor also includes advanced data integrity, reliability, serviceability features mission critical applications. Pentium processor contain design defects errors known errata. Current characterized errata available upon request.
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Intel retains right make changes these specifications time, without notice. Microcomputer products have minor variations these specifications known errata. Contact your local sales office distributor obtain latest specifications before placing your product order. INTEL CORPORATION 1995 November 1995 Order Number: 242769-003
PENTIUM® PROCESSOR 150, 166, 180,
CONTENTS
PAGE 1.0. INTRODUCTION 1.1. TERMINOLOGY.4 1.2. REFERENCES.4 2.0. PENTIUM® PROCESSOR ARCHITECTURE OVERVIEW.4 2.1. Full Core Utilization 2.2. Pentium® Processor Pipeline.6 2.3. Architecture Summary.11 3.0. ELECTRICAL SPECIFICATIONS.11 3.1. Pentium® Processor VREF11 3.2. Power Management: Stop Grant Auto HALT 3.3. Power Ground Pins 3.4. Decoupling Recommendations 3.5. BCLK Clock Input Guidelines.14 3.6. Voltage Identification 3.7. JTAG Connection 3.8. Signal Groups.17 3.9. PWRGOOD.18 3.10. THERMTRIP# 3.11. Unused Pins 3.12. Maximum Ratings.20 3.13. Specifications 3.14. GTL+ Specifications.24 3.15. Specifications 3.16. Flexible Motherboard Recommendations.35 GTL+ Interface Specification.36 4.1. System Specification 4.2. General GTL+ Buffer Specification.46 4.3. Package Specification 4.4. Ref8N Network 3.3V Tolerant Signal Quality Specifications 5.1. OVERSHOOT/UNDERSHOOT GUIDELINES 5.2. RINGBACK SPECIFICATION 5.3. SETTLING LIMIT GUIDELINE.59
6.0. THERMAL SPECIFICATIONS 6.1. Thermal Parameters.60 6.2. Thermal Analysis 7.0. MECHANICAL SPECIFICATIONS 7.1. Dimensions.64 7.2. Pinout.67 8.0. OVERDRIVE® PROCESSOR SOCKET SPECIFICATION 8.1. Introduction 8.2. Mechanical Specifications 8.3. Functional Operation OverDrive® Processor Signals 8.4. OverDrive® Processor Electrical Specifications 8.5. Thermal Specifications 8.6. Criteria OverDrive® Processor APPENDIX A[35:3]# (I/O).97 A20M# (I).97 ADS# (I/O).98 AERR# (I/O).99 AP[1:0]# (I/O) ASZ[1:0]# (I/O) ATTR[7:0]# (I/O).100 BCLK .100 BE[7:0]# (I/O) .100 A.10 BERR# (I/O).101 A.11 BINIT# (I/O).101 A.12 BNR# (I/O) .101 A.13 BP[3:2]# (I/O) .102 A.14 BPM[1:0]# (I/O) .102 A.15 BPRI# .102 A.16 BR0#(I/O), BR[3:1]# .102 A.17 BREQ[3:0]# (I/O).103 A.18 D[63:0]# (I/O) .103 A.19 DBSY# (I/O) .104
PENTIUM® PROCESSOR 150, 166, 180,
CONTENTS (Contd.)
PAGE A.20 DEFER# .104 A.21 DEN# (I/0) .105 A.22 DEP[7:0]# (I/O) .105 A.23 DID[7:0]# (I/O).105 A.24 DRDY# (I/O).105 A.25 DSZ[1:0]# (I/O).105 A.26 EXF[4:0]# (I/O).106 A.27 FERR# .106 A.28 FLUSH# (I).106 A.29 FRCERR (I/O).106 A.30 HIT# (I/O), HITM# (I/O).107 A.31 IERR# .107 A.32 IGNNE# .107 A.33 INIT# .108 A.34 INTR .108 A.35 LEN[1:0]# (I/O).108 A.36 LINT[1:0] .108 A.37 LOCK# (I/O) .109 A.38 .109 PAGE A.39 PICCLK (I).109 A.40 PICD[1:0] (I/O) .109 A.41 PWRGOOD .109 A.42 REQ[4:0]# (I/O) .109 A.43 RESET# (I).110 A.44 (I/O) .111 A.45 RS[2:0]# (I).111 A.46 RSP# .112 A.47 SMI# (I).112 A.48 SMMEM# (I/O) .112 A.49 SPLCK# (I/O) .113 A.50 STPCLK# (I).113 A.51 (I).113 A.52 TDI(I) .113 A.53 .113 A.54 .113 A.55 TRDY .113 A.56 TRST .114
PENTIUM® PROCESSOR 150, 166, 180,
1.0.
INTRODUCTION
Pentium processor next Intel386TM, Intel486TM, Pentium family processors. Pentium processor implements Dynamic Execution microarchitecture-a unique combination multiple branch prediction, data flow analysis, speculative execution. Pentium processor upgradable future OverDrive processor matching voltage regulator module described Section
symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D#[3:0] `LHLH' also refers `A'. High logic level, logic level) word Preliminary appears occasionally. Check with your local Field Applications Engineer recent information.
within
1.2.
References
referenced this
Increasing clock frequencies silicon density complicate system designs. Pentium processor integrates several system components which alleviate some previous system burdens. second level cache, cache controller, Advanced Programmable Interrupt Controller (APIC) some components that existed previous Intel processor family systems which integrated into this single component. This integration results Pentium processor more closely resembling symmetric multiprocessing (SMP) system rather than resembling previous generation processor-tocache bus. This added level integration improved performance, results higher power consumption technology. This means more important than ever ensure adherence this specification. significant feature Pentium processor, from system perspective, built-in direct multiprocessing support. order achieve multi-processing four processors, maintain memory Input/Output (I/O) bandwidth support them, system designs needed. creating system with multiple processors, important consider additional power burdens signal integrity issues supporting loads high-speed bus.
following specification:
Pentium® Processor Buffer Models- IBIS Format world wide page http://www.intel.com)
AP-523, Pentium® Processor Power Distribution Guidelines Application Note (Order Number 242764) AP-524, Pentium® Processor GTL+ Layout Guidelines Application Note (Order Number 242765) AP-525, Pentium® Processor Thermal Design Guidelines Application Note (Order Number 242766)
Pentium® Processor Developer's Manual, Volume Specifications (Order Number 242690) Pentium® Processor Developer's Manual, Volume Programmer's Reference Manual (Order Number 242691) Pentium® Processor Developer's Manual, Volume Operating System Writer's Guide (Order Number 242692)
2.0.
PENTIUM® PROCESSOR ARCHITECTURE OVERVIEW
1.1.
Terminology
symbol after signal name refers active signal. This means that signal active state (based name signal) when driven low. example, when FLUSH# flush been requested. When Nonmaskable Interrupt (NMI) high, Non-maskable interrupt occurred. case lines where name does imply active state describes part binary sequence (such address data),
Pentium processor decoupled, 12stage, superpipelined implementation, trading less work pipestage more stages. Pentium processor also pipestage time percent less than Pentium processor, which helps achieve higher clock rate given process. approach used Pentium processor removes constraint linear instruction sequencing between traditional "fetch"
2.1.
PENTIUM® PROCESSOR 150, 166, 180,
first instruction this example load that, time, causes cache miss. traditional core must wait interface unit read this data from main memory return before moving instruction This stalls while waiting this data thus being under-utilized. avoid this memory latency problem, Pentium processor "looks-ahead" into instruction pool subsequent instructions will useful work rather than stalled. example Example instruction executable since depends upon result instruction however, both instructions executable. Pentium processor executes instructions out-oforder. results this out-of-order execution committed permanent machine state (i.e., programmer-visible registers) immediately since original program order must maintained. results instead stored back instruction pool awaiting in-order retirement. core executes instructions depending upon their readiness execute, their original program order, therefore true dataflow engine. This approach side effect that instructions typically executed out-of-order.
"execute" phases, opens wide instruction window using instruction pool. This approach allows "execute" phase Pentium processor have much more visibility into program's instruction stream that better scheduling take place. requires instruction "fetch/decode" phase Pentium processor much more intelligent terms predicting program flow. Optimized scheduling requires fundamental "execute" phase replaced decoupled "dispatch/execute" "retire" phases. This allows instructions started order always completed original program order. Pentium processor implemented three independent engines coupled with instruction pool shown Figure
Full Core Utilization
three independent-engine approach taken more fully utilize core. Consider code fragment Example
Fetch/ Decode Unit
Dispatch /Execute Unit
Retire Unit
Instruction Pool
Figure Three Engines Communicating Using Instruction Pool
PENTIUM® PROCESSOR 150, 166, 180,
Example Typical Code Fragment [r0] Instruction Instruction Instruction Instruction
cache miss instruction will take many internal clocks, Pentium processor core continues look ahead other instructions that could speculatively executed, typically looking instructions front instruction pointer. Within this instruction window there will average, five branches that fetch/decode unit must correctly predict dispatch/execute unit useful work. sparse register Intel Architecture (IA) processor will create many false dependencies registers dispatch/execute unit will rename registers into larger register enable additional forward progress. retire unit owns programmer's register results only committed permanent machine state these registers when removes completed instructions from pool original program order. Dynamic Execution technology summarized optimally adjusting instruction execution predicting program flow, having ability speculatively execute instructions order, then analyzing program's dataflow graph choose best order execute instructions.
FETCH/DECODE unit: in-order unit that takes input user program instruction stream from instruction cache, decodes them into series micro-operations (µops) that represent dataflow that instruction stream. pre-fetch speculative. DISPATCH/EXECUTE unit: out-of-order unit that accepts dataflow stream, schedules execution µops subject data dependencies resource availability temporarily stores results these speculative executions. RETIRE unit: in-order unit that knows when commit ("retire") temporary, speculative results permanent architectural state. INTERFACE unit: partially ordered unit responsible connecting three internal units real world. interface unit communicates directly with (second level) cache supporting four concurrent cache accesses. interface unit also controls transaction bus, with Modified Exclusive Shared Invalid (MESI) snooping protocol, system memory.
2.2.
Pentium® Processor Pipeline
order closer look Pentium processor implements Dynamic Execution, Figure shows block diagram including cache memory interfaces. "Units" shown Figure represent groups stages Pentium processor pipeline.
PENTIUM® PROCESSOR 150, 166, 180,
System
Cache
Interface Unit
ICache
Fetch
DCache
Load Store
Fetch/ Decode Unit
Dispatch /Execute Unit
Retire Unit
Instruction Pool
Figure Three Core Engines Interface with Memory Unified Caches
2.2.1. FETCH/DECODE UNIT ICache local instruction cache. Next_IP unit provides ICache index, based inputs from Branch Target Buffer (BTB), trap/interrupt status, branch-misprediction indications from integer execution section.
Figure shows more detailed view Fetch/Decode Unit.
PENTIUM® PROCESSOR 150, 166, 180,
From
ICache
Next_IP
Interface Unit Instruction Decoder Branch Target Buffer Microcode Instruction Sequencer Register Alias Table ReOrder Buffer
(x3)
Allocate
Instruction Pool (ROB)
Figure Inside Fetch/Decode Unit
ICache fetches cache line corresponding index from Next_IP, next line, presents aligned bytes decoder. prefetched bytes rotated that they justified Instruction Decoders (ID). beginning instructions marked. Three parallel decoders accept this stream marked bytes, proceed find decode instructions contained therein. decoder converts instructions into triadic µops (two logical sources, logical destination µop). Most instructions converted directly into single µops, some instructions decoded into one-to-four µops complex instructions require microcode (the labeled Figure This microcode just preprogrammed sequences normal µops. µops queued, sent Register Alias Table (RAT) unit, where logical IA-based register references converted into Pentium processor physical register references, Allocator stage, which adds status information µops enters them into instruction pool. instruction pool implemented array Content Addressable Memory called ReOrder Buffer (ROB).
This in-order pipe. 2.2.2. DISPATCH/EXECUTE UNIT
dispatch unit selects µops from instruction pool depending upon their status. status indicates that operands then dispatch unit checks execution resource needed that also available. both true, Reservation Station removes that sends resource where executed. results later returned pool. There five ports Reservation Station, multiple resources accessed shown Figure Pentium processor schedule peak rate µops clock, each resource port, sustained rate µops clock typical. activity this scheduling process out-oforder process; µops dispatched execution resources strictly according dataflow constraints resource availability, without regard original ordering program.
To/from Instruction Pool (ROB)
PENTIUM® PROCESSOR 150, 166, 180,
Port
Port Port Port
Reservation Station Execution Unit Floating Point Integer Jump Address Generation Unit ReOrder Buffer
Load Store
Figure Inside Dispatch/Execute Unit Note that actual algorithm employed this execution-scheduling process vitally important performance. only resource becomes data-ready clock cycle, then there choice. several available, must choose. Pentium processor uses pseudo First First (FIFO) scheduling algorithm favoring back-toback µops. Note that many µops branches. will correctly predict most these branches can't correctly predict them all. Consider that correctly predicting backward branch bottom loop; eventually that loop going terminate, when does, that branch will mispredicted. Branch µops tagged in-order pipeline) with their fall-through address destination that predicted them. When branch executes, what branch actually compared against what prediction hardware said would those coincide, then branch eventually retires, most speculatively executed work behind instruction pool good. they coincide, then Jump Execution Unit (JEU) changes status µops behind branch remove them from instruction pool. that case proper branch destination provided which restarts whole pipeline from target address. 2.2.3. RETIRE UNIT Figure shows more detailed view Retire Unit. retire unit also checking status µops instruction pool. looking µops that have executed removed from pool. Once removed, original architectural target µops written original instruction. retirement unit must only notice which µops complete, must also reimpose original program order them. must also this face interrupts, traps, faults, breakpoints mispredictions. retirement unit must first read instruction pool find potential candidates retirement determine which these candidates next original program order. Then writes results this cycle's retirements both Instruction Pool Retirement Register File (RRF). retirement unit capable retiring µops clock. 2.2.4. INTERFACE UNIT
Figure shows detailed view Interface Unit.
PENTIUM® PROCESSOR 150, 166, 180,
To/from DCache
Reservation Station Memory Interface Unit Retirement Register File
From
Instruction Pool
Figure Inside Retire Unit
Cache
Memory Order Buffer Address Generation Unit ReOrder Buffer
DCache
From
To/from Instruction Pool (ROB)
Figure Inside Interface Unit There types memory access: loads stores. Loads only need specify memory address accessed, width data being retrieved, destination register. Loads encoded into single µop. Stores need provide memory address, data width, data written. Stores therefore require µops, generate address, generate data. These µops must later recombine store complete. Stores never performed speculatively since there transparent undo them. Stores also never reordered among themselves. store dispatched only when both address data available there older stores awaiting dispatch. study importance memory access reordering concluded: Stores must constrained from passing other stores, only small impact performance.
PENTIUM® PROCESSOR 150, 166, 180,
There VREF pins Pentium processor ensure that internal noise will affect performance buffers. Pins (VREF[3:0]) must tied together pins A47, U41, AE47 AG45 (VREF[7:4]) must tied together. groups also tied each other desired.
Stores constrained from passing loads, inconsequential performance loss. Constraining loads from passing other loads stores significant impact performance.
Memory Order Buffer (MOB) allows loads pass other loads stores acting like reservation station re-order buffer. holds suspended loads stores re-dispatches them when blocking condition (dependency resource) disappears.
1.5V
1.5V
2.3.
Architecture Summary
stubs
ASIC ASIC
Dynamic Execution this combination improved branch prediction, speculative execution data flow analysis that enables Pentium processor deliver superior performance.
Figure GTL+ Topology
3.0. 3.1.
ELECTRICAL SPECIFICATIONS Pentium® Processor VREF
Most Pentium processor signals variation voltage Gunning Transceiver Logic (GTL) signaling technology. Pentium processor specification similar specification been enhanced provide larger noise margins reduced ringing. This accomplished increasing termination voltage level controlling edge rates. Because this specification different from standard specification, refered GTL+ this document. GTL+ signals open-drain require external termination supply that provides high signal level. GTL+ inputs differential receivers which require reference signal (VREF). Termination (usually resistor each signal trace) used pull high voltage level control reflections stubfree transmission line. VREF used receivers determine signal logical logical Table termination voltage specifications GTL+, Section GTL+ Interface Specification.
GTL+ depends incident wave switching. Therefore timing calculations GTL+ signals based flight time opposed capacitive deratings. Analog signal simulation Pentium processor including trace lengths highly recommended when designing system with heavily loaded GTL+ bus. Intel's world wide page (http:\\www.intel.com) download buffer models Pentium processor IBIS format.
3.2.
Power Management: Stop Grant Auto HALT
Pentium processor allows Stop Grant Auto HALT modes immediately reduce power consumed device. When enabled, these cause clock stopped most CPU's internal units thus significantly reduces power consumption whole. Stop Grant entered asserting STPCLK# Pentium processor. When STPCLK# recognized Pentium processor, will stop execution will service interrupts. will continue snooping bus. Stop Grant power specified assuming snoop hits occur. Auto HALT low-power state entered when Pentium processor executes halt (HLT) instruction. this state, Pentium processor behaves executed halt instruction, additionally powers-down most internal units. Auto
PENTIUM® PROCESSOR 150, 166, 180,
HALT, Pentium processor will recognize interrupts snoops. Auto HALT power specified assuming snoop hits interrupts occur. low-power stand-by mode Stop Grant Auto HALT defined Low-Power Enable configuration either lowest power achievable Pentium processor (Stop Grant power), power state which clock distribution left running (Idle power). "Low-power stand-by" disabled leaves core logic running, while "Low-power stand-by" enabled allows Pentium processor enter lowest power mode.
on-package cache some processors. VCC5 provided OverDrive processor. VCC5, VCCS VCCP must remain electrically separated from each other. circuit board, VCCP pins must connected voltage island VCCS pins must connected separate voltage island island portion power plane that been divided, entire plane). Similarly, pins must connected system ground plane. Figure locations power ground pins.
3.4.
Decoupling Recommendations
3.3.
Power Ground Pins
future versions Pentium processor released, operating voltage cache differ from each other. There groups power inputs Pentium processor package support possible voltage difference between package, support OverDrive processor. There also pins defined package voltage identification (VID). These pins specify voltage required die. These have been added cleanly support voltage specification variations Pentium processor future processors. Section 3.6. explanation voltage identification pins. Future mainstream devices will fall into groups. Either Cache will both same voltage (VCCP), Cache will VCCS (3.3V) while runs another voltage VCCP. When cache running same supply die, VCCS pins will consume current. properly support this, system should distribute selectable voltage Pentium processor socket. Selection provided socketed regulation using pins. Note that possible that VCCP VCCS both nominally should assumed that these will able same power supply. clean on-chip power distribution, Pentium processor (power) (ground) inputs. pins further divided provide different voltage levels device. VCCP inputs some account pins, while VCCS inputs (3.3V)
large number transistors high internal clock speeds, Pentium processor create large, short duration transient (switching) current surges that occur internal clock edges which cause power planes spike above below their nominal value properly controlled. Pentium processor also capable generating large average current swings between full power states, called Load-Change Transients, which cause power planes below their nominal value bulk decoupling adequate. Figure example these current fluctuations. Care must taken board design guarantee that voltage provided Pentium processor remains within specifications listed this volume. Failure result timing violations and/or reduced lifetime component. Adequate decoupling capacitance should placed near power pins Pentium processor. inductance capacitors such 1206 package surface mount capacitors recommended best high frequency electrical performance. Forty (40) 1206-style capacitors with ±22% tolerance make good starting point simulations this recommended decoupling when using standard Pentium Voltage Regulator Module. Inductance should reduced connecting capacitors directly VCCP planes with minimal trace length between component pads vias plane. sure include effects board inductance within simulation. Also, when choosing capacitors use, bear mind operating temperatures they will tolerance that they rated Type better recommended (±22% tolerance over temperature range -30°C +85°C).
PENTIUM® PROCESSOR 150, 166, 180,
Current Current Averaged Current
Load-Change Transient
Switching Transient
Switching Transient
Figure Transient Types
Bulk capacitance with Effective Series Resistance (ESR) should also placed near Pentium processor order handle changes average current between low-power normal operating states. About 4000uF capacitance with makes good starting point simulations, although more capacitance needed bring down this level current technology industry. standard Pentium Voltage Regulator Modules already contain this bulk capacitance. sure determine what available market before choosing parameters models. Also, include power supply response time cable inductance full simulation. AP-523 Pentium® Processor Power Distribution Guidelines Application Note (Order Number 242764) power modeling Pentium processor.
3.4.1.
VCCS DECOUPLING
Decoupling (10) ceramic capacitors (type better) minimum five 22µF tantalum capacitors recommended VCCS pins. This handle transients that will occur future devices. 3.4.2. GTL+ DECOUPLING
Although Pentium GTL+ processor receives power external Pentium processor, should noted that this power supply will also require same diligent decoupling methodologies processor. Notice that existence external power entering through buffers causes current higher than current evidenced Figure
PENTIUM® PROCESSOR 150, 166, 180,
3.4.3. PHASE LOCK LOOP (PLL) DECOUPLING
Isolated analog decoupling required internal PLL. This should equivalent 0.1µF ceramic capacitance. capacitor should type better should across PLL1 PLL2 pins Pentium processor. ("Y5R" implies ±15% tolerance over temperature range -30°C +85°C.)
clocks beyond RESET# pulse, determines multiplier that will internal core clock. Appendix definition these pins during reset. other times their functionality defined compatibility signals that pins named after. These signals tolerant driven existing logic devices. This important both functions pins. Supplying clock multiplier this required order increase processor performance without changing processor design, maintain frequency such that system boards designed function properly frequencies increase. 3.5.1. SETTING CORE CLOCK CLOCK RATIO
3.5.
BCLK Clock Input Guidelines
BCLK input directly controls operating speed GTL+ interface. GTL+ external timing parameters specified with respect rising edge BCLK input. Clock multiplying within processor provided internal Phase Lock Loop (PLL) which requires constant frequency BCLK input. Therefore BCLK frequency cannot changed dynamically. however changed when RESET# active assuming that reset specifications clock configuration signals. Pentium processor core frequency must configured during reset using A20M#, IGNNE#, LINT1/NMI, LINT0/INTR pins. value these pins during RESET#, until
Table lists configuration pins values that must driven reset time order core clock clock ratio. Figure shows timing relationship required clock ratio signals with respect RESET# BCLK. CRESET# from 82453GX 82453KX) shown since timing useful controlling multiplexing function that required sharing pins.
BCLK RESET# CRESET#
PENTIUM® PROCESSOR 150, 166, 180,
Compatibility
Ratio pins#
Final Ratio
Final Ratio
Figure Timing Diagram Clock Ratio Signals Using CRESET# (CMOS reset), circuit Figure used share pins. pins processors bussed together allow them compatibility processor. component used multiplexer must have outputs that drive higher than order meet Pentium processor's tolerant buffer specifications. multiplexer output current should limited 200mA maximum, case VCCP supply processor ever fails. pull-down resistors between multiplexer processor (1K) force ratio into processor event that Pentium processor powers before multiplexer and/or chip set. This prevents processor from ever seeing ratio higher than final ratio. multiplexer were powered VCCP, CRESET# would still unknown until supply came power CRESET# driver. pull-down used CRESET# instead four between multiplexer Pentium processor. this case, multiplexer must designed such that compatibility inputs truly ignored their state unknown. case, compatibility inputs multiplexer must meet input specifications multiplexer. This require level translation before multiplexer inputs unless inputs signals driving them already compatible. mode processors, multiplexer will needed pair, multiplexer will need clocked using BCLK meet setup hold times processors. This require high speed programmable logic. 3.5.2. MIXING PROCESSORS DIFFERENT FREQUENCIES
Mixing components different internal clock frequencies fully supported been validated Intel. should also note when attempting processors rated different frequencies multiprocessor system that common clock frequency multipliers must found that acceptable processors system. course, processor core frequency minimum rating. Operating system support multi-processing with mixed frequency components should also considered.
PENTIUM® PROCESSOR 150, 166, 180,
Pentium®
Processor
3.3V
A20M# IGNNE# LINT1/NMI LINT0/INTR
3.3V
Ratio:
CRESET#
Figure Example Schematic Clock Ratio Sharing Note: order support different frequency multipliers each processor, design shown above would require four multiplexers Table Voltage Identification Definition VID[3:0] 0000 0001 Voltage Setting VID[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Voltage Setting Present
3.6.
Voltage Identification
0010 0011 0100 0101 0110 0111
There four Voltage Identification Pins Pentium processor package. These pins used support automatic selection power supply voltage. These pins signals each either open circuit package short circuit VSS. opens shorts define voltage required processor. This been added cleanly support voltage specification variations future Pentium processors. These pins named VID0 through VID3 definition these pins shown Table this table refers open refers short ground. VCCP power supply should supply voltage that requested disable itself.
NOTES:
Nominal setting requiring regulation Pentium® processor VCCP pins under conditions. Support expected 2.1V-2.3V. Open circuit; Short
Support wider range settings will benefit system meeting power requirements future Pentium processors. Note that `1111' opens) used detect absence processor given socket long power supply used does affect these lines. these pins, they need pulled external resistor another power source. power source chosen should that guaranteed stable whenever supply voltage regulator stable. This will prevent possibility Pentium processor supply running event failure supply lines. Note that specification standard Pentium Voltage Regulator Modules allows these signals either compatible levels opens shorts. Using them compatible levels will require pull-up resistors input voltage regulator voltage divider input voltage regulator resistors chosen should cause current through exceed specification Table There must other components these signals uses them opens shorts.
PENTIUM® PROCESSOR 150, 166, 180,
multiprocessor system, cautious when including empty Pentium processor sockets scan chain. sockets scan chain must have processor installed complete chain system must support method bypass empty sockets. Pentium® Processor Developer's Manual, Volume Specifications (Order Number 242690) full information putting debug port JTAG chain.
3.8.
Signal Groups
order simplify following discussion, signals have been combined into groups buffer type. outputs open drain require external high-level source provided externally termination pull-up resistor. GTL+ input signals have differential input buffers which VREF their reference signal. GTL+ output signals require termination Later this document, term "GTL+ Input" refers GTL+ input group well GTL+ group when receiving. Similarly, "GTL+ Output" refers GTL+ output group well GTL+ group when driving. tolerant, Clock, APIC JTAG inputs each driven from ground 3.3V. tolerant, APIC, JTAG outputs each pulled high much Table specifications. groups signals contained within each group shown Table Note that signals ASZ[1:0]#, ATTR[7:0]#, BE[7:0]#, BREQ#[3:0], DEN#, DID[7:0]#, DSZ[1:0]#, EXF[4:0]#, LEN[1:0]#, SMMEM#, SPLCK# GTL+ signals that shared onto another pin. Therefore they appear this table. 3.8.1. ASYNCHRONOUS SYNCHRONOUS
3.7.
JTAG Connection
debug port described Pentium® Processor Developer's Manual, Volume Specifications (Order Number 242690) should start JTAG chain with first component coming from Debug Port from last component going Debug Port. recommended pull-up value Pentium processor pins 240. voltage levels supported Pentium processor JTAG logic, recommended that Pentium processors other logic level components within system first JTAG chain. translation buffer should used connect rest chain unless component used next that capable accepting input. Similar considerations must made TCK, TRST#. Components need these signals buffered match required logic levels.
GTL+ signals synchronous. tolerant signals applied asynchronously, except when running processors mode. mode, synchronization logic required signals, (except PWRGOOD) going
PENTIUM® PROCESSOR 150, 166, 180,
both processors. Also note timing requirements PICCLK with respect BCLK. With enabled, PICCLK must BCLK
synchronized with respect BCLK. PICCLK must always BCLK least more than
Table Signal Groups Group Name GTL+ Input GTL+ Output GTL+ BPRI#, PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#, STPCLK# FERR#, IERR#, THERMTRIP#3 BCLK PICCLK PICD[1:0] TCK, TDI, TMS, TRST# CPUPRES#, PLL1, PLL2, TESTHI, TESTLO, UP#, VCCP, VCCS, VCC5, VID[3:0], VREF[7:0], BR[3:1]#1, Signals DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
Tolerant Input Tolerant Output Clock4 APIC APIC JTAG JTAG Clock4 I/O4 Input4 Output4
Power/Other5
NOTES:
BR0# only BREQ# signal that bi-directional. internal BREQ# signals mapped onto pins after agent determined. PWRGOOD Section 3.9. THERMTRIP# Section 3.10. These signals tolerant 3.3V. pull-up resistor PICD[1:0] TDO. CPUPRES# ground defined allow designer detect presence processor socket. (preliminary) PLL1 PLL2 decoupling internal (See Section 3.4.3.). TESTHI pins should tied VCCP. pull-up used. Section 3.11. TESTLO pins should tied VSS. pull-down used. Section 3.11. open Pentium® processor tied OverDrive® processor (see Section 8.3.2 usage). VCCP primary power supply. VCCS secondary power supply used some versions second level cache. VCC5 unused Pentium processor used OverDrive processor fan/heatsink power. Section VID[3:0] lines described Section 3.6. VREF [7:0] reference voltage pins GTL+ buffers. ground.
3.9.
PENTIUM® PROCESSOR 150, 166, 180,
stable before rising edge PWRGOOD. must also meet minimum pulse width specification Table followed RESET# pulse. This signal must supplied Pentium processor used protect internal circuits against voltage sequencing issues. this signal recommended added reliability. This signal does need synchronized operation. should remain high throughout boundary scan testing.
PWRGOOD
PWRGOOD tolerant input. expected that this signal will clean indication that clocks system VCCP supplies stable within their specifications. Clean implies that signal will remain low, (capable sinking leakage current) without glitches, from time that power supplies turned until they come within specification. signal will then transition monotonically high (3.3 state. Figure illustrates relationship PWRGOOD other system signals. PWRGOOD driven inactive time, power clocks must again
Figure PWRGOOD Relationship Power-On
3.10.
THERMTRIP#
3.11.
Unused Pins
Pentium processor protects itself from catastrophic overheating internal thermal sensor. This sensor well above normal operating temperature ensure that there false trips. processor will stop execution when junction temperature exceeds ~135°C. This signaled system THERMTRIP# pin. Once activated, signal remains latched, processor stopped, until RESET# goes active. There hysteresis built into thermal sensor itself, long temperature drops below trip level, RESET# pulse will reset processor execution will continue. temperature dropped beyond trip level, processor will continue drive THERMTRIP# remain stopped.
RESERVED pins must remain unconnected. pins named TESTHI must pulled higher than VCCP, tied directly VCCP. pins named TESTLO must pulled tied directly VSS. PICCLK must driven with clock input, PICD[1:0] lines must each pulled-up with separate resistor, even when APIC will used. reliable operation, always connect unused inputs appropriate signal level. Unused GTL+ inputs should pulled-up VTT. Unused active tolerant inputs should connected with resistor unused active high inputs should
PENTIUM® PROCESSOR 150, 166, 180,
connected ground (VSS). resistor must also used when tying bi-directional signals power ground. When tying signal power ground, resistor will also allow fully testing processor after board assembly. unused pins, suggested that ~10K resistors used pull-ups (except PICD[1:0] discussed above), resistors used pull-downs. Never directly supply other than processor's VCCP supply VSS.
3.12.
Maximum Ratings
Unit Notes
Table contains Pentium processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. Pentium processor should receive clock while subjected these conditions. Functional operating conditions given tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table Absolute Maximum Ratings1 Symbol TStorage TBias VCCP(Abs) VCCS(Abs) VCCP-VCCS VIN3 IVID NOTES:
Functional operation absolute maximum minimum implied guaranteed. Operating voltage voltage that component designed operate Table Parameter applies GTL+ signal groups only. Parameter applies tolerant, APIC, JTAG signal groups only. Current flow through buffer diodes when VCCP+1.1V, power supply fault condition while power supplies sequencing. Thermal stress should minimized cycling power VCCP supply fails.
Parameter Storage Temperature Case Temperature under Bias Primary Supply Voltage with respect Supply Voltage with respect Primary Supply Voltage with respect Secondary Supply GTL+ Buffer Input Voltage with respect Tolerant Buffer Input Voltage with respect Maximum input current Maximum current
-0.5 -0.5 -3.7 -0.5 -0.5
Operating Voltage Operating Voltage VCCP+ exceed VCCP+ exceed
3.13.
Symbol VCCP VCCS VCC5 NOTES:
PENTIUM® PROCESSOR 150, 166, 180,
Most signals Pentium processor GTL+ signal group. These signals specified terminated 1.5V. specifications these signals listed Table Care should taken read notes associated with each parameter. allow compatibility with other devices, some signals tolerant therefore terminated driven 3.3V. specifications these tolerant inputs listed Table Care should taken read notes associated with each parameter.
Specifications
Table through Table list specifications associated with Pentium processor. Specifications valid only while meeting processor specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter. Section 3.3. explanation voltage plans Pentium processors. Section 8.4.1.1. OverDrive processor information Section 3.16 flexible motherboard recommendations. specifications VCCP, VCCS, VCC5 supplies listed Table Table
Table Voltage Specification Parameter Primary Secondary Supply 2.945 3.135 3.135 4.75 3.255 3.465 3.465 5.25 Unit Notes @150 MHz, 166,
This tolerance. comply with these guidelines industry standard voltage regulator module specifications, equivalent forty (40) µF±22% capacitors 1206 packages should placed near power pins processor. More specifically, least capacitance should exist power plane with less than 250pH inductance resistance between pins processor assuming regulator point ±1%. This voltage currently required Pentium processor. voltage defined future use. This voltage required OverDrive processor support.
PENTIUM® PROCESSOR 150, 166, 180,
Unit Notes MHz, 256K MHz, 512K MHz, 256K MHz, 256K MHz, 512K MHz, 256K other components frequencies MHz, 256K MHz, 512K MHz, 256K MHz, 256K MHz, 512K frequencies
Table Power Specifications Symbol PMax Parameter Thermal Design Power 23.0 27.5 24.8 27.3 32.6 29.2 35.0 31.7 35.0 37.9 11.2 10.1 11.2 12.4
ISGntP
VCCP Stop Grant Current
ISGntS ICCP
VCCS Stop Grant Current VCCP Current
ICCS ICC5 NOTES:
VCCS Current Supply Current Operating Case Temp.
power measurements taken with CMOS inputs driven VCCP Maximum values measured typical VCCP take into account thermal time constant package. Typical values tested, imply maximum power should when running normal high power applications most devices. When designing system typical power level, there should failsafe mechanism guarantee control specification case statistical anomalies workload. This workload could cause temporary rise maximum power. Power specifications 512K components PRELIMINARY. Consult your FAE. values measured typical VCCP asserting STPCLK# executing HALT intruction (Auto Halt) with EBL_CR_POWERON Low_Power_Enable enabled. Model Specific Registers Appendix Pentium® Processor Developer's Manual, Volume Operating System Writer's Guide (Order Number 242692). Minimum values guaranteed design/characterization minimum VCCP. VCCP current measured VCC. CMOS pins driven with VCCP during execution ICC-stopgrant/autohalt tests. current processors draw current from VCCS inputs. ICCS when receives power from VCCP pins. recommended decoupling Section 3.4.
Symbol IREF CGTL+ NOTES:
PENTIUM® PROCESSOR 150, 166, 180,
Table GTL+ Signal Groups Specifications Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Output Current Leakage Current Reference Voltage Current GTL+ Capacitance -0.3 VREF 0.30 VREF -0.2 VCCP 0.60 ±100 Unit Notes Table Table
VREF worst case, nominal. Noise VREF should accounted for. Parameter measured into resistor Min. max. guaranteed design/characterization. VPIN VCCP). Total current VREF pins. Section 3.1. details VREF connections. Total buffer, package parasitics socket. Capacitance values guaranteed design GTL+ buffers.
Table Non-GTL+1 Signal Groups Specifications Symbol CTOL CCLK CTCK NOTES:
Table applies tolerant, APIC, JTAG signal groups. Parameter measured (for with inputs). Parameter guaranteed design (for with CMOS inputs). Vpin VCCP). Total buffer, package parasitics socket. Capacitance values guaranteed design.
Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Input Leakage Current Tol. Capacitance BCLK Input Capacitance Input Capacitance
-0.3
Unit
Notes
±100
Outputs Open-Drain Except BCLK TCK,
PENTIUM® PROCESSOR 150, 166, 180,
3.14.
GTL+ Specifications
GTL+ must routed daisy-chain fashion with termination resistors each every signal trace. These termination resistors placed between ends signal trace voltage supply generally chosen approximate board impedance. valid high levels determined input buffers
using reference voltage called VREF. Table lists nominal specifications GTL+ termination voltage (VTT) GTL+ reference voltage (VREF). important that printed circuit board impedance specified held ±20% tolerance, that intrinsic trace capacitance GTL+ signal group traces known. more details GTL+, Section
Notes ±10% ±2%,
Table GTL+ Voltage Specifications Symbol VREF Parameter Termination Voltage Input Reference Voltage 1.35 VTT-2% Typical 1.65 Units
NOTES:
VREF should created from voltage divider resistors.
3.15.
Specifications
Table covers APIC timing, Table covers Boundary Scan timing. specifications GTL+ signal group relative rising edge BCLK input. GTL+ timings referenced VREF both logic levels unless otherwise specified. Care should taken read notes associated with particular timing parameter.
Table through Table list specifications associated with Pentium processor. Timing Diagrams begin with Figure specifications broken into categories. Table contains clock specifications, Table Table contain GTL+ specifications, Table tolerant Signal group specifications, Table contains timings reset conditions,
Parameter Core Frequency Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time NOTES:
PENTIUM® PROCESSOR 150, 166, 180,
Table Clock Specifications 50.00 166.67 66.67 Unit Figure Figure Figure Figure Figure Figure Notes Frequencies, Frequencies @>2.0 @<0.8 (0.8 (2.0 V),2
internal core clock frequency derived from clock. clock ratio must driven into Pentium® processor signals LINT[1:0], A20M# IGNNE# reset. descriptions these signals Appendix 100% tested. Guaranteed design/characterization. Measured rising edge adjacent BCLKs jitter present must accounted component BCLK skew between devices. Clock jitter measured from rising edge clock signal next rising edge 1.5V. remain within clock jitter specifications, clock periods must within ideal clock period given frequency. example, 66.67 clock with nominal period must have single clock period that greater than 15.3 less than 14.7
Table Supported Clock Ratios Component: NOTES:
Only those indicated tested during manufacturing test process.
5/2X
7/2X
PENTIUM® PROCESSOR 150, 166, 180,
Notes MHz, 256K other components MHz, 256K other components MHz, 256K other components
Table GTL+ Signal Groups Specifications Parameter 0.55 0.80 0.55 0.80 0.45 0.70 Unit Figure Figure
T7A: GTL+ Output Valid Delay T7B: GTL+ Output Valid Delay GTL+ Input Setup Time GTL+ Input Hold Time
Figure
Figure Figure
T10: RESET# Pulse Width
Figure Figure
NOTES:
Valid delay timings these signals specified into idealized resistor with VREF 1.0V. Minimum values guaranteed design. Figure actual test configuration. GTL+ timing specifications 166MHz higher components PRELIMINARY. Consult local FAE. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. Specification takes into account V/ns edge rate allowable VREF variation. Guaranteed design. After VCC, VTT, VREF, BCLK clock ratio become stable.
Table GTL+ Signal Groups Ringback Tolerance Parameter Overshoot Minimum Time High Amplitude Ringback Duration Squarewave Ringback Final Settling Voltage -100 Unit Figure Figure Figure Figure Figure Figure Notes
NOTES:
Specified edge rate 0.3-0.8V/ns. Section 4.1.3.1 definition these terms. Figure Figure generic waveforms. values determined design/characterization.
T11: T12: T13: T14: T15: Parameter NOTES:
PENTIUM® PROCESSOR 150, 166, 180,
Table Tolerant Signal Groups Specifications Unit BCLKs BCLKs Figure Figure Figure Figure Figure Figure Figure Both levels Notes
Tolerant Output Valid Delay Tolerant Input Setup Time Tolerant Input Hold Time Tolerant Input Pulse Width, except PWRGOOD PWRGOOD Inactive Pulse Width
Valid delay timings these signals specified into Figure capacitive derating curve. These inputs driven asynchronously. However, guarantee recognition specific clock, setup hold times with respect BCLK must met. These signals must driven synchronously mode. A20M#, IGNNE#, INIT# FLUSH# asynchronous inputs, guarantee recognition these signals following synchronizing instruction such write instruction, they must valid with active RS[2:0]# signals corresponding synchronizing transaction. INTR only valid APIC disable mode. LINT[1:0]# only valid APIC enabled mode. When driven inactive, after Power, VREF, BCLK, ratio signals stable.
12.00 11.50 11.00 10.50 10.00 9.50 9.00 8.50 8.00 7.50 7.00
Figure Tolerant Group Derating Curve
PENTIUM® PROCESSOR 150, 166, 180,
Figure Notes Before deassertion RESET# After clock that deasserts RESET# Before deassertion RESET# After assertion RESET# After clock that deasserts RESET#
Table Reset Conditions Specifications T16: Parameter Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Setup Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Delay Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time Unit BCLKs
Figure
T17:
BCLKs
Figure
T18:
Figure
T19:
BCLKs
Figure
T20:
BCLKs
Figure Figure
NOTES:
reset, clock ratio defined these signals must safe value (their final lower multiplier) within this delay unless PWRGOOD being driven inactive.
Parameter T21A: PICCLK Frequency T21B: Mode BCLK PICCLK offset T22: T23: T24: T25: T26: T27: T28: T29: NOTES:
PENTIUM® PROCESSOR 150, 166, 180,
Table APIC Clock APIC Specifications 33.3 Unit Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Notes
PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time PICD[1:0] Valid Delay
With enabled PICCLK must BCLK synchronized with respect BCLK. PICCLK must always BCLK least more than Referenced PICCLK Rising Edge. open drain signals, Valid Delay synonymous with Float Delay. Valid delay timings these signals specified into
PENTIUM® PROCESSOR 150, 166, 180,
Figure Notes Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure @2.0 @0.8 (0.8 V-2.0 (2.0 V-0.8 Asynchronous
Table Boundary Scan Interface Specifications T30: T31: T32: T33: T34: T35: T36: T37: T38: T39: T40: T41: T42: T43: T44: Parameter Frequency Period High Time Time Rise Time Fall Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 62.5 Unit
NOTES:
100% tested. Guaranteed design/characterization. added maximum rise fall times every below MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified into terminated Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. PWRGOOD should driven high throughout boundary scan testing. During Debug Port operation, normal specified timings rather than boundary scan timings.
Rise Time Fall Time High Time Time Period
PENTIUM® PROCESSOR 150, 166, 180,
Figure Generic Clock Waveform
Valid Delay Pulse Width GTL+ signal group; Tolerant, APIC, JTAG signal groups GTL+ signals must achieve high level least 1.2V GTL+ signals must achieve level most 0.8V
Figure Valid Delay Timings
PENTIUM® PROCESSOR 150, 166, 180,
Setup Time Hold Time GTL+ signal group; Tolerant, APIC JTAG signal groups
Figure Setup Hold Timings
T21B (FRC Mode BCLK PICCLK offset)
Figure Mode BCLK PICCLK Timing
VREF
0.3-0.8
PENTIUM® PROCESSOR 150, 166, 180,
VREF
VREF
Vstart
+0.05ns
Clock
Time
Case analogous. Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage
Figure High GTL+ Receiver Ringback Tolerance
PENTIUM® PROCESSOR 150, 166, 180,
(GTL+ Input Hold Time) (GTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time). (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Delay Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Setup Time)
Figure Reset Configuration Timings
(PWRGOOD Inactive Pulse Width) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time)
Figure Power-On Reset Configuration Timings
PENTIUM® PROCESSOR 150, 166, 180,
(All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold Time) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Delay)
Figure Test Timings (Boundary Scan)
(TRST# Pulse Width)
Figure Test Reset Timings
3.16.
Flexible Motherboard Recommendations
support required voltage regulator module. Section information Header These values preliminary. zero-insertion force socket processor voltage regulator module recommended. should also make every attempt leave margin system where possible.
Table provides recommendations designing "flexible" motherboard supporting future Pentium processors. meeting these recommendations, same system design should able support future standard Pentium processors. voltage regulator module socketed using Header smaller range
PENTIUM® PROCESSOR 150, 166, 180,
Unit 1206 packages 1206 packages Notes tolerance over range tolerance tolerance
Table Flexible Motherboard (FMB) Power Recommendations1 Symbol VCCP VCCS VCC5 PMax ICCP ICCS ICC5 Parameter Full Primary Socketed Primary Secondary Thermal Design power Full VCCP Current VCCS Current VCC5 Current High Frequency VCCP Decoupling High Frequency VCCS Decoupling Operating Case Temperature High 14.5
NOTE:
Values preliminary, processor, tested parameters. They solely recommendations.
GTL+ Interface Specification
This section defines open-drain called GTL+. primary target audience designers developing systems using GTL+ devices such Pentium processor 82450 PCIset. This specification will also useful buffer designers developing cell package used GTL+ bus. This specification enhancement specification. enhancements were made allow interconnect eight devices operating 66.6 higher using manufacturing techniques that standard microprocessor industry. specification enhancements over standard provide better noise margins reduced ringing. Since this specification different from specification, referred GTL+. GTL+ specification defines open-drain with external pull-up resistors providing termination termination voltage (VTT). specification includes maximum driver output voltage (VOL) value, output driver edge rate requirements, example
timings, maximum agent loading (capacitance package stub length), receiver threshold (VREF) that proportional termination voltage. specification given parts. first, system specification which describes system environment. second, actual specification, which describes characteristics transceiver. Note that some critical distances, such routing length, given electrical length (time) instead physical length (distance). This because system design dependent propagation time signal printed circuit board trace rather than just length trace. Different materials, package materials system construction result different signal propagation velocities. Therefore, given physical length does correspond fixed electrical length. distance (time) calculation designer.
4.1.
PENTIUM® PROCESSOR 150, 166, 180,
inputs connected reference voltage, VREF, which generated externally voltage divider. Typically, voltage divider exists each component. Here shown entire network.
System Specification
Figure shows typical system that GTL+ device would placed into. typical system shown with terminations multiple transceiver agents connected bus. receivers have differential
Figure Example Terminated with GTL+ Transceivers
PENTIUM® PROCESSOR 150, 166, 180,
4.1.1. System Parameters
Tolerance ±10% Note Notes
following system parameters apply Figure Table System Parameters Symbol VREF ZEFF NOTES:
Parameter Termination Voltage Input Reference Voltage Termination Resistance Effective (Loaded) Network Impedance
Value ZEFF (nominal) 45-65
This tolerance addition ±10% tolerance VTT, could caused such factors voltage divider inaccuracy. (nominal) ZEFF (1+Cd/Co) Nominal board impedance; recommended ±10%. function trace cross-section, distance reference plane(s), dielectric constant, material dielectric constant solder-mask/air micro-strip traces. Total intrinsic nominal trace capacitance between first last agents, excluding termination resistor tails. function 4.3, approximately 2.66 pF/in times network length (first agent last agent). Capacitance devices stubs any) attached net, Stub Capacitance +Socket Capacitance +Package Stub Capacitance Capacitance. ZEFF 8-load nets must remain between 45-65 under conditions, including variations temperature, VCC, etc. reduce cost, system would usually employ value GTL+ nets, irrespective ZEFF individual nets. designer start with average value ZEFF system. value adjusted balance Hi-to-Lo Lo-to-Hi noise margins. Increasing value tends slow rising edge, increasing rising flight time, decreasing Lo-to-Hi noise margin, increasing Hi-to-Lo noise margin lowering VOL. decreased opposite effects. affects GTL+ rising edge rates "apparent clock-to-out" time driver follows: large causes standing current when (open drain) driver (on). driver switches off, small current turned off, launching relatively small positive-going wave down net. After trips back forth between driver terminations (undergoing reflections intervening agents meantime) voltage finally climbs VTT. Because wave launched initially relatively small amplitude (than would have been been smaller standing current larger), overall rising edge climbs toward slower rate. Notice that this effect causes increase flight time, influence true clock-to-out timing driver into standard test load.
4.1.2.
Topological Guidelines
board routing should layout design rules consistent with high-speed digital design (i.e., minimize trace length number vias, minimize trace-to-trace coupling, maintain consistent impedance over length net, maintain consistent impedance from another,
ensure sufficient power ground plane bypassing, etc.). addition, signal routing should done Daisy Chain topology (such shown Figure without significant stubs. Table describes, more completely, some these guidelines. Note that critical distances measured electrical length (propagation time) instead physical length.
Parameter Maximum Trace Length Maximum Stub Length Distributed Loads
PENTIUM® PROCESSOR 150, 166, 180,
Table System Topological Guidelines Description meet specific clock cycle time, maximum trace length between agents must restricted. flight time (defined later) must less than equal maximum amount time which leaves enough time within clock cycle remaining system parameters such driver clock-out delay (TCO), receiver setup time (TSU), clock jitter clock skew. signals should Daisy Chain routing (i.e. stubs). acknowledged that package each device imposes stub, that practical layout using PQFP parts require SHORT stubs, truly stubless network impossible achieve, stub network (including device package) should greater than electrical length. Minimum spacing lengths determined hold time requirements clock skew. Maintaining ±30% inter-agent spacing minimizes variation noise margins between various networks, provide significant improvement networks. This only guideline.
System Parameters: Signal Quality system parameters fall into categories, Signal Quality Flight Time. Acceptable signal quality must maintained over operating conditions ensure reliable
4.1.3.
operation. Signal Quality defined three parameters: Overshoot/Undershoot, Settling Limit, Ringback. These parameters illustrated Figure described Table
Figure Receiver Waveform Showing Signal Quality Parameters
PENTIUM® PROCESSOR 150, 166, 180,
Specification (guideline) ±10% (VOH-VOL) (guideline) VREF ±200
Table Specifications Signal Quality Parameter Maximum Signal Overshoot/Undershoot Settling Limit Description Maximum Absolute voltage signal extends above below (simulated protection diodes). maximum amount ringing, receiving chip pad, signal must limited before next transition. This signal should within signal swing final value, when either high state state. maximum amount ringing allowed signal receiving chip within receiving chips setup hold time window before next clock. This value dependent upon specific receiver design. (Normally ringing within setup hold windows must come within VREF although specific devices allow more ringing loosen this specification. Section 4.1.3.1 more details.)
Maximum Signal Ringback (Nominal)
overshoot/undershoot guideline provided limit signals transitioning beyond fast signal edge rates. Violating overshoot/undershoot guideline acceptable, since excessive ringback harmful effect associated with overshoot/undershoot will make satisfying ringback specification very difficult. Violations Settling Limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions. signal settled close final value before next logic transition, then timing delay VREF succeeding transition vary slightly stored reactive energy inherited from previous transition. This akin "eye" patterns communication systems caused inter-symbol interference. resulting effect slight variation flight time. 4.1.3.1. Ringback Tolerance
Exceptions nominal overdrive requirement made when known that particular receiver's setup time specified manufacturer) relatively insensitive (less than 0.05 impact) well-controlled ringing into overdrive zone even brief re-crossing switching threshold, VREF. Such "ringback-tolerant" receivers give system designer more design freedom, and, exploited, least help maintain high system reliability. characterize ringback tolerance, employ idealized Lo-to-Hi input signal shown Figure corresponding waveform Hi-to-Lo transition shown Figure object ringback characterization determine range values different parameters shown diagram, which would maintain receiver setup time correct logic functionality. These parameters defined follows: minimum time that input must spend, after crossing VREF high level, before ring back, having overshot VIN_HIGH_MIN least while (defined below) some preset values, without increasing more than 0.05 Analogously Hi-to-Lo transitions.
nominal maximum ringback tolerated GTL+ receivers stated Table namely: closer VREF than ±200 overdrive zone. This requirement usually necessary guarantee that receiver meets specified minimum setup time (TSU), since set-up time usually degrades magnitude overdrive beyond switching threshold (VREF) reduced.
expected that larger overshoot smaller amount time, needed maintain setup time within +0.05 nominal value. given value likely that will longest slowest input edge rate V/ns.
PENTIUM® PROCESSOR 150, 166, 180,
Furthermore, there some dependence between lower starting voltages than VREF (for Lo-to-Hi transitions) reason described later Section 4.2.3.2. Minimum Set-up Hold Times.
rise/fall dges
start
+0.05ns
Clock
Figure Standard Input Lo-to-Hi Waveform Characterizing Receiver Ringback Tolerance
PENTIUM® PROCESSOR 150, 166, 180,
start
REF-
rise/fal Edges
Clock
+0.05ns
Time
Figure Standard Input Hi-to-Lo Waveform Characterizing Receiver Ringback Tolerance respectively, amplitude duration square-wave ringback, below threshold voltage (VREF), that receiver tolerate without increasing more than 0.05 given pair values. reason, receiver cannot tolerate ringback across reference threshold (VREF), then would negative number, infinite. Otherwise, expect inverse near-inverse) relationship between where more ringback, shorter time that ringback allowed last without causing receiver detect final minimum settling voltage, relative reference threshold (VREF), that input should return after ringback guarantee valid logic state internal flip-flop input. function input amplifier gain, differential mode offset, intrinsic maximum level differential noise. Specifying values responsibility receiver vendor. system designer should guarantee that signals arriving such receiver remain permissible region specified vendor parameters they correspond those idealized square waves Figure Figure instance, signal with ringback inside delineated have equal longer than minimum, equal larger than minimum also. receiver that does tolerate ringback would show following values above parameters: Tsu, -200 undefined, receiver which tolerates ringback would show following values above parameters: data sheet, -150 data sheet, tens (data sheet). Finally, receiver which tolerates ringback across switching threshold would show following values above parameters: data sheet, (data sheet), data sheet, tens where would usually brief amount time, yielding pulse "blip") beyond VREF.
4.1.4.
PENTIUM® PROCESSOR 150, 166, 180,
signal quality violations after input crosses VREF pad. Flight Time measurement similar simple Hi-to-Lo transition. Notice that timing measured driver receiver pins while signal integrity observed receiver chip pad. When signal integrity violates guidelines this specification, adjustments need made flight time, adjusted flight time obtained chip assumed have been obtained package pin, usually with small timing error penalty. 0.3V/ns edge rate will addressed later this document, since related conditions used specify GTL+ receiver's minimum set-up time. What meant edge rate neither instantaneous, strictly average. Rather, best described rising edge-by imagining V/ns line crossing VREF same moment that signal crosses extending VREF +200 with signal staying ahead (earlier time) that line times, until reaches VREF +200 Such requirement would always yield signals with average edge rate >0.3 V/ns, which could have instantaneous slopes that lower higher than 0.3V/ns, long they cause crossing inclined line.
Parameters: Flight Time
Signal Propagation Delay time between when signal appears driver time arrives receiver pin. Flight Time often used interchangeably with Signal Propagation Delay actually quite different. Flight time term timing equation that includes signal propagation delay, effects system driver, plus adjustments signal receiver needed guarantee receiver. More precisely, Flight Time defined time difference between when signal input receiving agent (adjusted meet receiver manufacturer's conditions required specifications) crosses VREF, time that output driving agent crosses VREF were driving test load used manufacturer specify that driver's timings. example simplest Flight Time measurement shown Figure receiver specification assumes that signal maintains edge rate greater than equal V/ns receiver chip OverDrive processor region from VREF VREF +200 rising edge that there
Figure Measuring Nominal Flight Time
PENTIUM® PROCESSOR 150, 166, 180,
either rising falling edge slower than 0.3V/ns through overdrive region beyond VREF, (i.e., does always stay ahead V/ns line), then flight time rising edge determined
extrapolating back from signal crossing VREF +200 VREF using V/ns slope indicated Figure
Figure Flight Time Rising Edge Slower Than 0.3V/ns signal monotonic while traversing overdrive region (VREF VREF +200 rising, VREF VREF-200 falling), rings back into overdrive region after crossing VREF, then flight time determined extrapolating back from last crossing VREF using line with slope V/ns (the maximum allowed rising edge rate). This yields VREF crossing point used flight time calculation. Figure represents situation where signal non-monotonic after crossing VREF rising edge. Figure shows falling edge that rings back into overdrive region after crossing VREF, 0.8V/ns line used extrapolate flight time. Since strict adherence edge rate specification required Hi-to-Lo transitions, some drivers' falling edges substantially faster than 0.8V/ns-at both fast slow corners-care should taken when using V/ns extrapolation. extrapolation invalid whenever yields VREF crossing that occurs earlier than when signal's actual edge crosses VREF. that case, flight time defined longer time when input receiver crosses VREF initially, when line extrapolated V/ns) crosses VREF. Figure illustrates situation where extrapolated value would used.
PENTIUM® PROCESSOR 150, 166, 180,
Figure Extrapolated Flight Time Non-Monotonic Rising Edge
Figure Extrapolated Flight Time Non-Monotonic Falling Edge maximum acceptable Flight Time determined net-by-net basis, usually different each unique driver-receiver pair. maximum acceptable Flight Time calculated using following equation (known setup time equation): TFLIGHT-MAX TPERIOD-MIN TCO-MAX +TSU-MIN +TCLK_SKEW-MAX +TCLK_JITTER-MAX Where, TCO-MAX maximum clock-to-out delay driving agent, TSU-MIN minimum setup time required receiver same net, TCLK_SKEWMAX maximum anticipated time difference between driver's receiver's clock inputs, TCLK_JITTER-MAX maximum anticipated edgeto-edge phase jitter. above equation should checked pairs devices nets bus.
minimum acceptable Flight Time determined following equation (known hold time equation): THOLD-MIN TFLIGHT-MIN +TCO-MIN TCLK_SKEW-MAX
PENTIUM® PROCESSOR 150, 166, 180,
Where, TCO-MIN minimum clock-to-out delay driving agent, THOLD-MIN minimum hold time required receiver, TCLK_SKEW-MAX defined above. Hold time equation independent clock jitter, since data released driver required held receiver same clock edge.
previous section. specifications must over possible operating conditions including temperature, voltage, semiconductor process. This information included designers components GTL+ bus. 4.2.1. Buffer Specification
Notes
4.2.
General GTL+ Buffer Specification
Table contains Buffer parameters.
This specification identifies parameters driver, receiver, package that must operate system environment described Table Buffer Parameters Symbol VILC CIN, NOTES:
Measured into test load tied shown Figure VREF VTT. (VTT ±10%), VREF additional tolerance This parameter inputs without internal pull-ups pull downs VTT. Total capacitance, seen from attachment node network, which includes traces PCB, socket, component package, driver/receiver capacitance, structure capacitance.
Parameter Driver Output Voltage Receiver Input High Voltage Receiver Input Voltage Input Leakage Current Total Input/Output Capacitance
0.600
Units
VREF VREF
4.2.2. Symbol dV/dt EDGE dV/dt EDGE THOLD NOTES:
PENTIUM® PROCESSOR 150, 166, 180,
Buffer Specification
Table contains Buffer parameters. Table Buffer Parameters Parameter Output Signal Edge Rate, rise Output Signal Edge Rate, fall Output Clock Data Time Input Setup Time Input Hold Time -0.8 spec spec spec Unit V/ns V/ns Figure Figure Figure Figure Notes
This maximum instantaneous dV/dt over entire transition range (Hi-to-Lo Lo-to-Hi) measured driver's output while driving Ref8N network, with driver package model located near center network (see Section 4.4). These design targets. acceptance buffer also based resultant signal quality. addition edge rate, shape rising edge also have significant effect buffer's performance, therefore driver must also meet signal quality criteria next section. example, rising linear ramp 0.8V/ns will generally produce worse signal quality (more ringback) than edge that rolls approaches even though might have exceeded that rate earlier. Hi-to-Lo edge rates exceed this specification produce acceptable results with corresponding reduction VOL. instance, buffer with falling edge rate larger than 1.5V/ns been deemed acceptable because produced less than Lo-to-Hi edges must meet both signal quality maximum edge rate specifications. minimum edge rate design target, slower edge rates acceptable, although there timing impact associated with them form increase flight time, since signal receiver will longer meet required conditions TSU. Refer Section 4.1.4 computing flight time more details effects edge rates slower than V/ns. These values specific this specification, they dependent location driver along network system requirements such number agents, distances between agents, construction (Z0, trace width, trace type, connectors), sockets being used, any, value termination resistors. Good targets components used 8-load 66.6 system would TCO_MAX TCO_MIN This value specified output device. should measured test probe point shown Figure delay caused transmission line must subtracted from measurement achieve accurate value output device. simulation purposes, tester load represented single termination resistor connected directly device. Section 4.2.3 description procedure determining receiver's minimum required setup hold times.
4.2.2.1.
Output Driver Acceptance Criteria mentioned note previous section, criteria acceptance output driver relate edge rate signal quality Lo-to-Hi transition, primarily signal quality Hi-to-Lo transition when device, with targeted package, simulated into Ref8n network (Figure 36). edge rate portion specification good initial target, insufficient guaranteeing acceptable performance.
Although Section 4.1.4 describes ways amending flight time receiver when edge rate lower than requirements shown Table when there excessive ringing, still preferable avoid slow edge rates excessive ringing through good driver system design, hence criteria presented this section.
PENTIUM® PROCESSOR 150, 166, 180,
Since Ref8N worst case network, expected modeled without many real system effects (e.g., inter-trace crosstalk, losses), required signal quality slightly different than that specified Section 4.1.3 this document. signal quality criterion acceptable driver design that signals produced driver fastest corner) Ref8N receiver pads must remain outside shaded areas shown Figure Simulations must performed both device operating extremes: fast process corner high temperature, slow process corner high temperature, both rising falling edges. clock frequency should desired maximum (e.g. 66.6 MHz, higher), simulation results should analyzed both from quiescent start (i.e., first cycle simulation), when preceded least previous transition (i.e. subsequent simulation cycles). boundaries keep-out area Lo-to-Hi transition formed vertical line start receiver setup window distance TSU' from next clock edge), 0.3V/ns ramp line passing through intersection between VREF +100 level (the assumed extra noise)
beginning setup window, horizontal line VREF +300 (which covers specified overdrive, margin extra noise coupled waveform), finally vertical line behind Clock THD'. keep-out zone Hi-to-Lo transition uses analogous boundaries other direction. Raising VREF assumed equivalent having extra noise coupled waveform giving more downward ringback, such coupled noise could come from variety sources such trace-to-trace coupling. TSU' receiver`s setup time plus board clock driver clock distribution skew jitter, plus additional number that inherited from driver's internal timings described next). Since buffer designer will most likely simulating driver circuit alone, certain delays that TCO, such on-chip clock phase shift, clock distribution skew, jitter, plus other data latch JTAG delays would missing. easier these numbers added TSU, yielding TSU' making driver simulation simpler. example, assume clock generation distribution skew plus jitter unmodeled delays driver typically about this yields total TSU'
PENTIUM® PROCESSOR 150, 166, 180,
Figure Acceptable Driver Signal Quality
Figure Unacceptable signal, Excessively Slow Edge After Crossing VREF
PENTIUM® PROCESSOR 150, 166, 180,
4.2.3.
THD' receiver's hold time plus board clock driver clock distribution skew minus driver's on-chip clock phase shift, clock distribution skew, jitter, plus other data latch JTAG delays (assuming these driver numbers included driver circuit simulation, done setup above paragraph). Note that THD' being negative number, i.e. ahead clock, rather than after That would acceptable, since that equivalent shifting driver output later time these extra delays been added driver opposed setup hold. When using Ref8N validate driver design, recommended that relevant combinations driver receiver locations checked. with other buffer technologies, such CMOS, given buffer design guaranteed always meet requirements possible system network topologies. Meeting acceptance criteria listed this document helps ensure buffer used variety GTL+ applications, system designer's responsibility examine performance buffer specific application ensure that GTL+ networks meet signal quality requirements.
Determining Clock-To-Out, Setup Hold
This section describes determine setup, hold clock timings. 4.2.3.1. Clock-to-Output Time,
measured using test load Figure delay from crossing point clock signal clock input device, VREF crossing point output signal output device. simulation purposes, test load replaced electrical equivalent, which single resistor connected directly package terminated production test environment, nearly impossible measure directly output device, instead, test performed finite distance away from compensated finite distance. test load circuit shown Figure takes this into account making this finite distance transmission line. exact timings output pin, propagation delay along transmission line must subtracted from measured value probe point.
Figure Test Load Measuring Output Timings
PENTIUM® PROCESSOR 150, 166, 180,
Figure Clock Output Data Timing (TCO) shaping logic gates, edge-triggered pulse-triggered) flip-flop. output flipflop must monitored. receiver's Lo-to-Hi setup time should determined using nominal input waveform like shown Figure (solid line). Loto-Hi input starts VIN_LOW_MAX (VREF goes VIN_HIGH_MIN VREF +200 slow edge rate V/ns, with process, temperature, voltage, VREF_INTERNAL receiver worst (longest TSU) corner values. Here, VREF external (system) reference voltage device pin. tolerance (1.5V, ±10%) voltage divider generating system VREF from (±2%), VREF shift around maximum ±122 When determining setup time, internal reference voltage VREF_INTERNAL reference gate diff. amp.) must value which yields longest setup time. Here, VREF_INTERNAL VREF ±(122 +VNOISE). Where, VNOISE maximum differential noise amplitude component's internal VREF distribution amplifier's reference input gate) comprising noise picked connection from VREF package input amp. Analogously, setup time Hi-to-Lo transitions (Figure 35), input starts VIN_HIGH_MIN VREF +200 drops
measurement Lo-to-Hi signal transition shown Figure measurement Hi-toLo transitions similar. 4.2.3.2. Minimum Setup Hold Times
Setup time GTL+ (TSU) defined minimum time from input signal crossing VREF clock receiver crossing level, which guarantees that input buffer captured data input pin, given infinite hold time. Strictly speaking, setup time must determined when input barely meets minimum hold time (see definition hold time below). However, current GTL+ systems, hold time should well beyond minimum required cases where setup critical. This because setup critical when receiver removed from driver. such cases, signal will held receiver long time after clock, since change needs long time propagate from driver receiver. recommended procedure buffer designer extract outlined below. employs additional steps, would beneficial that such extra steps documented with results this receiver characterization: full receiver circuit must used, comprising input differential amplifier,
PENTIUM® PROCESSOR 150, 166, 180,
VIN_LOW_MAX VREF rate 0.3V/ns. both V/ns edge rate faster edge rates V/ns Lo-to-Hi, V/ns Hi-to-Lo -dashed lines Figure Figure 35), must ensure that lower starting voltages input swing (VSTART range `VREF-200 Lo-to-Hi transitions,
`VREF+200 Hi-to-Lo transitions -dashed lines Figure Figure require made longer. This step needed since lower starting voltage cause input differential amplifier require more time switch, having been deeper saturation initial state.
VREF
VREF
VREF-
Clock Vstart
Time
Figure Standard Input Lo-to-Hi Waveform Characterizing Receiver Setup Time
start
PENTIUM® PROCESSOR 150, 166, 180,
Figure Standard Input Hi-to-Lo Waveform Characterizing Receiver Setup Time Hold time GTL+ THOLD, defined minimum time from clock receivers crossing level receiver input signal crossing VREF, which guarantees that input buffer captured data receiver input signal pin, given infinite setup time. Strictly speaking, hold time must determined when input barely meets minimum setup time (see definition setup time above). However, current GTL+ systems, setup time expected met, well beyond minimum required cases where hold critical. This because hold critical when receiver very close driver. such cases, signal will arrive receiver shortly after clock, hence meeting setup time with comfortable margin. recommended procedure extracting THOLD outlined below. employs additional steps, would beneficial that such extra steps documented with results this receiver characterization: full receiver circuit must used, comprising input differential amplifier, shaping logic gates, edge-triggered pulse-triggered) flip-flop. output flipflop must monitored.
Clock
Time
receiver's Lo-to-Hi hold time should determined using nominal input waveform that starts VIN_LOW_MAX (VREF goes VTT, fast edge rate 0.8V/ns, with process, temperature, voltage, VREF_INTERNAL receiver fastest best) corner values (yielding longest THOLD). Here, VREF external (system) reference voltage device pin. tolerance (1.5 ±10%) voltage divider generating system VREF from (±2%), VREF shift around maximum ±122 When determining hold time, internal reference voltage VREF_INTERNAL reference gate diff. amp.) must value which yields worst case hold time. Here, VREF_INTERNAL VREF (122 +VNOISE). Where, VNOISE maximum differential noise amplitude component's internal VREF distribution amplifier's reference input gate) comprising noise picked connection from VREF package input amp. Analogously, hold time Hi-to-Lo transitions, input starts VIN_HIGH_MIN VREF +200 drops rate 3V/ns.
PENTIUM® PROCESSOR 150, 166, 180,
4.2.3.3. Receiver Ringback Tolerance
Refer Section 4.1.3.1 complete description definitions methodology determining receiver ringback tolerance. 4.2.4. System-Based Calculation Required Input Output Timings
time remaining TCO-MAX TSU-MIN split ~60/40% (recommendation). Therefore, this example, TCO-MAX would TSU-MIN NOTE This numerical example, does necessarily apply particular device. Off-end agents will have less distance farthest receiver, therefore will have shorter flight times. values longer than example above necessarily preclude high-frequency (e.g. 66.6 MHz) operation, will result placement constraints device, such being required placed middle daisy-chain bus. 4.2.5. Calculating Target THOLD-MIN
Below sample calculations. first determines TCO-MAX TSU-MIN, while second determines THOLD-MIN. These equations used system replacing assumptions listed below, with actual system constraints. 4.2.4.1. Calculating Target TCO-MAX, TSU-MIN
TCO-MAX TSU-MIN calculated from Setup Time equation given earlier Section 4.1.4: TFLIGHT-MAX TPERIOD-MIN TCO-MAX +TSU-MIN +TCLK_SKEW-MAX +TCLK_JITTER-MAX) example, identical agents located opposite ends network with flight time other assumptions listed below, following calculations TCO-MAX TSU-MIN done:
calculate longest possible minimum required hold time target value, assume that TCO-MIN fourth TCO-MAX, hold time equation given earlier. Note that Clock Jitter part equation, since data released driver must held receiver relative same clock edge: THOLD-MIn TFLIGHT-MIN +TCO-MIN TCLK_SKEW-MAX
Assumptions: Assumptions:
TPERIOD-MIN TFLIGHT-MAX (66.6 MHz) (given flight time) (0.5ns driver) board (Clock TCO-MIN TCO-MAX (Max clock data time) (Assumed max) skew) TFLIGHT-MIN THOLD-MIN (Min 0.5" ns/inch) (Minimum signal hold time) (Driver
TCLK_SKEW-MAX (0.2 skew) TCLK_JITTER-MAX phase error) TCO-MAX TSU-MIN time) time)
TCLK_SKEW-MAX receiver
(Clock output data (Required input setup
Calculation:
THOLD-MIN +1.0 THOLD-MIN NOTE This numerical example, does necessarily apply particular device.
Calculation:
(TCO-MAX +TSU-MIN +0.7 +0.2) TCO-MAX +TSU-MIN
4.3.
4.3.1.
PENTIUM® PROCESSOR 150, 166, 180,
socket around electrical length. package, which typically requires short stub from landing (~50 ps), package lead frame length should less than ~200 4.3.2. Package Capacitance
Package Specification
This information also included designers components GTL+ bus. package that transceiver will placed into must adhere critical parameters. They package trace length, (the electrical distance from die), package capacitance. specifications package trace length package capacitance explicit, implied system buffer specifications. Package Trace Length
System specification requires that signals routed daisy chain fashion, that stub network exceed electrical length. stub includes printed circuit board (PCB) routing package from "Daisy Chain" net, well socket necessary, trace length package interconnect (i.e. electrical length from pin, through package, across bond wire necessary, die). example, package, which allows routing both from soldered PCB, maximum package trace length cannot exceed package socketed, maximum package trace length would ~225 since typical
maximum package capacitance function Input/Output capacitance transceiver. Buffer specification requires total package capacitance, output driver, input receiver structures, seen from pin, less than Thus, larger transceiver capacitance, smaller allowable package capacitance.
4.4.
Ref8N Network
Ref8N network shown Figure which represents eight-node reference network (hence name Ref8N), used characterize drivers' behavior into known environment. This network worst case, representative sample typical system environment. SPICE deck network also given.
PENTIUM® PROCESSOR 150, 166, 180,
volts ohms 0.07 0.105 1.8nS/ft. ohms nS/ft. ohms 0.07 0.105 nS/ft. ohms 0.25 nS/ft. ohms nS/ft. ohms
REF8N Topology:
volts ohms
0.10
0.07
0.105
nS/ft. ohms nS/ft. ohms
0.10
1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft. ohms ohms ohms ohms
1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft. ohms ohms ohms ohms
0.10
0.07
0.105 nS/ft. ohms
0.10
1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft. ohms ohms ohms ohms
1.02 nS/ft. 3.08nS/ft. 2.1nS/ft. 1.4nS/ft. ohms ohms ohms ohms
2.4nS/ft. ohms
0.25 nS/ft. ohms nS/ft. ohms
2.4nS/ft. ohms
2.4nS/ft. ohms
0.25 nS/ft. ohms
2.4nS/ft. ohms
0.25 nS/ft. ohms nS/ft. ohms
Place ASIC driver tested here
Replace with ASIC model
Figure Ref8N Topology
4.4.1. Ref8N HSPICE Netlist $REF8N, DC(vtt) rterm (R=42) crterm line1 Z0=72 TD=.075NS line1 load1 socket load1 load1a Z0=42 TD=230PS load1a CPU_1 Z0=200 TD=8.5PS CCPU_1 CPU_1 line1 line2 Z0=72 TD=568PS line2 load2 socket load2 load2a Z0=42 230ps Pull-up termination resistance Pull-up termination capacitance link from terminator load Socket model package model Bondwire input capacitance
trace between packages Socket model worst case package
PENTIUM® PROCESSOR 150, 166, 180,
Bondwire input capacitance trace between packages trace from landing ASIC package ASIC input capacitance (die capacitance) trace between packages trace from landing ASIC package ASIC input capacitance (die capacitance) trace between packages trace from landing Replace these lines with equivalent model your package. (This model should include package pin, package trace, bond wire capacitance that already included your driver model.) trace between packages trace from landing ASIC package ASIC input capacitance trace between packages Socket model worst case package Bondwire input capacitance trace between packages Socket model worst case package Bondwire input capacitance
load2a p6_2 Z0=200 TD=8.5ps CCPU_2 p6_2 line2 line3 Z0=72 TD=568ps line3 load3 Z0=50 TD=50ps load3 asic_1 Z0=75 TD=180PS CASIC_1 asic_1 6.5PF line3 line4 Z0=72 TD=403PS line4 load4 Z0=50 TD=50PS load4 asic_2 Z0=75 TD=180PS CASIC_2 asic_2 6.5PF line4 line5 Z0=72 TD=403PS line5 load5 Z0=50 TD=50PS load5 asic_3 Z0=75 TD=180PS CASIC_3 asic_3 6.5PF
line5 line6 Z0=72 TD=403PS line6 load6 Z0=50 TD=50PS load6 asic_4 Z0=75 TD=180PS CASIC_4 asic_4 6.5PF line6 line7 Z0=72 TD=403PS line7 load7 socket load7 load7a Z0=42 TD=230PS load7a p6_3 Z0=200 TD=8.5PS CCPU_3 p6_3 line7 line8 Z0=72 TD=568PS line8 load8 socket load8 load8a Z0=42 TD=230PS load8a p6_4 Z0=200 TD=8.5PS CCPU_4 p6_4 line8 R_TERM Z0=72 TD=75PS Rterm1 R_TERM (R=42) CRTERM1 R_TERM (C=2PF) Rout bond asic_3.001 .subckt socket
trace termination resistor Pull-up termination resistance Pull-up termination capacitance
Socket model
PENTIUM® PROCESSOR 150, 166, 180,
Z0=40 TD=12.25PS Z0=66 TD=12.25ps .ENDS
Tolerant Signal Quality Specifications
signals that tolerant should also meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect long term reliability component. There three signal quality parameters defined tolerant signals. They Overshoot/Undershoot, Ringback Settling Limit. three signal quality parameters shown Figure Pentium® Processor Buffer Models-IBIS Format world wide page http://www.intel.com) contain models simulating tolerant signal distribution.
5.1.
OVERSHOOT/UNDERSHOOT GUIDELINES
Overshoot undershoot) absolute value maximum voltage allowed above nominal high voltage below VSS.
overshoot/undershoot guideline limits transitions beyond VCCP fast signal edge rates. Figure processor damaged repeated overshoot events tolerant buffers charge large enough (i.e. overshoot great enough). However, excessive ringback dominant harmful effect resulting from overshoot undershoot (i.e. violating overshoot/undershoot guideline will make satisfying ringback specification difficult). overshoot/undershoot guideline assumes absence diodes input. These guidelines should verified simulations without on-chip protection diodes present because diodes will begin clamping tolerant signals beginning approximately above VCCP below VSS. signals reaching clamping voltage, then this issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
PENTIUM® PROCESSOR 150, 166, 180,
Figure Tolerant Signal Overshoot/Undershoot Ringback
5.2.
RINGBACK SPECIFICATION
5.3.
SETTLING LIMIT GUIDELIN
Ringback refers amount reflection seen after signal undergone transition. ringback specification voltage that signal rings back after achieving farthest excursion. Figure illustration ringback. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal Ringback specification allowed under circumstances. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications Non-GTL+ signals Table Signal Ringback Specifications Transition Maximum Ringback (with input diodes present)
Settling Limit defines maximum amount ringing receiving that signal must limited before next transition. amount allowed total signal swing (VHI-VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify Settling Limit done either with without input protection diodes present. Violation Settling Limit guideline acceptable simulations 5-10 successive transitions show amplitude ringing increasing subsequent transitions.
6.0.
THERMAL SPECIFICATIONS
Table specifies Pentium processor power dissipation. highly recommended that systems designed dissipate least 35-40W processor allow same design accommodate
PENTIUM® PROCESSOR 150, 166, 180,
higher frequency otherwise enhanced members Pentium processor family.
6.1.
Thermal Parameters
This section defines terms used Pentium processor thermal analysis. 6.1.1. AMBIENT TEMPERATUR
different temperature from surrounding ambient air, errors could introduced measurements handled properly. measurement errors could having poor thermal contact between thermocouple junction surface, heat loss radiation, conduction through thermocouple leads. minimize measurement errors, following approach recommended: gauge K-type thermocouple equivalent. Attach thermocouple bead junction package surface location corresponding center Pentium processor die. (Location Figure Using center Pentium processor gives more accurate measurement less variation boundary condition changes Attach thermocouple bead junction angle adhesive bond (such thermal grease heat-tolerant tape) package surface shown Figure When heat sink attached, hole should drilled through heat sink allow probing Pentium processor package above center Pentium processor die. hole diameter should larger than 0.150."
Ambient temperature, temperature ambient surrounding package. system environment, ambient temperature temperature upstream from package close vicinity; active cooling system, inlet active cooling device. 6.1.2. CASE TEMPERATUR
ensure functionality reliability, Pentium processor specified proper operation when (case temperature) within specified range Table Special care required when measuring case temperature ensure accurate temperature measurement. Thermocouples often used measure Before temperature measurements, thermocouples must calibrated. When measuring temperature surface which
2.46"
PENTIUM® PROCESSOR 150, 166, 180,
2.66"
1.23"
Cache
0.80"
Figure Location Case Temperature Measurement (Top-side View)
Probe Heat Spreader
Heat Sink
Thermal Interface Material
Ceramic Package
Ceramic Package
Figure Thermocouple Placement 6.1.3. THERMAL RESISTANCE thickness thermal interface used. measure thermal resistance from cooling solution local ambient air. values depend material, thermal conductivity, geometry thermal cooling solution well airflow rates.
thermal resistance value case-toambient, used measure cooling solution's thermal performance. comprised case-to-sink thermal resistance, sink-to-ambient thermal resistance, measure thermal resistance along heat flow path from package bottom thermal cooling solution. This value strongly dependent material, conductivity,
PENTIUM® PROCESSOR 150, 166, 180,
parameters defined following relationships where measured °C/W (See also Figure 40.):
Ambient Thermal Interface Material
Heat Sink
Where: Case-to-Ambient thermal resistance Case-to-Sink thermal resistance Sink-to-Ambient thermal resistance Case temperature defined location (°C) Ambient temperature (°C) Device power dissipation
Ceramic Package
Heat Spreader
Figure Thermal Resistance Relationships
6.2.
Thermal Analysis
Table below lists case-to-ambient thermal resistances Pentium processor different flow rates heat sink heights. Table Case-To-Ambient Thermal Resistance [°C/W] Airflow [Linear Feet Minute] Heat Sink Height1 Airflow (LFM): With 0.5" Heat Sink With 1.0" Heat Sink With 1.5" Heat Sink With 2.0" Heat Sink NOTES:
data taken level. altitudes above level, recommended that derating factor 1°C/1000 feet used. Heat Sink: 2.235" square omni-directional pin, aluminum heat sink with thickness 0.085", spacing 0.13" base thickness 0.15". Figure thin layer thermal grease (Thermoset TC208 with thermal conductivity 1.2W/m-°K) used interface material between heat sink package.
2.55 1.66 1.47
3.16 1.66 1.31 1.23
2.04 1.08 0.90 0.87
1.66 0.94 0.78 0.75
1.41 0.80 0.71 0.69
1000 1.29 0.76 0.67 0.65
0.150"
PENTIUM® PROCESSOR 150, 166, 180,
0.085"
0.130"
Height
2.235"
Figure Analysis Heat Sink Dimensions
Table shows required given 29.2 processor (150 MHz, 256K cache), 85°C. Table shows required assuming processor. Table Table were produced using relationships Section 6.1.3. data Table Table Ambient Temperature Required Heat Sink Height 29.2 Case Airflow [Linear Feet Minute] Heat Sink Height1 Airflow (LFM): With 0.5" Heat Sink With 1.0" Heat Sink With 1.5" Heat Sink With 2.0" Heat Sink NOTES:
level. Table Heat Sink design Table
1000
PENTIUM® PROCESSOR 150, 166, 180,
1000
Table Ambient Temperature Required Heat Sink Height Case Airflow [Linear Feet Minute] Heat Sink Height1 Airflow (LFM): With 0.5" Heat Sink With 1.0" Heat Sink With 1.5" Heat Sink With 2.0" Heat Sink NOTES:
level. Table Heat Sink design Table
7.0.
MECHANICAL SPECIFICATIONS
Pentium processor packaged modified staggered ceramic grid array (SPGA) with gold plated Copper-Tungsten (CuW) heat spreader top. Mechanical specifications assignments follow.
with package dimensions Pentium processor Figure shows view with dimensions. Figure view Pentium processor with VCCP, VCCS, VCC5, locations shown. sure read Section mechanical constraints OverDrive processor. Also, investigate tools that will used debug system before laying system.
7.1.
Dimensions
mechanical specifications provided Table Figure shows bottom side views
PENTIUM® PROCESSOR 150, 166, 180,
Figure Package Dimensions (Bottom View)
PENTIUM® PROCESSOR 150, 166, 180,
2.66 0.10" 2.225 0.10"
2.46 0.10" 1.30 0.10"
HEAT SPREADER
Keep Zones
1.025"
0.380" 0.195" 0.380"
Figure View Keep Zones Heat Spreader
Table Pentium® Processor Package Parameter Package Type Total Pins Array Package Size Heat Spreader Size Approximate Weight Modified Staggered 2.66" 2.46" (7.76cm 6.25cm) 2.225" 1.3" 0.04" (5.65cm 3.3cm 0.1cm) grams Value
PENTIUM® PROCESSOR 150, 166, 180,
VccS VccP Vcc5 Other
2H2O
Figure Pentium® Processor View with Power Locations
7.2.
Pinout
Table listing number order. Table listing name order. Please Section 3.8. determine signal's type.
signals described Appendix other pins described Section Table
PENTIUM® PROCESSOR 150, 166, 180,
Signal Name D21# A29# A30# A32# A33# A34# D22# D23# D25# D24# D26# VCCP VCCP VCCP VCCP A22# A24# A27# A26# A31# D27# D29# D30# D28# D31# A19# A21#
Table Listing Order Signal Name VREF0 STPCLK# TRST# IGNNE# A20M# FLUSH# THERMTRIP# BCLK RESERVED TESTHI TESTHI D14# D10# D11# D13# D16# VREF4 CPUPRES# VCCP VCCP VCCP Signal Name VCCP VCCP VCCP VCCP A35# IERR# BERR# VREF1 FRCERR INIT# FERR# PLL1 TESTLO PLL2 D12# D15# D17# D20# D18# D19#
Signal Name A20# A23# A28# D32# D35# D38# D33# D34# VCCP VCCP RESERVED A16# A15# A18# A25# D37# D40# D43# D36# D39# A12# A14# A11# A13# A17#
PENTIUM® PROCESSOR 150, 166, 180,
Table Listing Order (Continued) Signal Name D44# D45# D47# D42# D41# VCCP VCCP VCCP VCCP A10# D51# D52# D49# D48# D46# VREF2 AP1# D59# D57# D54# Signal Name D53# D50# VCCP VCCP AP0# RSP# BPRI# BNR# BR3# DEP7# VREF6 D60# D56# D55# SMI# BR1# REQ4# REQ1# REQ0# DEP2# DEP4# D63# D61# D58#
PENTIUM® PROCESSOR 150, 166, 180,
AF46 AG39 AG41 AG43 AG45 AG47 AJ39 AJ41 AJ43 AJ45 AJ47 AL39 AL41 AL43 AL45 AL47 Signal Name VCC5 RESERVED PWRGOOD RESERVED RESERVED LINT1/NMI LINT0/INTR VREF7 RESERVED VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
Table Listing Order (Continued) AA39 AA41 AA43 AA45 AA47 Signal Name VCCP VCCP REQ3# REQ2# DEFER# VREF3 TRDY# PRDY# RESET# DEP1# DEP6# D62# BR2# DRDY# DBSY# HITM# LOCK# BPM1# PICD0 PICCLK PREQ# DEP5# VCCP AB40 AB42 AB44 AB46 AC39 AC41 AC43 AC45 AC47 AE39 AE41 AE43 AE45 AE47 AF40 AF42 AF44 Signal Name VCCP RESERVED HIT# BR0# RS0# BP3# BPM0# BINIT# DEP0# DEP3# RESERVED ADS# RS1# RS2# AERR# TESTHI PICD1 BP2# RESERVED VREF5
AN39 AN41 AN43 AN45 AN47 AQ39 AQ41 AQ43 AQ45 AQ47 AS39 AS41 AS43 AS45 AS47 Signal Name VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VID0 VID1 VID2 VID3 RESERVED TESTLO TESTLO TESTLO TESTLO RESERVED VCCS
PENTIUM® PROCESSOR 150, 166, 180,
Table Listing Order (Continued) AU39 AU41 AU43 AU45 AU47 AW39 AW41 AW43 AW45 AW47 AY39 AY41 AY43 AY45 AY47 Signal Name VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS BA11 BA13 BA15 BA17 BA19 BA21 BA23 BA25 BA27 BA29 BA31 BA33 BA35 BA37 BA39 BA41 BA43 BA45 BA47 BC11 BC13 BC15 BC17 Signal Name VCCS RESERVED TESTLO TESTLO VCCP VCCP VCCP VCCP TESTLO RESERVED TESTLO VCCS VCCS RESERVED TESTLO TESTLO
PENTIUM® PROCESSOR 150, 166, 180,
BC39 BC41 BC43 BC45 BC47 Signal Name
Table Listing Order (Continued) BC19 BC21 BC23 BC25 BC27 Signal Name VCCS VCCS VCCS BC29 BC31 BC33 BC35 BC37 Signal Name VCCS TESTLO RESERVED TESTLO
Signal Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32#
PENTIUM® PROCESSOR 150, 166, 180,
Table Listing Alphabetic Order Signal Name A33# A34# A35# ADS# AERR# AP0# AP1# BCLK BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1# BR2# BR3# CPUPRES# AC43 AE43 AC39 AC41 AA39 Signal Name D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40#
PENTIUM® PROCESSOR 150, 166, 180,
Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1# RS2# RSP# SMI# STPCLK# TESTHI TESTHI TESTHI TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO AE45 AG39 AG47 AS47 BA11 BA35 BC11 BC35 AE39 AS39 AS41 AS43 AS45 BA13
Table Listing Alphabetic Order (Continued) Signal Name D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# AC45 AC47 AA47 Signal Name DEP6# DEP7# DRDY# FERR# FLUSH# FRCERR HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED AG43 AG41 AA43 AA41 AE41 AA45
Signal Name TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO THERMTRIP# TRDY# TRST# VCC5 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP BA15 BA33 BA37 BC13 BC15 BC33 BC37
PENTIUM® PROCESSOR 150, 166, 180,
Table Listing Alphabetic Order (Continued) Signal Name VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCS VCCS AB44 AJ41 AJ45 AL39 AL43 AL47 AN41 AN45 AQ39 AQ43 AQ47 BA17 BA21 BA25 BA29 Signal Name VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VCCS VID0 VID1 VID2 VID3 VREF0 AU39 AU43 AU47 AW41 AW45 AY39 AY41 AY43 AY45 AY47 BA41 BA45 BC19 BC23 BC27 BC31
PENTIUM® PROCESSOR 150, 166, 180,
Signal Name AL41 AL45 AN39 AN43 AN47 AQ41 AQ45 AU41 AU45 AW39 AW43 AW47 BA19 BA23 BA27 BA31 BA39 BA43
Table Listing Alphabetic Order (Continued) Signal Name VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7 AE47 AG45 Signal Name AB40 AB42 AB46 AF40 AF42 AF44 AF46 AJ39 AJ43 AJ47
Signal Name BA47
PENTIUM® PROCESSOR 150, 166, 180,
Table Listing Alphabetic Order (Continued) Signal Name BC17 BC21 BC25 BC29 Signal Name BC39 BC41 BC43 BC45 BC47
8.0.
OVERDRIVE® PROCESSOR SOCKET SPECIFICATION Introduction
8.1.
Intel will offer future OverDrive processors Pentium processor. This OverDrive processor will based faster, future Intel processor core. future OverDrive processor Pentium processor-based systems processor upgrade that will make software faster existing Pentium processor system. OverDrive processor binary compatible with Pentium processor. OverDrive processor intended replacement upgrade single dual processor Pentium processor designs. OverDrive processor will equipped with integral fan/heatsink retention clips. Intel plans ship OverDrive processors with matched Voltage Regulator Module (OverDrive VRM). support processor upgrades, Zero Insertion Force (ZIF) socket (Socket Voltage Regulator Module connector (Header have been defined along with Pentium processor. Header populated with Pentium processor with OverDrive which Intel plans ship with OverDrive processor part retail package. OverDrive processor will also support Voltage Identification described Section 3.6. four Voltage outputs (VID0-VID3) used design programmable power supply that will meet power requirements both Pentium OverDrive processors Header described this section, motherboard. plan design programmable supply OverDrive processor, please contact Intel additional information.
single socket system should include Socket Header When this system configuration upgraded, Pentium processor replaced with future OverDrive processor Pentium processor-based systems matching OverDrive VRM. OverDrive capable delivering lower voltage higher current required upgrade. Other voltage regulation configurations described Section 8.3.2. 8.1.1. TERMINOLOGY
Header 40-pin Voltage Regulator Module (VRM) connector defined contain OverDrive VRM.
OverDrive® Processor: processor Pentium systems. future OverDrive processor-based
OverDrive® VRM: designed provide specific voltage required future OverDrive processor Pentium processor-based systems. Socket 387-pin SPGA Zero Insertion Force (ZIF) socket defined contain either Pentium OverDrive processor.
8.2.
Mechanical Specifications
This section specifies mechanical features Socket Header This section includes pinout, surrounding space requirements, standardized clip attachment features. Figure shows mechanical representation OverDrive processor Socket OverDrive Header
PENTIUM® PROCESSOR 150, 166, 180,
8.2.1. VENDOR CONTACTS SOCKET HEADER
Contact your local Intel representative list participating Socket Header suppliers. 8.2.2. SOCKET DEFINITION Socket 387-pin, modified staggered grid array (SPGA), Zero Insertion Force (ZIF) socket.
pinout identical Pentium processor. pins used support on-package fan/heatsink included OverDrive processor indicate presence OverDrive processor. OverDrive processor package oriented Socket asymmetric interstitial pins. Standardized heat sink clip attachment tabs also defined part Socket (Section 8.2.2.3.).
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Voltage Regulator Module Airspace
Header
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Fan/Heatsink
Figure Socket Shown with Fan/heatsink Cooling Solution, Clip Attachment Features Adjacent Voltage Regulator Module
Socket
8.2.2.1.
PENTIUM® PROCESSOR 150, 166, 180,
Descriptions upgrade specific pins p
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