SBVS012B DECEMBER 2000 REVISED OCTOBER 2004 Miniature, Isolated U

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SBVS012B DECEMBER 2000 REVISED OCTOBER 2004 Miniature, Isolated U

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DCP01B SERIES
SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
Miniature, Isolated UNREGULATED DC/DC CONVERTERS
FEATURES Efficiency Thermal Protection Device-to-Device Synchronization Short-Circuit Protection EN55022 Class Performance UL1950 Recognized Component JEDEC DIP-14 SOP-14 Packages APPLICATIONS Point-of-Use Power Conversion Ground Loop Elimination Data Acquisition Industrial Control Instrumentation Test Equipment DESCRIPTION
DCP01B series family unregulated, isolated DC/DC converters. Requiring minimum external components including on-chip device protection, DCP01B series provides extra features such output disable synchronization switching frequencies. highly-integrated package design results highly reliable products with power density 40W/in3 (2.4W/cm3). This combination features small sizes makes DCP01B suitable wide range applications.
SYNCOUT
800kHz Oscillator
Reset
VOUT
Power Stage
SYNCIN
Watch- dog/ start-
herm Shutdown
IBIAS
Power Controller
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2000-2004, Texas Instruments Incorporated
www.ti.com
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) DCP01B SERIES models Input voltage Storage temperature Lead temperature (soldering, 10s)
SUPPLEMENTAL ORDERING INFORMATION
UNIT
Basic Model Number: Product Voltage Input: Voltage Output: Dual Output: Model Revision: Package Code: DIP-14 SOP-14 (Gullwing) DCP01
+125 +270
models models
Stresses above these ratings cause permanent damage. Exposure absolute maximum conditions extended periods degrade device reliability. These stress ratings only, functional operation device these other conditions beyond those specified implied.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA
SINGLE VOLTAGE(3) DIP-14 DCP010505 SOP-14(4) DIP-14 DCP010512 SOP-14(4) DIP-14 DCP010515 SOP-14(4) DIP-14 DCP012405 DUAL VOLTAGE(3) DIP-14 DCP010505 SOP-14(4) DIP-14 DCP010512 SOP-14(4) DIP-14 DCP010515 SOP-14(4) DIP-14 DCP011512 SOP-14(4) DIP-14 DCP011515 SOP-14(4) DIP-14 DCP012415
-40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C
DCP010505BP DCP010505BP-U DCP010512BP DCP010512BP-U DCP010515BP DCP010515BP-U DCP012405BP DCP012405BP-U
DCP010505BP DCP010505BP-U/700 DCP010512BP DCP010512BP-U/700 DCP010515BP DCP010515BP-U/700 DCP012405BP DCP012405BP-U/700
Rails Tape Reel Rails Tape Reel Rails Tape Reel Rails Tape Reel
SOP-14(4)
-40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C -40°C +100°C
DCP010505DBP DCP010505DBP-U DCP010512DBP DCP010512DBP-U DCP010515DBP DCP010515DBP-U DCP011512DBP DCP011512DBP-U DCP011515DBP DCP011515DBP-U DCP012415DBP DCP012415DBP-U
DCP010505DBP DCP010505DBP-U/700 DCP010512DBP DCP010512DBP-U/700 DCP010515DBP DCP010515DBP-U/700 DCP011512DBP DCP011512DBP-U/700 DCP011515DBP DCP011515DBP-U/700 DCP012415DBP DCP012415DBP-U/700
Rails Tape Reel Rails Tape Reel Rails Tape Reel Rails Tape Reel Rails Tape Reel Rails Tape Reel
SOP-14(4)
devices also available tray quatities. most current package ordering information, Package Option Addendum this data sheet, refer site www.ti.com. Models with available only Tape Reel quantities indicated (for example, /700 indicates devices reel). Ordering pieces "DCP010505BP-U/700" will single 700-piece Tape Reel. Single voltage versions have active pins; dual voltage versions have seven active pins. package gullwing surface-mount.
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
+25°C, nominal, 2.2µF, COUT 0.1µF, unless otherwise noted.
DCP01B SERIES PARAMETER Output Power Ripple Voltage Temperature Input Voltage range Isolation flash test Voltage Line Regulation Voltage Source (VS) Switching/Synchronization Oscillator frequency (fOSC) Sync input Sync input current Disable time Capacitance loading SYNCIN Reliability Demonstrated Thermal Shutdown temperature shutdown Shutdown current Temperature Range Operating
TEST CONDITIONS 100% full load capacitor 1µF, load Room cold Room
0.97 0.046 0.016
UNITS mVPP %/°C %/°C
kVrms kVrms change
test, UL1950(1)
Minimum constant typical Typical constant maximum
15(2)
Switcing frequency fOSC/2 VSYNC External 3-(U) versions +55°C
+150 +100
During UL1950 recognition tests only. Line regulation measured constant load current. Line regulation IOUT fixed)/VS. Variation typ, max.
ELECTRICAL CHARACTERISTICS DEVICE
+25°C, nominal, 2.2µF, COUT 0.1µF, unless otherwise noted.
INPUT VOLTAGE PRODUCT DCP010505B DCP010505DB DCP010512B DCP010512DB DCP010515B DCP010515DB DCP011512DB DCP011515DB DCP012405B DCP012415DB
OUTPUT VOLTAGE VNOM Typical LOAD(3)
LOAD REGULATION 100% LOAD(4)
LOAD CURRENT (mA) LOAD
EFFICIENCY
BARRIER CAPACITANCE (pF) CISO VISO 750VRMS
100% LOAD
13.5 13.5 21.6 21.6
16.5 16.5 26.4 26.4
4.75 ±4.25 11.4 ±11.4 14.25 ±14.25 ±11.4 ±14.25 4.75 ±14.25
5.25 ±5.75 12.6 ±12.6 15.75 ±15.75 ±12.6 ±15.75 5.25 ±15.75
100% load current 1W/VS typical. Load regulation (VOUT load VOUT 100% load)/VOUT load.
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
ASSIGNMENTS (Single Voltage Version)
PACKAGES (TOP VIEW)
ASSIGNMENTS (Dual Voltage Version)
PACKAGES (TOP VIEW)
SYNCIN
SYNCIN
DCP01B +VOUT SYNCOUT +VOUT -VOUT
DCP01DB
SYNCOUT
Terminal Functions (Single Voltage)
TERMINAL NAME +VOUT SYNCOUT SYNCIN DESCRIPTION Voltage input Input side common Output side common +Voltage connected Unrectified transformer output Synchronization
Terminal Functions (Dual Voltage)
TERMINAL NAME +VOUT -VOUT SYNCOUT SYNCIN DESCRIPTION Voltage input Input side common Output side common +Voltage -Voltage Unrectified transformer output Synchronization
NOTE: input output.
NOTE: input output.
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
25°C, unless otherwise noted.
DCP010505B OUTPUT RIPPLE LOAD (20MHz Ripple (mVPP) VOUT Load Ceramic 4.7µF Ceramic 10µF Ceramic
DCP010505B VOUT
DCP010505B VOUT LOAD VOUT Load Efficiency
DCP010505B EFFICIENCY LOAD
Load
DCP010505DB VOUT LOAD VOUT Load Efficiency +VOUT -VOUT
DCP010505DB EFFICIENCY LOAD
Load
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
25°C, unless otherwise noted.
DCP010512B VOUT LOAD 14.5 14.0 13.5 Efficiency VOUT 13.0 12.5 12.0 11.5 11.0 Load
DCP010512B EFFICIENCY LOAD
Load
DCP010512DB VOUT LOAD 14.5 14.0 13.5 Efficiency 13.0 VOUT 12.5 12.0 11.5 11.0 10.5 10.0 Load +VOUT -VOUT
DCP010512DB EFFICIENCY LOAD
Load
DCP010515B VOUT LOAD 18.0 17.5 17.0 VOUT 16.5 16.0 15.5 15.0 14.5 14.0 Load Efficiency
DCP010515B EFFICIENCY LOAD
Load
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
25°C, unless otherwise noted.
DCP010515DB VOUT LOAD Efficiency VOUT +VOUT -VOUT Load
DCP010515DB EFFICIENCY LOAD
Load
DCP012405B VOUT LOAD 5.60 5.50 5.40 VOUT 5.30 5.20 5.10 5.00 4.90 4.80 Load Efficiency
DCP012405B EFFICIENCY LOAD
Load
DCP010505B CONDUCTED EMISSIONS (125% Load) Emission Level, Peak (dBµA) Emission Level, Peak (dBµA) 0.15 0.15
DCP010505B CONDUCTED EMISSIONS Load)
Frequency (MHz)
Frequency (MHz)
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
25°C, unless otherwise noted.
DCP011512DBP EFFICIENCY LOAD +VOUT -VOUT Efficiency 10.50 Load Load
DCP011512DBP VOUT LOAD 13.50 13.00 12.50 VOUT 12.00 11.50 11.00
DCP011515DBP EFFICIENCY LOAD Load 17.00 16.50 16.00 Efficiency Efficiency 15.50 15.00 14.50 14.00 13.50 13.00
DCP011515DBP VOUT LOAD +VOUT -VOUT
Load
DCP012415DBP EFFICIENCY LOAD Efficiency Load VOUT 16.50 16.00 15.50 15.00 14.50 14.00 13.50
DCP012415DBP VOUT LOAD +VOUT -VOUT
Load
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
FUNCTIONAL DESCRIPTION
OVERVIEW
DCP01B offers unregulated output power with typical efficiency 85%. This achieved through highly integrated packaging technology implementation custom power stage control circuit design uses advanced BiCMOS/DMOS process. additional information, refer application notes located DCP01B product folder www.ti.com.
synchronized devices used, should noted that startup, devices will draw maximum current simultaneously. This cause input voltage dip. dips below minimum input voltage (4.5V), devices start 2.2µF capacitor should connected close input pins. more than eight devices synchronized, recommended that SYNCIN pins driven external device. Details contained Application Report SBAA035, External Synchronization DCP01/02 Series DC/DC Converters, available download www.ti.com.
POWER STAGE
This uses push-pull, center-tapped topology switching 400kHz (divide-by-2 from 800kHz oscillator).
CONSTRUCTION
DCP01B basic construction same standard ICs. There substrate within molded package. DCP01B constructed using rectifier diodes, wound magnetic toroid leadframe. Since there solder within package, DCP01B does require special assembly processing. This results isolated DC/DC converter with inherently high reliability.
OSCILLATOR WATCHDOG
onboard 800kHz oscillator generates switching frequency divide-by-2 circuit. oscillator synchronized other DCP01B circuits external source, used minimize system noise. watchdog circuit checks operation oscillator circuit. oscillator stopped pulling SYNC low. output pins will tri-stated. This will occur 2µs.
ADDITIONAL FUNCTIONS
DISABLE/ENABLE
DCP01B disabled enabled driving SYNC using open drain CMOS gate. SYNCIN pulled low, DCP01B will disabled. disable time depends upon external loading; internal disable function implemented 2µs. Removal pull-down will cause DCP01B enabled. Capacitive loading SYNCIN should minimized order prevent reduction oscillator frequency.
THERMAL SHUTDOWN
DCP01B protected thermal shutdown circuit. on-chip temperature exceeds 150°C, device will shut down. Once temperature falls below 150°C, normal operation will resume. thermal condition continues, operation will randomly cycle off. This will continue until temperature reduced.
SYNCHRONIZATION
event that more than DC/DC converter needed onboard, beat frequencies other electrical interference generated. This small variations switching frequencies between DC/DC converters. DCP01B overcomes this allowing devices synchronized another. eight devices synchronized connecting SYNCIN pins together, taking care minimize stray capacitance. Stray capacitance 3pF) will have effect reducing switching frequency, even stopping oscillator circuit.
DECOUPLING
Ripple Reduction
high switching frequency 400kHz allows simple filtering. reduce ripple, recommended that least capacitor used VOUT. Dual outputs should have both positive negative buses decoupled VOUT ground (pin required 2.2µF equivalent series resistance (ESR) ceramic capacitor input versions, 0.47µF low-ESR ceramic capacitor versions help reduce ripple noise. Application Bulletin SBVA012, DC-to-DC Converter Noise Reduction, available download www.ti.com.
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
Connecting DCP01B Series
Multiple DCP01B isolated DC/DC converters connected series provide nonstandard voltage rails. This possible using floating outputs provided DCP01B galvanic isolation. Connect positive VOUT from DCP01B negative VOUT (0V) another, shown Figure SYNC pins tied together, self-synchronization feature DCP01B will prevent beat frequencies voltage rails. SYNCIN feature DCP01B allows easy connection series, which reduces separate filtering components.
outputs dual output DCP01B versions also connected series provide times magnitude VOUT, shown Figure example, dual DCP01B could connected provide rail.
Connecting DCP01B Parallel
output power from DCP01B sufficient, possible parallel outputs multiple DCP01B converters (see Figure Again, SYNCIN feature allows easy synchronization prevent power-rail beat frequencies additional filtering cost.
VSUPPLY CIN(1)
SYNCIN
VOUT VOUT1 VOUT2
CIN(1) SYNCIN
VOUT COUT
NOTE: requires low-ESR ceramic capacitor: version 2.2µF; version minimum 0.47µF. COUT 1.0µF.
Figure Connecting DCP01B Series
VSUPPLY CIN(1)
+VOUT -VOUT
COUT(1) COUT(1)
+VOUT -VOUT
NOTE: requires low-ESR ceramic capacitor: version 2.2µF; version minimum 0.47µF. COUT 1.0µF.
Figure Connecting Dual Outputs Series
VSUPPLY CIN(1)
SYNCIN
VOUT COUT(1) Power
CIN(1) SYNCIN
VOUT COUT(1)
NOTE: requires low-ESR ceramic capacitor: version 2.2µF; version minimum 0.47µF. COUT 1.0µF.
Figure Connecting Multiple DCP01Bs Parallel
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
APPLICATION INFORMATION
DCP01B, DCV01, DCP02 three families miniature DC/DC converters providing isolated unregulated voltage output. fabricated using CMOS/DMOS process with DCP01B replacing familiar DCP01 family that fabricated from bipolar process. DCP02 essentially extension DCP01B family providing higher power output with significantly improved load regulation, DCV01 tested higher isolation voltage.
cycle that devices discharge together. subsequent charge cycle only restarted when last device finished discharge cycle.
OPTIMIZING PERFORMANCE
Optimum performance only achieved device correctly supported. very nature switching converter, requires power instantly available when switches converter DMOS switching transistors, fast edges will create high current demand input supply. This transient load placed input supplied external input decoupling capacitor, thus maintaining input voltage. Therefore, input supply does this transient (this analogy high-speed digital circuits). positioning capacitor critical must placed close possible input pins connected low-impedance path. optimum performance primarily dependent factors:
TRANSFORMER DRIVE CIRCUIT
Transformer drive transistors have characteristically value transistor resistance (RDS); thus, more power transferred transformer. transformer drive circuit limited base current available switch power transistors driving transformer their characteristic current gain (beta), resulting slower turn-on time. Consequently, more power dissipated within transistor. This results lower overall efficiency, particularly higher output load currents.
Connection input output circuits minimal loss. ability decoupling capacitors maintain input output voltages constant level. Design
copper losses (resistance inductance) minimized mutual ground power planes (tracks) where possible. that possible, wide tracks reduce losses. several devices being powered from common power source, star-connected system track must deployed; devices must connected series, this will cascade resistive losses. position decoupling capacitors important. They must close devices possible order reduce losses. Layout section more details.
SELF-SYNCHRONIZATION
input synchronizations facility (SYNCIN), allows easy synchronizing multiple devices. eight devices (maximum) have their respective SYNCIN pins connected together, then devices will synchronized. Each device onboard oscillator. This generated charging capacitor from constant current producing ramp. When this ramp passes threshold, internal switch activated that discharges capacitor second threshold before cycle repeated. When several devices connected together, internal capacitors charged simultaneously. When device passes threshold during charge cycle, starts discharge cycle. other devices sense this falling voltage and, likewise, initiate discharge
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
Decoupling Ceramic Capacitors
capacitors have losses their internal equivalent series resistance (ESR), lesser degree their equivalent series inductance (ESL). Values always easy obtain. However, some manufacturers provide graphs Frequency versus Capacitor Impedance. These will show capacitors' impedance falling frequency increased (see Figure frequency increased, impedance will stop decreasing begin rise. point minimum impedance indicates capacitors' resonant frequency. This frequency where components capacitance inductance reactance equal magnitude. Beyond this point, capacitor effective capacitor.
Input Capacitor effects
input decoupling capacitor ceramic with ESR, then instant power transistors switch voltage input pins will fall momentarily. Should voltage fall below approximately will detect under-voltage condition switch drive circuits state. This carried precaution against genuine input voltage condition that could slow down even stop internal circuits from operating correctly. This would result drive transistors being turned long, causing saturation transformer destruction device. Following detection input voltage condition, device switches internal drive circuits until input voltage returns safe value. Then device tries restart. input capacitor still unable maintain input voltage, shutdown recurs. This process repeated until capacitor charged sufficiently start device correctly. Otherwise, device will caught loop. Normal startup should occur approximately from power being applied device. considerably longer startup duration time encountered, likely that either both) input supply capacitors performing adequately. input devices, 2.2µF low-ESR ceramic capacitor will ensure good startup performance, remaining input voltage ranges, 0.47µF ceramic capacitors good. Tantalum capacitors recommended, since most have low-ESR values will degrade performance. tantalum capacitors must used, close attention must paid both voltage derated vendor.
Frequency
Where: reactance capacitance, reactance resonant frequency XL)2 (ESR)2
Figure Capacitor Impedance Frequency
however, there 180° phase difference resulting cancellation imaginary component. resulting effect that impedance resonant point real part complex impedance; namely, value ESR. resonant frequency must well above 800kHz switching frequency DCVs. effect cause voltage drop within capacitor. value this voltage drop simply product transient load current, shown Equation (1):
Output Ripple Calculation Example
DCP020505: Output voltage Output current 0.4A. full output power, load resistor 12.5. Output capacitor 1µF, 0.1. Capacitor discharge time 800kHz (ripple frequency): tDIS 0.0125µs RLOAD 10-6 12.5 12.5µs VDIS VO(1 EXP(-tDIS/)) VDIS contrast voltage dropped ESR: VESR ILOAD VESR 40mV Ripple voltage 45mV Clearly, increasing capacitance will have much smaller effect output ripple voltage than reducing value filter capacitor.
(ESR
Where:
voltage device input. maximum value voltage capacitor during charge. transient load current. other factor that affects performance value capacitance. However, input full wave outputs (single-output voltage devices), dominant factor.
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
DUAL OUTPUT VOLTAGE DCVs
voltage output dual DCPs half wave rectified; therefore, discharge time 1.25µs. Repeating above calculations using 100% load resistance (0.2A output), results shown below: 25µs TDIS 1.25µs. VDIS 244mV VESR 20mV Ripple Voltage 266mV This time, capacitor discharging that contributing largest component ripple. Changing output filter 10µF, repeating calculations: Ripple Voltage 45mV. This value composed almost equal components. above calculations given only guide. Capacitor parameters usually have large tolerances susceptible environmental conditions.
Sync pin, when being used, best left floating pad. ground ring annulus connected around will prevent noise being conducted onto pin. Sync being connected more Sync pins, then linking trace should narrow must kept short length. addition, other trace should close proximity this trace because that will increase stray capacitance this pin, that will effect performance oscillator.
Ripple Noise
Careful consideration should given layout PCB, order that best results obtained. DCP01B switching power supply such place high peak current demands input supply. order avoid supply falling momentarily during fast switching pulses, ground power planes should used connect power input DCP01B. this possible, then supplies must connected star formation with traces made wide possible. SYNCIN being used, then trace connection between device SYNCIN pins should short avoid stray capacitance. SYNCIN being used, advisable place guard ring (connected input ground) around this avoid noise pick output should taken from device using ground power planes; this ensures minimum losses. good quality low-ESR ceramic capacitor placed close practical across input will reduce reflected ripple ensure smooth startup. good quality low-ESR capacitor (ceramic preferred) placed close practical across rectifier output terminal output ground gives best ripple noise performance. SBVA012 more information noise rejection.
LAYOUT
Figure Figure illustrate printed circuit board (PCB) layout conventional (DCP01/02, DCV01), SO-28 surface-mount packages (DCP02U). Figure shows schematic. Input power ground planes have been used, providing low-impedance path input power. output, common been connected ground plane, while connections positive negative voltage outputs conducted wide traces order minimize losses. location decoupling capacitors close proximity their respective pins ensures losses effects stray inductance; thus, improving ripple performance. This particular importance input decoupling capacitor this supplies transient current associated with fast switching waveforms power drive circuits.
THERMAL MANAGEMENT
high power density this device, advisable provide ground planes input output.
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
Figure Example Layout, Component-Side View
Figure Example Layout, Non-component-Side View
DCP01B SERIES
www.ti.com SBVS012B DECEMBER 2000 REVISED OCTOBER 2004
CON1 COM1 C4-1 C2-1 DCP02xP COM3 SYNC
CON3 SYNC DCP02xU
CON2 COM2 C7-1 SYNC DCP02xP COM4
CON4 SYNC DCP02xU
Capacitors C2-1, C4-1, C7-1, C9-1 through-hole plated components connected parallel with (1206 SMD), respectively. optimum low-noise performance, low-ESR capacitors. connect SYNC jumper (JP1-JP4) SYNC function being used. Connections power input should made with minimum wire 16/0.2 twisted pair, with length kept short. input supply ground respecively represents channel). positive negative outputs, referenced common ground COMx. links used self-synchronization; this facility being used, links should unconnected. R1-R8 power output loads; these external load connected. CON1 CON2 DIL-14; CON3 CON4 SO-28 packages. (10) connected.
Figure Example Layout, Schematic Diagram
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2004
PACKAGING INFORMATION
ORDERABLE DEVICE DCP010505BP DCP010505BP-U DCP010505BP-U/700 DCP010505DBP DCP010505DBP-U DCP010505DBP-U/700 DCP010512BP DCP010512BP-U DCP010512BP-U/700 DCP010512DBP DCP010512DBP-U DCP010512DBP-U/700 DCP010515BP DCP010515BP-U DCP010515BP-U/700 DCP010515DBP DCP010515DBP-U DCP010515DBP-U/700 DCP011512DBP DCP011512DBP-U DCP011512DBP-U/700 DCP011515DBP DCP011515DBP-U DCP011515DBP-U/700 DCP012415DBP DCP012415DBP-U DCP012415DBP-U/700 STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PDIP PACKAGE DRAWING PINS PACKAGE
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
MECHANICAL DATA
MPDI058 APRIL 2001
(R-PDIP-T7/14)
0.775 (19,69) 0.735 (18,67)
PLASTIC DUAL-IN-LINE
0.280 (7,11) 0.240 (6,10) Index Area
Base Plane 0.070 (1,78) 0.045 (1,14) 0.195 (4,95) 0.115 (2,92) 0.325 (8,26) 0.300 (7,62)
0.015 (0,38)
0.210 (5,33)
0.005 (0,13) Full Lead
0.100 (2,54) Seating Plane 0.022 (0,56) 0.014 (0,36) 0.010 (0,25)
0.150 (3,81) 0.115 (2,92)
0.300 (7,63)
0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.000 (0,00)
0.430 (10,92)
4202489/A 03/01
NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Dimensions measured with package seated JEDEC seating plane gauge GS-3. Dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 (0,25). Dimensions measured with leads constrained perpendicular Datum Dimensions measured lead tips with leads unconstrained. Pointed rounded lead tips preferred ease insertion. Lead shoulder maximum dimension does include dambar protrusions. Dambar protrusions shall exceed 0.010 (0,25).
Distance between leads including dambar protrusions 0.005 (0,13) minumum. visual index feature must located within cross-hatched area. automatic insertion, raised irregularity surface (step, mesa, etc.) shall symmetrical about lateral longitudinal package centerlines. Falls within JEDEC MS-001-AA.
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS097 APRIL 2001
(R-PDSO-G7/14)
PLASTIC SMALL-OUTLINE
0.775 (19,69) 0.735 (18,67)
0.280 (7,11) 0.240 (6,10)
Index Area
0.022 (0,56) 0.014 (0,36)
0.420 (10,70) 0.405 (10,30) 0.070 (1,78) 0.045 (1,14) 0.210 (5,33) 0.325 (8,26) 0.300 (7,62)
Base Plane Seating Plane 0.100 (2,54) 0.005 (0,13) Full Lead 0.015 (0,38) 0.043 (1,10) 0.025 (0,65) 0.057 (1,45) 0.045 (1,15)
0.014 (0,36) 0.008 (0,20)
4202490/A 03/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 (0,25). Lead shoulder maximum dimension does include dambar protrusions. Dambar protrusions shall exceed 0.010 (0,25). Distance between leads including dambar protrusions 0.005 (0,13) minimum. visual index feature must located within cross-hatched area. automatic insertion, raised irregularity surface (step, mesa, etc.) shall symmetrical about lateral longitudinal package centerlines.
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SBVS012B DECEMBER 2000 REVISED OCTOBER 2004 Miniature, Isolated U

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