DESCRIPTIO 3Msps Sampling with Simultaneous Differential Inputs 1

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DESCRIPTIO 3Msps Sampling with Simultaneous Differential Inputs 1

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LTC1407-1/LTC1407A-1 Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown
DESCRIPTIO
3Msps Sampling with Simultaneous Differential Inputs 1.5Msps Throughput Channel Power Dissipation: 14mW (Typ) Single Supply Operation ±1.25V Differential Input Range Compatible 2.5V Input Range Version (LTC1407/LTC1407A) 2.5V Internal Bandgap Reference with External Overdrive 3-Wire Serial Interface Sleep (10µW) Shutdown Mode (3mW) Shutdown Mode 80dB Common Mode Rejection 100kHz Tiny 10-Lead Package
LTC1407-1/LTC1407A-1 12-bit/14-bit, 3Msps ADCs with 1.5Msps simultaneously sampled differential inputs. devices draw only 4.7mA from single supply come tiny 10-lead package. Sleep shutdown feature lowers power consumption 10µW. combination speed, power tiny package makes LTC1407-1/LTC1407A-1 suitable high speed, portable applications. LTC1407-1/LTC1407A-1 contain separate differential inputs that sampled simultaneously rising edge CONV signal. These sampled inputs then converted rate 1.5Msps channel. 80dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. devices convert -1.25V 1.25V bipolar inputs differentially. absolute voltage swing CH0+, CH0-, CH1+ CH1- extends from ground supply voltage. serial interface sends conversion results clocks compatibility with standard serial interfaces.
Lare registered trademarks Linear Technology Corporation. other trademarks property their respective owners. Protected U.S. Patents, including 6084440, 6522187.
APPLICATIO
Telecommunications Data Acquisition Systems Uninterrupted Power Supplies Multiphase Motor Control Demodulation Industrial Radio
BLOCK DIAGRA
CH0+
10µF
LTC1407A-1
14-BIT LATCH
CH0-
3Msps 14-BIT
THD, 2nd, (dB)
CH1+
14-BIT LATCH
THREESTATE SERIAL OUTPUT PORT
CH1-
VREF 2.5V REFERENCE
TIMING LOGIC
CONV
10µF
EXPOSED
1407A1
THD, Input Frequency Differential Input Signals
-104 FREQUENCY (MHz)
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LTC1407-1/LTC1407A-1
ABSOLUTE
(Notes
RATI
PACKAGE/ORDER ATIO
VIEW VREF CH1+ CH1- CONV
Supply Voltage (VDD) Analog Input Voltage (Note 0.3V (VDD 0.3V) Digital Input Voltage 0.3V (VDD 0.3V) Digital Output Voltage 0.3V (VDD 0.3V) Power Dissipation 100mW Operation Temperature Range LTC1407C-1/LTC1407AC-1 70°C LTC1407I-1/LTC1407AI-1 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
PACKAGE 10-LEAD PLASTIC MSOP TJMAX 125°C, 150°C/ EXPOSED (PIN MUST SOLDERED
ORDER PART NUMBER LTC1407CMSE-1 LTC1407IMSE-1 LTC1407ACMSE-1 LTC1407AIMSE-1
PART MARKING LTBGT LTBGV LTBGW LTBGX
Order Options Tape Reel: Lead Free: #PBF Lead Free Tape Reel: #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult Marketing parts specified with wider operating temperature ranges.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Offset Error Offset Match from Gain Error Gain Match from Gain Tempco
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference,
CONDITIONS
LTC1407-1
LTC1407A-1 ±0.5
UNITS Bits ppm/°C ppm/°C
(Notes (Notes (Note (Notes (Note Internal Reference (Note External Reference
±0.25 ±0.5
ALOG
SYMBOL PARAMETER tACQ tJITTER CMRR
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference,
CONDITIONS 2.7V 3.3V -1.25 1.25
UNITS
Analog Differential Input Range (Notes Analog Common Mode Differential Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Sample-and-Hold Aperture Skew from Analog Input Common Mode Rejection Ratio
(Note (Note
1MHz, 100MHz,
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LTC1407-1/LTC1407A-1
ACCURACY
SYMBOL SINAD PARAMETER Signal-to-Noise Plus Distortion Ratio
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference, Single ended signal drive CH0+/CH1+ with CHO-/CH1- 1.5V Differential signals drive both inputs each channel with 1.5V
CONDITIONS 100kHz Input Signal (Note 750kHz Input Signal (Note 100kHz Input Signal, External VREF 3.3V, 3.3V (Note 750kHz Input Signal, External VREF 3.3V, 3.3V (Note 100kHz First Harmonics (Note 750kHz First Harmonics (Note 100kHz Input Signal (Note 750kHz Input Signal (Note 0.625VP-P 1.4MHz Summed with 0.625VP-P, 1.56MHz into CH0+ Inverted into CHO-. Also Applicable CH1+ CH1- VREF 2.5V (Note 2.5VP-P, 11585LSBP-P (-3dBFS) (Note S/(N 68dB
SFDR
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance VREF Settling Time CONDITIONS IOUT
DIGITAL PUTS DIGITAL OUTPUTS
SYMBOL ISOURCE ISINK PARAMETER High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT Output Short-Circuit Source Current Output Short-Circuit Sink Current VOUT VOUT CONDITIONS 3.3V 2.7V
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
LTC1407-1 70.5 70.5 72.0 72.0
LTC1407A-1 73.5 73.5 76.3 76.3
UNITS
Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Code-to-Code Transition Noise Full Power Bandwidth Full Linear Bandwidth
0.25
LSBRMS
25°C.
UNITS ppm/°C µV/V
2.7V 3.6V, VREF 2.5V Load Current 0.5mA
UNITS
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IOUT 200µA 2.7V, IOUT 160µA 2.7V, IOUT 1.6mA VOUT
0.05 0.10
LTC1407-1/LTC1407A-1
POWER REQUIRE
SYMBOL PARAMETER Supply Voltage Supply Current
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. With internal reference,
CONDITIONS Active Mode, fSAMPLE 1.5Msps Mode Sleep Mode (LTC1407) Sleep Mode (LTC1407A) Active Mode with Fixed State
Power Dissipation
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C.
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tSCK tCONV PARAMETER Maximum Sampling Frequency Channel (Conversion Rate) Minimum Sampling Period (Conversion Acquisiton Period) Clock Period Conversion Time Minimum Positive Negative SCLK Pulse Width CONV Setup Time Before CONV Minimum Positive Negative CONV Pulse Width Sample Mode CONV Hold Mode 32nd CONV Interval (Affects Acquisition Period) Minimum Delay from Valid Bits Through Hi-Z Previous Remains Valid After VREF Settling Time After Sleep-to-Wake Transition CONDITIONS
CHARACTERISTICS
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note voltage values with respect ground GND. Note When these pins taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below greater than without latchup. Note Offset range specifications apply single-ended CH0+ CH1+ input with CH1- grounded using internal 2.5V reference. Note Integral linearity tested with external 2.55V reference defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Guaranteed design, subject test. Note Recommended operating conditions. Note analog input range defined voltage difference between CH0+ CH1+ CH1-. Performance specified with CHO- 1.5V while driving CHO+ with CH1- 1.5V while driving CH1+. Note absolute voltage CH0+, CH1+ CH1- must within this range.
UNITS
UNITS SCLK cycles
(Note (Note (Note (Notes (Note (Note (Note (Notes (Notes (Notes (Notes (Notes (Notes
19.6
10000 10000
Note less than allowed, output data will appear clock cycle later. best CONV rise half clock before SCK, when running clock rated speed. Note same aperture delay. Aperture delay (1ns) difference between 2.2ns delay through sample-and-hold 1.2ns CONV Hold mode delay. Note rising edge guaranteed catch data coming into storage latch. Note time period acquiring input signal started 32nd rising clock ended rising edge CONV. Note internal reference settles after wakes from Sleep mode with more cycles 10µF capacitive load. Note full power bandwidth frequency where output code swing drops with 2.5VP-P input sine wave. Note Maximum clock period guarantees analog performance during conversion. Output data read with arbitrarily long clock period. Note LTC1407A-1 measured specified with 14-bit Resolution (1LSB 152µV) LTC1407-1 measured specified with 12-bit Resolution (1LSB 610µV). Note sampling capacitor each input accounts 4.1pF input capacitance. Note Full-scale sinewaves into noninverting inputs while inverting inputs kept 1.5V
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LTC1407-1/LTC1407A-1 TYPICAL PERFOR CHARACTERISTICS
ENOBs SINAD Input Sinewave Frequency
12.0 11.5 11.0
ENOBs (BITS)
25°C. Single ended signals drive +CH0/+CH1 with -CH0/-CH1 1.5V differential signals drive both inputs with 1.5V (LTC1407A-1) THD, Input Frequency
FREQUENCY (MHz)
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10.0
-104
SFDR (dB)
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10.5
THD, 2nd, (dB)
Input Frequency
12.0 11.5 11.0
ENOBs (BITS)
(dB)
FREQUENCY (MHz)
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10.5 10.0 FREQUENCY (MHz)
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THD, 2nd, (dB)
SFDR Input Frequency Differential Input Signals
MAGNITUDE (dB)
MAGNITUDE (dB)
SFDR (dB)
FREQUENCY (MHz)
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SFDR Input Frequency
SINAD (dB)
FREQUENCY (MHz)
FREQUENCY (MHz)
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ENOBs SINAD Input Sinewave Frequency Differential Input Signals
THD, Input Frequency Differential Input Signals
-104 FREQUENCY (MHz)
SINAD (dB)
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98kHz Sine Wave 4096 Point Plot
-100 -110 -120 FREQUENCY (kHz)
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748kHz Sine Wave 4096 Point Plot
-100 -110 -120 FREQUENCY (kHz)
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LTC1407-1/LTC1407A-1 TYPICAL PERFOR CHARACTERISTICS
1403kHz Input Summed with 1563kHz Input 4096 Point Plot Differential Input Signals
25°C. Single ended signals drive +CH0/+CH1 with -CH0/-CH1 1.5V differential signals drive both inputs with 1.5V (LTC1407A-1) 748kHz Sine Wave 4096 Point Plot Differential Input Signals
MAGNITUDE (dB) MAGNITUDE (dB)
MAGNITUDE (dB)
-100 -110 -120 FREQUENCY (kHz)
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Differential Linearity with Internal 2.5V Reference
DIFFERENTIAL LINEARITY (LSB)
INTEGRAL LINEARITY (LSB)
INTEGRAL LINEARITY (LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 4096 12288 8192 OUTPUT CODE 16384
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Differential Linearity with Internal 2.5V Reference
DIFFERENTIAL LINEARITY (LSB)
INTEGRAL LINEARITY (LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 4096 12288 8192 OUTPUT CODE 16384
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-0.8 -1.6 -2.4 -3.2 -4.0 4096 12288 8192 OUTPUT CODE 16384
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INTEGRAL LINEARITY (LSB)
10.7MHz Sine Wave 4096 Point Plot Differential Input Signals
-100 -110 -120
-100 -110 -120 185k 371k 556k FREQUENCY (Hz) 741k
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185k
371k 556k FREQUENCY (Hz)
741k
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Integral Linearity Point with Internal 2.5V Reference
-0.8 -1.6 -2.4 -3.2 -4.0
4096 12288 8192 OUTPUT CODE 16384
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Integral Linearity Point with Internal 2.5V Reference Differential Input Signals
-0.8 -1.6 -2.4 -3.2 -4.0
4096
12288 8192 OUTPUT CODE
16384
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Integral Linearity Point with Internal 2.5V Reference
-0.8 -1.6 -2.4 -3.2 -4.0
Integral Linearity Point with Internal 2.5V Reference Differential Input Signals
4096
12288 8192 OUTPUT CODE
16384
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LTC1407-1/LTC1407A-1
TYPICAL PERFOR CHARACTERISTICS
Differential Integral Linearity Conversion Rate
2.25 2.75 3.25 3.75 CONVERSION RATE (MSPS)
25°C. Single ended signals drive +CH0/+CH1 with -CH0/-CH1 1.5V differential signals drive both inputs with 1.5V (LTC1407A-1)
LINEARITY (LSB)
S/(N+D) (dB)
25°C (LTC1407-1/LTC1407A-1) Full-Scale Signal Frequency Response
CMRR (dB)
100M FREQUENCY (Hz)
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CROSSTALK (dB)
AMPLITUDE (dB)
Output Match with Simultaneous Input Steps from
16384 14336 12288
OUTPUT CODE
PSRR (dB)
10240 8192 6144 4096 2048 FALLING TIME (ns)
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SINAD Conversion Rate
EXTERNAL VREF 3.3V, fS/3 EXTERNAL VREF 3.3V, fS/40 INTERNAL VREF 2.5V, fS/3 INTERNAL VREF 2.5V, fS/40
CONVERSION RATE (Msps)
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CMRR Frequency
-100 -120
Crosstalk Frequency
100k FREQUENCY (Hz)
100M
100k FREQUENCY (Hz)
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PSSR Frequency
RISING
FREQUENCY (Hz) 100k
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LTC1407-1/LTC1407A-1 TYPICAL PERFOR CHARACTERISTICS
Reference Voltage
2.4902 2.4900 2.4898 2.4902 2.4900 2.4898
VREF
2.4896 2.4894 2.4892
2.4890
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VREF
CTIO
CH0+ (Pin Noninverting Channel CH0+ operates fully differentially with respect CH0-, with -1.25V 1.25V differential swing with respect CH0- absolute input range. CH0- (Pin Inverting Channel CH0- operates fully differentially with respect CH0+, with 1.25V -1.25V differential swing with respect CH0+ absolute input range. VREF (Pin 2.5V Internal Reference. Bypass solid analog ground plane with 10µF ceramic capacitor 10µF tantalum parallel with 0.1µF ceramic). overdriven external reference voltage 2.55V VDD. CH1+ (Pin Noninverting Channel CH1+ operates fully differentially with respect CH1-, with -1.25V 1.25V differential swing with respect CH1- absolute input range. CH1- (Pin Inverting Channel CH1- operates fully differentially with respect CH1+, with 1.25V -1.25V differential swing with respect CH1+ absolute input range. (Pins 11): Ground Exposed Pad. This single ground Exposed must tied directly solid ground plane under part. Keep mind that analog signal currents digital output signal currents flow through these connections. (Pin Positive Supply. This single power supplies entire chip. Bypass solid analog ground plane with 10µF ceramic capacitor 10µF tantalum) parallel with 0.1µF ceramic. Keep mind that internal analog currents digital output signal currents flow through this pin. Care should taken place 0.1µF bypass capacitor close Pins possible. (Pin Three-state Serial Data Output. Each pair output data words represent analog input channels start previous conversion. output format complement. (Pin External Clock Input. Advances conversion process sequences output data rising edge. more pulses wake from sleep. CONV (Pin 10): Convert Start. Holds analog input signals starts conversion rising edge. pulses with fixed high fixed state starts mode. Four more pulses with fixed high fixed state starts Sleep mode.
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25°C (LTC1407-1/LTC1407A-1) Reference Voltage Load Current
2.4896 2.4894 2.4892
2.4890 LOAD CURRENT (mA)
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LTC1407-1/LTC1407A-1
BLOCK DIAGRA
CH0-
3Msps 14-BIT
14-BIT LATCH
CH0+
CH1+
CH1-
VREF 2.5V REFERENCE
14-BIT LATCH
10µF
10µF LTC1407A-1
THREESTATE SERIAL OUTPUT PORT
TIMING LOGIC
CONV
EXPOSED
1407A1
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LTC1407 Timing Diagram
DIAGRA
CONV tACQ HOLD HOLD REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION 12-BIT DATA WORD tCONV tTHROUGHPUT Hi-Z Hi-Z
1407A1 TD01
INTERNAL STATUS
SAMPLE
SAMPLE
HOLD
LTC1407-1/LTC1407A-1
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION 12-BIT DATA WORD
Hi-Z
*BITS MARKED AFTER SHOULD IGNORED
LTC1407A Timing Diagram
CONV tACQ HOLD Hi-Z REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION 14-BIT DATA WORD tCONV tTHROUGHPUT Hi-Z
1407A1 TD01
HOLD
INTERNAL STATUS
SAMPLE
SAMPLE
HOLD
REPRESENTS ANALOG INPUT FROM PREVIOUS CONVERSION 14-BIT DATA WORD
Hi-Z
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LTC1407-1/LTC1407A-1
DIAGRA
Mode Waveforms
CONV
CONV
SLEEP
VREF
NOTE: SLEEP INTERNAL SIGNALS
Sleep Mode Waveforms
1407 TD02
Delay
14071 TD03
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
DRIVING ANALOG INPUT
differential analog inputs LTC1407-1/ LTC1407A-1 easy drive. inputs driven differentially single-ended input (i.e., CH0- input grounded VCC/2). four analog inputs both differential analog input pairs, CH0+ with CH0- CH1+ with CH1-, sampled same instant. unwanted signal that common both inputs each input pair will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit low, then LTC1407-1/LTC1407A-1 inputs driven directly. source impedance increases, will acquisition time. minimum acquisition time with high source impedance, buffer amplifier must used. main requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 39ns full throughput rate). Also keep mind, while choosing input amplifier, amount noise harmonic distortion added amplifier. CHOOSING INPUT AMPLIFIER Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance 100) closed-loop bandwidth frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz must less than 100. second requirement that closed-loop bandwidth must greater than 40MHz ensure adequate smallsignal settling full throughput rate. slower amps used, more time settling provided
increasing time between conversions. best choice drive LTC1407-1/LTC1407A-1 depends application. Generally, applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1407-1/LTC1407A-1. (More detailed information available Linear Technology Databooks LinearViewCD-ROM.) LTC1566-1: Noise 2.3MHz Continuous Time Lowpass Filter. LT®1630: Dual 30MHz Rail-to-Rail Voltage Amplifier. 2.7V ±15V supplies. Very high AVOL, 500µV offset 520ns settling 0.5LSB swing. noise 93dB 40kHz below 1LSB 320kHz 2VP-P into 5V), making part excellent applications Nyquist) where rail-to-rail performance desired. Quad version available LT1631. LT1632: Dual 45MHz Rail-to-Rail Voltage Amplifier. 2.7V ±15V supplies. Very high AVOL, 1.5mV offset 400ns settling 0.5LSB swing. suitable applications with single supply. noise 93dB 40kHz below 1LSB 800kHz 2VP-P into 5V), making part excellent applications where rail-to-rail performance desired. Quad version available LT1633. LT1801: 80MHz GBWP, -75dBc 500kHz, 2mA/amplifier, 8.5nV/Hz. LT1806/LT1807: 325MHz GBWP, -80dBc distortion 5MHz, unity gain stable, rail-to-rail out, 10mA/amplifier, 3.5nV/Hz. LT1810: 180MHz GBWP, -90dBc distortion 5MHz, unity gain stable, rail-to-rail out, 15mA/amplifier, 16nV/Hz.
LinearView trademark Linear Technology Corporation.
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual Voltage Mode Operational Amplifier. LT6200: 165MHz GBWP, -85dBc distortion 1MHz, unity gain stable, rail-to-rail out, 15mA/amplifier, 0.95nV/Hz. LT6203: 100MHz GBWP, -80dBc distortion 1MHz, unity gain stable, rail-to-rail out, 3mA/amplifier, 1.9nV/Hz. LT6600: Amplifier/Filter Differential In/Out with 10MHz Cutoff. INPUT FILTERING SOURCE IMPEDANCE noise distortion input amplifier other circuitry must considered since they will LTC1407-1/LTC1407A-1 noise distortion. small-signal bandwidth sample-and-hold circuit 50MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 47pF capacitor from CHO+ ground source resistor limit input bandwidth 30MHz. 47pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling-glitch sensitive circuitry. High quality capacitors resistors should used since these components
ANALOG INPUT 1.5V 47pF* CH0- LTC1407-1/ LTC1407A-1 VREF CH1+ CH0+
10µF ANALOG INPUT 1.5V 47pF*
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*TIGHT TOLERANCE REQUIRED AVOID APERTURE SKEW DEGRADATION
FILM TYPE TYPE CERAMIC BYPASS
Figure Input Filter
Figure Coupling Signals with 1kHz
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CH1-
distortion. silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. When high amplitude unwanted signals close frequency desired signal frequency multiple pole filter required. High external source resistance, combined with 13pF input capacitance, will reduce rated 50MHz input bandwidth increase acquisition time beyond 39ns. INPUT RANGE analog inputs LTC1407-1/LTC1407A-1 driven fully differentially with single supply. Either input swing provided differential swing greater than 1.25V. valid input range, each input each channel always ±1.25V away from other input each channel. -1.25V 1.25V range also ideally suited AC-coupled signals single supply applications. Figure shows couple signals single supply system without needing mid-supply 1.5V external reference. common mode level supplied previous stage that already bounded single supply voltage system. common mode range inputs extends from ground supply voltage VDD. difference between CH0+ CH0- inputs CH1+ CH1- inputs exceeds 1.25V, output code will stay fixed zero ones, this difference goes below -1.25V, ouput code will stay fixed zeros.
LTC1407-1/ LTC1407A-1 CHO+ CHO- 4.09V VREF 10µF 14071 56pF 1.6k 1.6k
LTC1407-1/LTC1407A-1
APPLICATIO ATIO
INTERNAL REFERENCE
LTC1407-1/LTC1407A-1 have on-chip, temperature compensated, bandgap reference that factory trimmed near 2.5V obtain precise ±1.25V input span. reference amplifier output VREF, (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended. VREF overdriven with external reference shown Figure voltage external reference must higher than 2.5V open-drain P-channel output internal reference. recommended range external reference 2.55V VDD. external reference 2.55V will quiescent load 0.75mA much during conversion.
10µF
CMRR (dB)
VREF LTC1407-1/ LTC1407A-1
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Figure
INPUT SPAN VERSUS REFERENCE VOLTAGE differential input range unipolar voltage span that equals difference between voltage reference buffer output VREF (Pin voltage Exposed ground. differential input range -1.25V 1.25V when using internal reference. internal referenced these nodes. This relationship also holds true with external reference. DIFFERENTIAL INPUTS will always convert bipolar difference CH0+ minus CH0- bipolar difference CH1+ minus CH1-, independent common mode voltage either inputs. common mode rejection holds high frequencies (see Figure only requirement that both inputs below ground exceed VDD. Integral nonlinearity errors (INL) differential
COMPLEMENT OUTPUT CODE
nonlinearity errors (DNL) largely independent common mode voltage. However, offset error will vary. CMRR typically better than 60dB. Figure shows ideal input/output characteristics LTC1407-1/LTC1407A-1. code transitions occur midway between successive integer values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, 1.5LSB). output code complement with 1LSB 2.5V/16384 153µV LTC1407A-1 1LSB 2.5V/4096 610µV LTC1407-1. LTC1407A-1 1LSB Gaussian white noise. Figure shows LTC1819 converting single ended input signal differential input signals optimum SFDR performance shown plot (Figure 6b).
-100 -120 100k FREQUENCY (Hz) 100M
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Figure CMRR Frequency
011.111 011.110 011.101
100.010 100.001 100.000 INPUT VOLTAGE
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1LSB
Figure LTC1407-1/LTC1407A-1 Transfer Characteristic
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
0.1µF
MAGNITUDE (dB)
LT1819
Figure LT1819 Driving LTC1407A-1 Differentially
Board Layout Bypassing Wire wrap boards recommended high resolution and/or high speed converters. obtain best performance from LTC1407-1/LTC1407A-1, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track. optimum phase match between inputs desired, length four input wires input channels should kept matched. each pair input wires input channels should kept separated ground trace avoid high frequency crosstalk between channels. High quality tantalum ceramic bypass capacitors should used VREF pins shown Block Diagram first page this data sheet. optimum performance, 10µF surface mount tantalum capacitor with 0.1µF ceramic recommended VREF pins. Alternatively, 10µF ceramic chip capacitors such used. capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. bypass capacitor returns (Pin VREF bypass capacitor returns Exposed ground (Pin 11). Care should
1.25VP-P
LT1819 0.1µF
47pF +CH0 +CH1
1.5VCM
47pF
-100 -110
LTC1407A-1
-120
185k
371k 556k FREQUENCY (Hz)
741k
14031 F06b
-CH0 -CH1
1407A F06a
Figure LTC1407-1 6MHz Sine Wave 4096 Point Plot with LT1819 Driving Inputs Differentially
1407-1
Figure Recommended Layout
taken place 0.1µF bypass capacitor close Pins possible. Figure shows recommended system ground connections. analog circuitry grounds should terminated
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
LTC1407-1/LTC1407A-1 Exposed Pad. ground return from LTC1407-1/LTC1407A-1 power supply should impedance noise-free operation. Exposed 10-lead package also tied LTC1407-1/LTC1407A-1 GND. Exposed should soldered board reduce ground connection inductance. Digital circuitry grounds must connected digital supply common. POWER-DOWN MODES Upon power-up, LTC1407-1/LTC1407A-1 initialized active state ready conversion. Sleep mode waveforms show power-down modes LTC1407-1/LTC1407A-1. CONV inputs control power-down modes (see Timing Diagrams). rising edges CONV, without intervening rising edges SCK, LTC1407-1/LTC1407A-1 mode power drain drops from 14mW 6mW. internal reference remains powered mode. more rising edges wake LTC1407-1/LTC1407A-1 service very quickly CONV start accurate conversion within clock cycle. Four rising edges CONV, without intervening rising edges SCK, LTC1407-1/LTC1407A-1 Sleep mode power drain drops from 14mW 10µW. bring part Sleep mode requires more rising edges followed request. Then more rising edges wake LTC1407-1/LTC1407A-1 operation. When mode entered after Sleep mode, reference that shut down Sleep mode reactivated. internal reference (VREF takes slew settle with 10µF load. Using sleep mode more frequently compromises settled accuracy internal reference. Note that slower conversion rates, Sleep modes used substantial reductions power consumption. DIGITAL INTERFACE LTC1407-1/LTC1407A-1 have 3-wire (Serial Protocol Interface) interface. CONV inputs output implement this interface. CONV inputs accept swings from logic
compatible, logic swing does exceed VDD. detailed description three serial port signals follows: Conversion Start Input (CONV) rising edge CONV starts conversion, subsequent rising edges CONV ignored LTC1407-1/ LTC1407A-1 until following rising edges have occurred. duty cycle CONV arbitrarily chosen used frame sync signal processor serial port. simple approach generate CONV create pulse that wide drive LTC1407-1/ LTC1407A-1 then buffer this signal drive frame sync input processor serial port. good practice drive LTC1407-1/LTC1407A-1 CONV input first avoid digital noise interference during sample-to-hold transition triggered CONV start conversion. also good practice keep width portion CONV signal greater than 15ns avoid introducing glitches front just before sampleand-hold goes into Hold mode rising edge CONV. Minimizing Jitter CONV Input high speed applications where high amplitude sinewaves above 100kHz sampled, CONV signal must have little jitter possible (10ps less). square wave output common crystal clock module usually meets this requirement easily. challenge generate CONV signal from this crystal clock without jitter corruption from other digital circuits system. clock divider gates signal path from crystal clock CONV input should share same integrated circuit with other parts system. shown interface circuit examples, CONV inputs should driven first, with digital buffers used drive serial port interface. Also note that master clock already corrupted with jitter, even comes directly from crystal. Another problem with high speed processor clocks that they often cost, speed crystal (i.e., 10MHz) generate fast, jittery, phase-locked-loop system clock (i.e., 40MHz). jitter these PLL-generated high speed clocks several nanoseconds. Note that choose frame sync signal generated port, this signal will have same jitter DSP's master clock.
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
Serial Clock Input (SCK)
rising edge advances conversion process also udpates each data stream. After CONV rises, third rising edge sends sets 12/14 data bits, with sent first. simple approach generate drive LTC1407-1/ LTC1407A-1 first then buffer this signal with appropriate number inverters drive serial clock input processor serial port. falling edge clock latch data from Serial Data Output (SDO) into your processor serial port. 14-bit Serial Data will received right justified, 16-bit words with more clocks frame sync. good practice drive LTC1407-1/LTC1407A-1 input first avoid digital noise interference during internal comparison decision internal high speed comparator. Unlike CONV input, input sensitive jitter because input signal already sampled held constant. Serial Data Output (SDO) Upon power-up, output automatically reset high impedance state. output remains high impedance until conversion started. sends sets 12/14 bits complement format output data stream after third rising edge after start conversion with rising edge CONV. 12-/14-bit words separated clock cycles high impedance mode. Please note delay specification from valid SDO. always guaranteed
CONV LTC1407-1/ LTC1407A-1 CONV 3-WIRE SERIAL INTERFACELINK
LOGIC SWING
Figure Serial Interface TMS320C54x
valid next rising edge SCK. 32-bit output data stream compatible with 16-bit 32-bit serial port most processors. HARDWARE INTERFACE TMS320C54x LTC1407-1/LTC1407A-1 serial output ADCs whose interface been designed high speed buffered serial ports fast digital signal processors (DSPs). Figure shows example this interface using TMS320C54X. buffered serial port TMS320C54x direct access segment memory. ADC's serial data collected alternating segments, real time, full 3Msps conversion rate LTC1407-1/ LTC1407A-1. assembly code sets frame sync mode BFSR accept external positive going pulse serial clock BCLKR accept external positive edge clock. Buffers near LTC1407-1/ LTC1407A-1 added drive long tracks prevent corruption signal LTC1407-1/ LTC1407A-1. This configuration adequate traverse typical system board, source resistors buffer outputs termination resistors DSP, needed match characteristic impedance very long transmission lines. need terminate transmission line, buffer first with 74ACxx gates. threshold inputs port respond properly swing used with LTC1407-1/ LTC1407A-1.
BFSR TMS320C54x BCLKR
14071
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
12-03-03 Files: 014SIAB.ASM 1407A Sine wave collection with Serial Port interface bvectors.asm both channels collected sequence same record. s2k14ini.asm Buffered mode buffer size. First element 1024, last element 1023, middles 2047 0000 bipolar mode Works clock frames. negative edge BCLKR negative BFSR pulse data shifted .width .length .title "sineb0 auto buffer mode" .mmregs .setsect ".text", 0x500,0 ;Set address .setsect "vectors", 0x180,0 ;Set address .setsect "buffer", 0x800,0 ;Set address .setsect "result", 0x1800,0 ;Set address .text ;.text marks
start: ;this label seems necessary ;Make sure /PWRDWN J1-9 turn AC01 tim=#0fh prd=#0fh #10h tspc pmst #01a0h #0700h #1800h #0800h call sineinit sinepeek: call sineinit wait goto wait
stop timer stop serial port AC01 iptr. Processor Mode STatus register init stack pointer. data page pointer computed receive buffer. pointer Buffered Serial Port receive buffer reset record counter Double clutch initialization insure proper reset. external frame sync must occur clocks more after port comes reset.
-Buffered Receive Interrupt Routine
breceive: #10h clear interrupt flags bitf(@BSPCE,#4000h) check which half (bspce(bit14)) buffer (NTC) goto bufull this still first half next half bspce #(2023h 08000h); turn halt second half (bspce(bit15)) return_enable
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executable incoming 1403 data buffer clearing result clearing start code
LTC1407-1/LTC1407A-1
APPLICATIO ATIO
bufull: *ar3+ #07FFFh #2000h *ar2+ data(#0bh) (@ar2 #02000h) (TC) goto start goto bufull bsend
-mask shift input data
load with buffer shift right mask TRISTATE bits with #03FFFh invert bipolar operation store buffer advance pointer output buffer starting 1800h restart buffer 1fffh
-dummy bsend return- return_enable ;this also dummy return define bsend vector table file BVECTORS.ASM .copy "c:\dskplus\1403\s2k14ini.asm" ;initialize buffered serial port .space 16*32 ;clear chunk mark
VECTORS .sect "vectors" ;The vectors start here .copy "c:\dskplus\1403\bvectors.asm" ;get vectors .sect "buffer" .space 16*0x800 .sect "result" .space 16*0x800 .end File: BVECTORS.ASM Vector Table `C54x DSKplus 10.Jul.96 vectors Debugger vectors vectors just return vectors this table configured processing external internal software interrupts. DSKplus debugger uses four interrupt vectors. These RESET, TRAP2, INT2, HPIINT. MODIFY THESE FOUR VECTORS PLAN DEBUGGER other vector locations free use. When programming always sure HPIINT unmasked (IMR=200h) allow communications kernel host interact. INT2 should normally masked (IMR(bit that will interrupt itself during HINT. HINT tied INT2 externally. ;Set address buffer clearing ;Set address result clearing
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
.title "Vector Table" .mmregs reset goto #80h return_enable goto #88h .space 52*16 return_enable return_enable return_enable return_enable goto breceive goto bsend return_enable return_enable return_enable dgoto #0e4h ;00; RESET
;04; non-maskable external interrupt
trap2
;08; trap2
int0
;0C-3F: vectors software interrupts 18-30 ;40; external interrupt int0
int1
;44; external interrupt int1
int2
;48; external interrupt int2
tint
;4C; internal timer interrupt
brint
;50; receive interrupt
bxint
;54; transmit interrupt
trint
;58; receive interrupt
txint
;5C; transmit interrupt
int3
;60; external interrupt int3
hpiint
;64; HPIint
MODIFY USING DEBUGGER MODIFY USING DEBUGGER MODIFY USING DEBUGGER
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
.space 24*16 ;68-7F; reserved area COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 File: s2k14ini.ASM initialization code `C54x DSKplus with 1407 buffered mode BSPC same `C542 BSPCE SPCE seem same `C542 .title "Buffered Serial Port Initialization Routine" .set .set .set .set !YES BIT_8 .set BIT_10 .set BIT_12 .set BIT_16 .set .set 0x80 This example initialize Buffered Serial Port (BSP). initialized require external operation. data format 16-bits, burst mode, with autobuffering enabled. *LTC1407 timing from board with 10MHz crystal. *10MHz, divided from 40MHz, forced CLKIN 1407 board. *Horizontal scale 25ns/chr 100ns period BCLKR *Timing measured pins. labels jumper cable. *BFSR J1-20 ~\_/~\_/ *BCLKR J1-14 ~\_/~\_/~* *BDR J1-26 *CLKIN J5-09 ~\_/~\_/~\_/~\_/ ~\_/~* *C542 read B12* negative edge BCLKR negative BFSR pulse data shifted cable from counter CONV
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LTC1407-1/LTC1407A-1
APPLICATIO ATIO
cable from counter right shift needed right justify input data main program *the msbs should also masked Loopback .set ;(digital looback mode?) Format .set BIT_16 ;(Data format? 16,12,10,8) IntSync .set ;(internal Frame syncs generated?) IntCLK .set ;(internal clks generated?) BurstMode .set ;(if BurstMode=NO, then Continuous) CLKDIV .set ;(3=default value, CLOCKOUT) PCM_Mode .set ;(Turn mode?) FS_polarity .set ;(change polarity)YES=^^^\_/^^^, NO=_/^\_ CLK_polarity .set ;(change polarity)for BCLKR YES=_/^, NO=~\_ Frame_ignore .set !YES ;(inverted !YES -ignores frame) XMTautobuf .set ;(transmit autobuffering) RCVautobuf .set ;(receive autobuffering) XMThalt .set ;(transmit buff halt buff full) RCVhalt .set ;(receive buff halt buff full) XMTbufAddr .set 0x800 ;(address transmit buffer) XMTbufSize .set 0x000 ;(length transmit buffer) RCVbufAddr .set 0x800 ;(address receive buffer) RCVbufSize .set 0x800 ;(length receive buffer)works notes `C54x Peripherals Reference Guide setting valid buffer start length values. Page 9-44 .eval ((Loopback 1)|((Format 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,SPCval .eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format SPCEval .eval SPCEval sineinit: bspc #SPCval #10h #210h intm bspce #SPCEval #XMTbufAddr #XMTbufSize #RCVbufAddr #RCVbufSize bspc #(SPCval return
places buffered serial port reset clear interrupt flags Enable HPINT,enable BRINT0 unmasked interrupts enabled. programs BSPCE initializes transmit buffer start address initializes transmit buffer size initializes receive buffer start address initializes receive buffer size bring buffered serial port reset ;for transmit receive because GO=0xC0
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LTC1407-1/LTC1407A-1
PACKAGE DESCRIPTIO
Package 10-Lead Plastic MSOP
(Reference 05-08-1664)
BOTTOM VIEW EXPOSED OPTION
2.794 0.102 (.110 .004)
0.889 0.127 (.035 .005)
2.06 0.102 (.081 .004) 1.83 0.102 (.072 .004)
5.23 (.206)
2.083 0.102 3.20 3.45 (.082 .004) (.126 .136)
0.50 0.305 0.038 (.0197) (.0120 .0015) RECOMMENDED SOLDER LAYOUT
3.00 0.102 (.118 .004) (NOTE
0.497 0.076 (.0196 .003)
4.90 0.152 (.193 .006) 0.254 (.010) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL 0.18 (.007) SEATING PLANE 1.10 (.043) DETAIL
3.00 0.102 (.118 .004) (NOTE
0.86 (.034)
0.17 0.27 (.007 .011)
NOTE: DIMENSIONS MILLIMETER/(INCH) DRAWING SCALE DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH, PROTRUSIONS GATE BURRS SHALL EXCEED 0.152mm (.006") SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSIONS. INTERLEAD FLASH PROTRUSIONS SHALL EXCEED 0.152mm (.006") SIDE LEAD COPLANARITY (BOTTOM LEADS AFTER FORMING) SHALL 0.102mm (.004")
0.50 (.0197)
0.127 0.076 (.005 .003)
MSOP (MSE) 0603
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC1407-1/LTC1407A-1 RELATED PARTS
PART NUMBER ADCs LTC1608 LTC1609 LTC1403/LTC1403A LTC1407/LTC1407A LTC1411 LTC1420 LTC1405 LTC1412 LTC1402 LTC1864/LTC1865 LTC1864L/LTC1865L DACs LTC1666/LTC1667 LTC1668 LTC1592 References LT1790-2.5 LT1461-2.5 LT1460-2.5 Micropower Series Reference SOT-23 Precision Voltage Reference Micropower Series Voltage Reference 0.05% Initial Accuracy, 10ppm Drift 0.04% Initial Accuracy, 3ppm Drift 0.10% Initial Accuracy, 10ppm Drift 12-/14-/16-Bit, 50Msps 16-Bit, Serial SoftSpanIOUT 87dB SFDR, 20ns Settling Time ±1LSB INL/DNL, Software Selectable Spans 16-Bit, 500ksps Parallel 16-Bit, 250ksps Serial 12-/14-Bit, 2.8Msps Serial 12-/14-Bit, 3Msps Simultaneous Sampling 14-Bit, 2.5Msps Parallel 12-Bit, 10Msps Parallel 12-Bit, 5Msps Parallel 12-Bit, 3Msps Parallel 12-Bit, 2.2Msps Serial 16-Bit, 250ksps 1-/2-Channel Serial ADCs Supply, ±2.5V Span, 90dB SINAD Configurable Bipolar/Unipolar Inputs 15mW, Unipolar Inputs, MSOP Package 15mW, Bipolar Inputs, MSOP Package 14mW, 2-Channel Unipolar Input Range Selectable Spans, 80dB SINAD Selectable Spans, 72dB SINAD Selectable Spans, 115mW Supply, ±2.5V Span, 72dB SINAD Supply, 4.096V ±2.5V Span (L-Version), Micropower, MSOP Package DESCRIPTION COMMENTS
LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial
SoftSpan trademark Linear Technology Corporation.
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Linear Technology Corporation
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LINEAR TECHNOLOGY CORPORATION 2004

DESCRIPTIO 3Msps Sampling with Simultaneous Differential Inputs 1

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