The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

tables below following notations. Access column: Supervisor Access Onl


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



APPENDIX MPC555 INTERNAL MEMORY
tables below following notations. Access column: Supervisor Access Only User Access Test Access Reset column: SRESET HRESET Module Reset Power-On Reset Unchanged Unknown codes Reset column indicate which reset effect register values. INDEX MEMORY TABLES Table (Special Purpose Registers) Table (CDR MoneT Flash EEPROM) Flash Array Table USIU (Unified System Interface Unit) Table (CDR MoneT Flash EEPROM) Table DPTRAM (Dual-Port RAM) Table DPTRAM Array Table TPU3 (Time Processor Unit) Table QADC64 (Queued Analog-to-Digital Converter) Table QSMCM (Queued Serial Multi-Channel Module) Table A-10 MIOS1 (Modular Input/Output Subsystem) Table A-11 TouCAN (CAN 2.0B Controller) Table A-12 UIMB (U-Bus IMB3 Interface)
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA
Table A-13 SRAM (Static Access Memory) Table A-14 SRAM (Static Access Memory) Array
MOTOROLA
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table (Special Purpose Registers)
Address Access Symbol Register Machine State Register. Table 3-12 descriptions Integer Exception Register. Table 3-10 descriptions Link Register. 3.7.6 Link Register (LR) descriptions. Count Register. 3.7.7 Count Register (CTR) descriptions. DAE/Source Instruction Service Register. 3.9.2 DAE/Source Instruction Service Register (DSISR) descriptions. Data Address Register. 3.9.3 Data Address Register (DAR) descriptions. Decrementer Register. 3.9.5 Decrementer Register (DEC) descriptions. Machine Status Save/Restore Register 3.9.6 Machine Status Save/Restore Register (SRR0) descriptions. Machine Status Save/Restore Register 3.9.7 Machine Status Save/Restore Register (SRR1) descriptions. External Interrupt Enable Register 3.9.10.1 EIE, EID, Special-Purpose Registers descriptions. External Interrupt Disable Register 3.9.10.1 EIE, EID, Special-Purpose Registers descriptions. Non-Recoverable Interrupt Register 3.9.10.1 EIE, EID, Special-Purpose Registers descriptions. Comparator Value Register. Table 21-17 descriptions. Comparator Value Register. Table 21-17 descriptions. Comparator Value Register. Table 21-17 descriptions. Comparator Value Register. Table 21-17 descriptions. Exception Cause Register Table 21-26 descriptions. Debug Enable Register Table 21-27 descriptions. Breakpoint Counter Value Control Register Table 21-24 descriptions. Breakpoint Counter Value Control Register Table 21-25 descriptions. Comparator Value Register. Table 21-20 descriptions. Size Reset
DSISR
SRR0
SRR1
CMPA CMPB CMPC CMPD COUNTA COUNTB CMPE
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA
Table (Special Purpose Registers) (Continued)
Address 268, Access read only Symbol CMPF CMPG CMPH LCTRL1 LCTRL2 ICTRL Register Comparator Value Register. Table 21-20 descriptions. Comparator Value Register. Table 21-18 descriptions. Comparator Value Register. Table 21-18 descriptions. L-Bus Support Control Register Table 21-22 descriptions. L-Bus Support Control Register Table 21-23 descriptions. I-Bus Support Control Register. Table 21-21 descriptions. Breakpoint Address Register. Table 21-19 descriptions. Time Base (Read Only). Table 3-11 descriptions. General Special Purpose Registers. 3.9.8 General SPRs (SPRG0-SPRG3) descriptions. General Special Purpose Registers. 3.9.8 General SPRs (SPRG0-SPRG3) descriptions. General Special Purpose Registers. 3.9.8 General SPRs (SPRG0-SPRG3) descriptions. General Special Purpose Registers. 3.9.8 General SPRs (SPRG0-SPRG3) descriptions. Time Base Register (Write Only). Table 3-14 descriptions. Processor Version Registers. Table 3-16 descriptions. Global Region Attribute Register. Table descriptions. Global Region Attribute Register. Table 11-10 descriptions. Module Configuration Register. Table descriptions. Module Configuration Register. Table 11-7 descriptions. Development Port Data Register. Internal Memory Mapping Register. Table 6-11 descriptions. Region Address Register Table descriptions. Region Address Register Table descriptions. Region Address Register Table descriptions. Region Address Register Table descriptions. Region Address Register. Table 11-8 descriptions. Size Reset
SPRG0
SPRG1
SPRG2
write only read only
SPRG3
284,
MI_GRA L2U_GRA BBCMCR L2U_MCR DPDR IMMR MI_RBA0 MI_RBA1 MI_RBA2 MI_RBA3 L2U_RBA0
POR, POR, POR,
MOTOROLA
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table (Special Purpose Registers) (Continued)
Address Access Symbol L2U_RBA1 L2U_RBA2 L2U_RBA3 MI_RA0 MI_RA1 MI_RA2 MI_RA3 L2U_RA0 L2U_RA1 L2U_RA2 L2U_RA3 Register Region Address Register. Table 11-8 descriptions. Region Address Register. Table 11-8 descriptions. Region 3Address Register. Table 11-8 descriptions. Region Attribute Register Table descriptions. Region Attribute Register Table descriptions. Region Attribute Register Table descriptions. Region Attribute Register Table descriptions. Region Attribute Register. Table 11-9 descriptions. Region Attribute Register. Table 11-9 descriptions. Region Attribute Register. Table 11-9 descriptions. Region Attribute Register. Table 11-9 descriptions. Floating-Point Exception Cause Register. 3.9.10.2 Floating-Point Exception Cause Register (FPECR) descriptions. Size Reset POR, POR, POR, POR, POR, POR, POR,
1022
FPECR
Table (CDR MoneT Flash EEPROM) Flash Array
Address 0x00 0000 0x03 FFFF 0x04 0000 0x06 FFFF Access Symbol CMF_A Array CMF_B Array Register Size Reset
Table USIU (Unified System Interface Unit)
Address 0x2F C000 0x2F C004 0x2F C008 0x2F C00E Access write only SWSR Symbol SIUMCR SYPCR Register Module Configuration Register. Table descriptions. System Protection Control Register. Table 6-13 descriptions. Reserved Software Service Register. Table 6-14 descriptions. Interrupt Pending Register. 6.13.2.1 SIPEND Register descriptions. Interrupt Mask Register. 6.13.2.2 Interrupt Mask Register (SIMASK) descriptions. Size Reset
0x2F C010
SIPEND
0x2F C014
SIMASK
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA
Table USIU (Unified System Interface Unit) (Continued)
Address 0x2F C018 Access SIEL Symbol Register Interrupt Edge Level Mask. 6.13.2.3 Interrupt Edge Level Register (SIEL) descriptions. Interrupt Vector. 6.13.2.4 Interrupt Vector Register descriptions. Transfer Error Status Register. Table 6-15 descriptions. USIU General-Purpose Data Register Table 6-21 descriptions. USIU General-Purpose Data Register Table 6-22 descriptions. USIU General-Purpose Control Register. Table 6-23 descriptions. External Master Mode Control Register. Table 6-12 descriptions. Pads Module Configuration Register. Table descriptions. Reserved Memory Controller Registers 0x2F C100 0x2F C104 0x2F C108 0x2F C10C 0x2F C110 0x2F C114 0x2F C118 0x2F C11C 0x2F C120 0x2F C13C 0x2F C140 0x2F C144 0x2F C148 0x2F C174 0x2F C178 MSTAT DMBR DMOR Base Register Table 10-7 descriptions. Option Register Table 10-8 descriptions. Base Register Table 10-7 descriptions. Option Register Table 10-8 descriptions. Base Register Table 10-7 descriptions. Option Register Table 10-8 descriptions. Base Register Table 10-7 descriptions. Option Register Table 10-8 descriptions. Reserved Dual-Mapping Base Register. Table 10-9 descriptions. Dual-Mapping Option Register. Table 10-10 descriptions. Reserved Memory Status. Table 10-6 descriptions. System Integration Timers 0x2F C200 TBSCR Time Base Status Control. Table 6-16 descriptions. Time Base Reference 6.13.4.3 Time Base Reference Registers descriptions. Size Reset
0x2F C01C
read only
SIVEC
0x2F C020 0x2F C024 0x2F C028 0x2F C02C 0x2F C030 0x2F C03C 0x2F C040 0x2F C0FC
TESR SGPIODT1 SGPIODT2 SGPIOCR EMCR PDMCR
0x2F C204
TBREF0
MOTOROLA
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table USIU (Unified System Interface Unit) (Continued)
Address 0x2F C208 0x2F C20C 0x2F C21C 0x2F C220 Access Symbol TBREF1 Register Time Base Reference 6.13.4.3 Time Base Reference Registers descriptions. Reserved Real Time Clock Status Control. Table 6-17 descriptions. Real Time Clock. 6.13.4.6 Real-Time Clock Register (RTC) descriptions. Real Time Alarm Seconds, reserved. Real Time Alarm. 6.13.4.7 Real-Time Clock Alarm Register (RTCAL) descriptions. PISCR PITC PITR Reserved Status Control. Table 6-18 descriptions. Count. Table 6-19 descriptions. Register. Table 6-20 descriptions. Reserved Clocks Reset 0x2F C280 0x2F C284 0x2F C288 0x2F C28C 0x2F C290 0x2F C294 0x2F C2FC U3,5,6 SCCR PLPRCR COLIR VSRMCR System Clock Control Register. Table descriptions. Power Reset Control Register. Table 8-10 descriptions. Reset Status Register. Table descriptions. Change Lock Interrupt Register. Table 8-11 descriptions. VDDSRM Control Register. Table 8-12 descriptions. Reserved System Integration Timer Keys 0x2F C300 0x2F C304 0x2F C308 0x2F C30C 0x2F C310 0x2F C31C 0x2F C320 0x2F C324 TBSCRK TBREF0K TBREF1K RTCSCK RTCK Time Base Status Control Key. Table descriptions. Time Base Reference Key. Table descriptions. Time Base Reference Key. Table descriptions. Time Base Decrementer Key. Table descriptions. Reserved Real-Time Clock Status Control Key. Table descriptions. Real-Time Clock Key. Table descriptions. Size Reset
RTCSC
0x2F C224 0x2F C228 0x2F C22C 0x2F C230 0x2F C23C 0x2F C240 0x2F C244 0x2F C248 0x2F C24C 0x2F C27C
RTSEC RTCAL
read only
(half reserved) (half reserved)
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA
Table USIU (Unified System Interface Unit) (Continued)
Address 0x2F C328 0x2F C32C 0x2F C330 0x2F C33C 0x2F C340 0x2F C344 0x2F C348 0x2F C37C Access Symbol RTSECK RTCALK PISCRIK PITCK Register Real-Time Alarm Seconds Key. Table descriptions. Real-Time Alarm Key. Table descriptions. Reserved Status Control Key. Table descriptions. Count Key. Table descriptions. Reserved Clocks Reset Keys 0x2F C380 0x2F C384 0x2F C388 0x2F C38C 0x2F C3FC SCCRK PLPRCRK RSRK System Clock Control Key. Table descriptions. Low-Power Reset Control Register Key. Table descriptions. Reset Status Register Key. Table descriptions. Reserved Size Reset
NOTES: Entire register locked (DLK) set. Write once after power reset (POR). Must register unlock been locked register, 8.9.3.2 Keep Alive Power Registers Lock Mechanism. Locked after Power Reset (POR). write 0x55CCAA33 must performed register unlock. 8.9.3.2 Keep Alive Power Registers Lock Mechanism.
have bits 0:11 bits) write-protected setting (MFPDL) SCCR register (CSRC) bits 22:23 (LPM) locked setting (LPML) SCCR register (CSR) write-once after soft reset.
Table (CDR MoneT Flash EEPROM)
Address Access Symbol CMF_A 0x2F C800 0x2F C804 0x2F C808 CMFMCR CMF_A EEPROM Configuration Register. Table 19-2 descriptions. CMF_A EEPROM Test Register. Table 19-3 descriptions. CMF_A EEPROM High Voltage Control Register. Table 19-5 descriptions. CMF_B 0x2F C840 0x2F C844 0x2F C848 CMFMCR CMF_B EEPROM Configuration Register. Table 19-2 descriptions. CMF_B EEPROM Test Register. Table 19-3 descriptions. CMF_B EEPROM High Voltage Control Register. Table 19-5 descriptions. POR, POR, POR, POR, POR, POR, Register Size Reset
CMFTST
CMFCTL
CMFTST
CMFCTL
NOTES: (FIC) write-once. (LOCK) write-once unless freeze test mode.
MOTOROLA
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table DPTRAM (Dual-Port RAM)
Address 0x30 0000 0x30 0002 0x30 0004 Access read only read only read only Symbol DPTMCR RAMTST RAMBAR Register Module Configuration Register. Table 18-2 descriptions. Test register, factory test only. Array Address Register. Table 18-3 descriptions. Multiple Input Signature Register High. 18.3.4 MISR High (MISRH) MISR (MISRL) descriptions. Multiple Input Signature Register Low. 18.3.4 MISR High (MISRH) MISR (MISRL) descriptions. MISC Counter. 18.3.5 MISC Counter (MISCNT) descriptions. Size Reset POR, POR,
0x30 0006
MISRH
0x30 0008
MISRL
0x30 000A
MISCNT
NOTES: Entire register write-once.
Table DPTRAM Array
Address 0x30 2000 0x30 37FF Access Symbol DPTRAM Array Register Size Reset
NOTES: Access DPTRAM array through IMB3 disabled once (EMU) either TPUMCR set.
Table TPU3 (Time Processor Unit)
Address Access Symbol Register Size Reset TPU_A (Note: descriptions apply TPU_B well) 0x30 4000 0x30 4002 0x30 4004 0x30 4006 0x30 4008 0x30 400A 0x30 400C 0x30 400E 0x30 4010 0x30 4012 TPUMCR_A TCR_A DSCR_A DSSR_A TICR_A CIER_A CFSR0_A CFSR1_A CFSR2_A CFSR3_A TPU3_A Module Configuration Register. Table 17-6 descriptions. TPU3_A Test Configuration Register. TPU3_A Development Support Control Register. Table 17-7 descriptions. TPU3_A Development Support Status Register. Table 17-8 descriptions. TPU3_A Interrupt Configuration Register. Table 17-9 descriptions. TPU3_A Channel Interrupt Enable Register. Table 17-10 descriptions. TPU3_A Channel Function Selection Register Table 17-11 descriptions. TPU3_A Channel Function Selection Register Table 17-11 descriptions. TPU3_A Channel Function Selection Register Table 17-11 descriptions. TPU_A Channel Function Selection Register Table 17-11 descriptions. only
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA
Table TPU3 (Time Processor Unit) (Continued)
Address 0x30 4014 0x30 4016 0x30 4018 0x30 401A 0x30 401C 0x30 401E 0x30 4020 0x30 4022 0x30 4024 0x30 4026 0x30 4028 0x30 402A 0x30 402C 0x30 402E 0x30 4100 0x30 410F 0x30 4110 0x30 411F 0x30 4120 0x30 412F 0x30 4130 0x30 413F 0x30 4140 0x30 414F 0x30 4150 0x30 415F 0x30 4160 0x30 416F 0x30 4170 0x30 417F 0x30 4180 0x30 418F 0x30 4190 0x30 419F 0x30 41A0 0x30 41AF 0x30 41B0 0x30 41BF 0x30 41C0 0x30 41CF 0x30 41D0 0x30 41DF Access S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 Symbol HSQR0_A HSQR1_A HSRR0_A HSRR1_A CPR0_A CPR1_A CISR_A LR_A SGLR_A DCNR_A TPUMCR2_A TPUMCR3_A ISDR_A ISCR_A Register TPU_A Host Sequence Register Table 17-12 descriptions. TPU_A Host Sequence Register Table 17-12 descriptions. TPU_A Host Service Request Register Table 17-13 descriptions. TPU_A Host Service Request Register Table 17-13 descriptions. TPU_A Channel Priority Register Table 17-14 descriptions. TPU_A Channel Priority Register Table 17-14 descriptions. TPU_A Channel Interrupt Status Register. Table 17-16 descriptions. TPU_A Link Register TPU_A Service Grant Latch Register TPU_A Decoded Channel Number Register TPU_A Module Configuration Register Table 17-17 descriptions. TPU_A Module Configuration Register Table 17-20 descriptions. TPU_A Internal Scan Data Register TPU_A Internal Scan Control Register TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers. TPU_A Channel Parameter Registers. TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers Size Reset
MOTOROLA A-10
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table TPU3 (Time Processor Unit) (Continued)
Address 0x30 41E0 0x30 41EF 0x30 41F0 0x30 41FF 0x30 44001 0x30 4402 0x30 4404 0x30 4406 0x30 4408 0x30 440A 0x30 440C 0x30 440E 0x30 4410 0x30 4412 0x30 4414 0x30 4416 0x30 4418 0x30 441A 0x30 441C 0x30 441E 0x30 4420 0x30 4422 0x30 4424 0x30 4426 0x30 4428 0x30 442A 0x30 442C 0x30 442E 0x30 4500 0x30 450E 0x30 4510 0x30 451E 0x30 4520 0x30 452E 0x30 4530 0x30 453E 0x30 4540 0x30 454E 0x30 4550 0x30 455E 0x30 4560 0x30 456E 0x30 4570 0x30 457E Access S/U3 S/U3 Symbol Register TPU_A Channel Parameter Registers TPU_A Channel Parameter Registers TPU_B S/U3 S/U3 S/U3 S/U3
Size
Reset
TPUMCR_B TCR_B DSCR_B DSSR_B TICR_B CIER_B CFSR0_B CFSR1_B CFSR2_B CFSR3_B HSQR0_B HSQR1_B HSRR0_B HSRR1_B CPR0_B CPR1_B CISR_B LR_B SGLR_B DCNR_B TPUMCR2_B TPUMCR3_B ISDR_B ISCR_B
TPU3_B Module Configuration Register TPU3_B Test Configuration Register TPU3_B Development Support Control Register TPU3_B Development Support Status Register TPU3_B Interrupt Configuration Register TPU3_B Channel Interrupt Enable Register TPU3_B Channel Function Selection Register TPU3_B Channel Function Selection Register TPU3_B Channel Function Selection Register TPU_B Channel Function Selection Register TPU_B Host Sequence Register TPU_B Host Sequence Register TPU_B Host Service Request Register TPU_B Host Service Request Register TPU_B Channel Priority Register TPU_B Channel Priority Register TPU_B Channel Interrupt Status Register TPU_B Link Register TPU_B Service Grant Latch Register TPU_B Decoded Channel Number Register TPU_B Module Configuration Register TPU_B Module Configuration Register TPU_B Internal Scan Data Register TPU_B Internal Scan Control Register TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers
only
S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA A-11
Table TPU3 (Time Processor Unit) (Continued)
Address 0x30 4580 0x30 458E 0x30 4590 0x30 459E 0x30 45A0 0x30 45AE 0x30 45B0 0x30 45BF 0x30 45C0 0x30 45CF 0x30 45D0 0x30 45DF 0x30 45E0 0x30 45EF 0x30 45F0 0x30 45FF Access S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 Symbol Register TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers TPU_B Channel Parameter Registers Size Reset
NOTES: (TPU3) (T2CSL) write-once. Bits (TCR1P) bits (TCR2P) write-once PWOD TPUMCR3 register. This register cannot accessed with 32-bit read. only accessed with 16-bit read. Some registers only read written with 32-bit accesses. 8-bit accesses allowed. Supervisor accessible only SUPV unrestricted SUPV Unrestricted registers allow both user supervisor access. SUPV TPUMCR register. Bits 9:10 (ETBANK), (T2CF), (DTPU) write-once.
Table QADC64 (Queued Analog-to-Digital Converter)
Address Access Symbol Register Size Reset QADC_A (Note: descriptions apply QADC_B well) 0x30 4800 0x30 4802 0x30 4804 0x30 4806 0x30 4808 0x30 480A 0x30 480C 0x30 480E 0x30 4810 0x30 4812 0x30 4814 0x30 49FE S/U1 S/U1 QADC64MCR_A QADC64TEST_A QADC64INT_A PORTQA_A/ PORTQB_A DDRQA_A/ DDRQB_A QACR0_A QACR1_A QACR2_A QASR0_A QASR1_A QADC64 Module Configuration Register. Table 13-7 descriptions. QADC64 Test Register Interrupt Register. Table 13-8 descriptions. Port Port Data. Table 13-9 descriptions. Port Data Port Direction Register. Table 13-10 descriptions. QADC64 Control Register Table 13-11 descriptions. QADC64 Control Register Table 13-12 descriptions. QADC64 Control Register Table 13-14 descriptions. QADC64 Status Register Table 13-16 descriptions. QADC64 Status Register Table 13-18 descriptions. Reserved
MOTOROLA A-12
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table QADC64 (Queued Analog-to-Digital Converter) (Continued)
Address 0x30 4A00 0x30 4A7E 0x30 4A80 0x30 4AFE 0x30 4B00 0x30 4B7E 0x30 4B80 0x30 4BFE Access Symbol CCW_A Register Conversion Command Word Table. Table 13-19 descriptions. Result Word Table Right-Justified, Unsigned Result Register. 13.12.12 descriptions. Result Word Table Left-Justified, Signed Result Register. 13.12.12 descriptions. Result Word Table Left-Justified, Unsigned Result Register. 13.12.12 descriptions. QADC_B 0x30 4C00 0x30 4C02 0x30 4C04 0x30 4C06 0x30 4C08 0x30 4C0A 0x30 4C0C 0x30 4C0E 0x30 4C10 0x30 4C12 0x30 4C14 0x30 4DFE 0x30 4E00 0x30 4E7E 0x30 4E80 0x30 4EFE 0x30 4F00 0x30 4F7E 0x30 4F80 0x30 4FFE
Size
Reset
RJURR_A
LJSRR_A
LJURR_A
QADC64MCR_B QADC64TEST_B QADC64INT_B PORTQA_B/ PORTQB_B DDRQA_B/ DDRQB_B QACR0_B QACR1_B QACR2_B QASR0_B QASR1_B CCW_B RJURR_B LJSRR_B LJURR_B
QADC64 Module Configuration Register QADC64 Test Register Interrupt Register Port Port Data Port Data Port Direction Register QADC64 Control Register QADC64 Control Register QADC64 Control Register QADC64 Status Register QADC64 Status Register Reserved Conversion Command Word Table Result Word Table. Right-Justified, Unsigned Result Register. Result Word Table. Left-Justified, Signed Result Register. Result Word Table. Left-Justified, Unsigned Result Register.
NOTES: (SSEx) readable test mode only.
Table QSMCM (Queued Serial Multi-Channel Module)
Address 0x30 5000 0x30 5002 0x30 5004 0x30 5006 0x30 5008 0x30 500A Access Symbol QSMCMMCR QTEST QDSCI_IL QSPI_IL SCC1R0 SCC1R1 Register QSMCM Module Configuration Register. Table 14-4 descriptions. QSMCM Test Register Dual Interrupt Level. Table 14-5 descriptions. Queued Interrupt Level. Table 14-6 descriptions. SCI1Control Register Table 14-23 descriptions. SCI1Control Register Table 14-24 descriptions. Size Reset POR, POR, POR, POR, POR, POR,
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA A-13
Table QSMCM (Queued Serial Multi-Channel Module) (Continued)
Address 0x30 500C 0x30 500E 0x30 5010 0x30 5012 0x30 5014 Access Symbol SC1SR SC1DR Register SCI1 Status Register. Table 14-25 descriptions. SCI1 Data Register. Table 14-26 descriptions. Reserved QSMCM Port Data Register. 14.6.1 Port Data Register (PORTQS) descriptions. QSMCM Port Assignment Register/ QSMCM Port Data Direction Register. Table 14-11 descriptions. QSPI Control Register Table 14-13 descriptions. QSPI Control Register Table 14-15 descriptions. QSPI Control Register Table 14-16 descriptions. QSPI Control Register Table 14-17 descriptions. QSPI Status Register Table 14-18 descriptions. SCI2 Control Register SCI2 Control Register SCI2 Status Register SCI2 Data Register QSCI1 Control Register. Table 14-33 descriptions. QSCI1 Status Register. Table 14-34 descriptions. Transmit Queue Locations Receive Queue Locations RECRAM TRAN.RAM COMD.RAM Reserved Receive Data Transmit Data Command Size Reset POR, POR,
PORTQS
POR,
0x30 5016
PQSPAR/ DDRQST SPCR0 SPCR1 SPCR2 SPCR3 SPSR SCC2R0 SCC2R1 SC2SR SC2DR QSCI1CR QSCI1SR SCTQ SCRQ
POR,
0x30 5018 0x30 501A 0x30 501C 0x30 501E 0x30 501F 0x30 5020 0x30 5022 0x30 5024 0x30 5026 0x30 5028 0x30 502A 0x30 502C 0x30 504A 0x30 504C 0x30 506A 0x30 506C 0x30 5013F 0x30 5140 0x30 517F 0x30 5180 0x30 51BF 0x30 51C0 0x30 51DF
S/U1 S/U2
POR, POR, POR, POR, POR, POR, POR, POR, POR, POR, POR, POR, POR,
NOTES: Bits writeable only test mode, otherwise read only. Bits 3-11 writeable only test mode, otherwise read only.
MOTOROLA A-14
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table A-10 MIOS1 (Modular Input/Output Subsystem)
Address Access Symbol Register MPWMSM0 Period Register. Table 15-20 descriptions. MPWMSM0 Pulse Register. Table 15-21 descriptions. MPWMSM0 Count Register. Table 15-22 descriptions. MPWMSM0 Status/Control Register. Table 15-23 descriptions. MPWMSM1 Period Register. Table 15-20 descriptions. MPWMSM1 Pulse Register. Table 15-21 descriptions. MPWMSM1 Count Register. Table 15-22 descriptions. MPWMSM1 Status/Control Register. Table 15-23 descriptions. MPWMSM2 Period Register. Table 15-20 descriptions. MPWMSM2 Pulse Register. Table 15-21 descriptions. MPWMSM2 Count Register. Table 15-22 descriptions. MPWMSM2 Status/Control Register. Table 15-23 descriptions. MPWMSM3 Period Register. Table 15-20 descriptions. MPWMSM3 Pulse Register. Table 15-21 descriptions. MPWMSM3 Count Register. Table 15-22 descriptions. MPWMSM3 Status/Control Register. Table 15-23 descriptions. MMCSM6 Up-Counter Register. Table 15-12 descriptions. MMCSM6 Modulus Latch Register. Table 15-13 descriptions. MMCSM6 Status/Control Register Duplicated. 15.10.1.3 MMCSM Status/Control Register (Duplicated) descriptions. MMCSM6 Status/Control Register. Table 15-14 descriptions. MDASM11 Data Register. 15.11.1.1 MDASM Data Register descriptions. Size Reset MPWMSM0 (MIOS Pulse Width Modulation Submodule 0x30 6000 0x30 6002 0x30 6004 0x30 6006 MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MPWMSM1 (MIOS Pulse Width Modulation Submodule 0x30 6008 0x30 600A 0x30 600C 0x30 600E MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MPWMSM2 (MIOS Pulse Width Modulation Submodule 0x30 6010 0x30 6012 0x30 6014 0x30 6016 MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MPWMSM3 (MIOS Pulse Width Modulation Submodule 0x30 6018 0x30 601A 0x30 601C 0x30 601E MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MMCSM6 (MIOS Modulus Counter Submodule 0x30 6030 0x30 6032 MMCSMCNT MMCSMML
0x30 6034
MMCSMSCRD
0x30 6036
MMCSMSCR
MDASM11 (MIOS Double Action Submodule 0x30 6058 MDASMAR
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA A-15
Table A-10 MIOS1 (Modular Input/Output Subsystem) (Continued)
Address 0x30 605A Access Symbol MDASMBR Register MDASM11 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM11 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM11 Status/Control Register. Table 15-17 descriptions. MDASM12 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM12 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM12 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM12 Status/Control Register. Table 15-17 descriptions. MDASM13 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM13 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM13 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM13 Status/Control Register. Table 15-17 descriptions. MDASM14 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM14 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM14 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM14 Status/Control Register. Table 15-17 descriptions. MDASM15 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM15 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM15 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. Size Reset
0x30 605C
MDASMSCRD
0x30 605E
MDASMSCR
MDASM12 (MIOS Double Action Submodule 0x30 6060 MDASMAR
0x30 6062
MDASMBR
0x30 6064
MDASMSCRD
0x30 6066
MDASMSCR
MDASM13 (MIOS Double Action Submodule 0x30 6068 MDASMAR
0x30 606A
MDASMBR
0x30 606C
MDASMSCRD
0x30 606E
MDASMSCR
MDASM14 (MIOS Double Action Submodule 0x30 6070 MDASMAR
0x30 6072
MDASMBR
0x30 6074
MDASMSCRD
0x30 6076
MDASMSCR
MDASM15 (MIOS Double Action Submodule 0x30 6078 MDASMAR
0x30 607A
MDASMBR
0x30 607C
MDASMSCRD
MOTOROLA A-16
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table A-10 MIOS1 (Modular Input/Output Subsystem) (Continued)
Address 0x30 607E Access Symbol MDASMSCR Register MDASM15 Status/Control Register. Table 15-17 descriptions. MPWMSM16 Period Register. Table 15-20 descriptions. MPWMSM16 Pulse Register. Table 15-21 descriptions. MPWMSM16 Count Register. Table 15-22 descriptions. MPWMSM16 Status/Control Register. Table 15-23 descriptions. MPWMSM17 Period Register. Table 15-20 descriptions. MPWMSM17 Pulse Register. Table 15-21 descriptions. MPWMSM17 Count Register. Table 15-22 descriptions. MPWMSM17 Status/Control Register. Table 15-23 descriptions. MPWMSM18 Period Register. Table 15-20 descriptions. MPWMSM18 Pulse Register. Table 15-21 descriptions. MPWMSM18 Count Register. Table 15-22 descriptions. MPWMSM18 Status/Control Register. Table 15-23 descriptions. MPWMSM19 Period Register. Table 15-20 descriptions. MPWMSM19 Pulse Register. Table 15-21 descriptions. MPWMSM19 Count Register. Table 15-22 descriptions. MPWMSM19 Status/Control Register. Table 15-23 descriptions. MMCSM Up-Counter Register. Table 15-12 descriptions. MMCSM Modulus Latch Register. Table 15-12 descriptions. MMCSM Status/Control Register Duplicated. 15.10.1.3 MMCSM Status/Control Register (Duplicated) descriptions. MMCSM Status/Control Register. Table 15-14 descriptions. MDASM27 Data Register. 15.11.1.1 MDASM Data Register descriptions. Size Reset
MPWMSM16 (MIOS Pulse Width Modulation Submodule 0x30 6080 0x30 6082 0x30 6084 0x30 6086 MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MPWMSM17 (MIOS Pulse Width Modulation Submodule 0x30 6088 0x30 608A 0x30 608C 0x30 608E MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MPWMSM18 (MIOS Pulse Width Modulation Submodule 0x30 6090 0x30 6092 0x30 6094 0x30 6096 MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MPWMSM19 (MIOS Pulse Width Modulation Submodule 0x30 6098 0x30 609A 0x30 609C 0x30 609E MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR
MMCSM22 (MIOS Modulus Counter Submodule 0x30 60B0 0x30 60B2 MMCSMCNT MMCSMML
0x30 60B4
MMCSMSCRD
0x30 60B6
MMCSMSCR
MDASM27 (MIOS Double Action Submodule 0x30 60D8 MDASMAR
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA A-17
Table A-10 MIOS1 (Modular Input/Output Subsystem) (Continued)
Address 0x30 60DA Access Symbol MDASMBR Register MDASM27 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM27 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM27 Status/Control Register. Table 15-17 descriptions. MDASM28 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM28 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM28 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM28 Status/Control Register. Table 15-17 descriptions. MDASM29 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM29 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM29 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM29 Status/Control Register. Table 15-17 descriptions. MDASM30 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM30 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM30 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. MDASM30 Status/Control Register. Table 15-17 descriptions. MDASM31 Data Register. 15.11.1.1 MDASM Data Register descriptions. MDASM31 Data Register. 15.11.1.2 MDASM Data Register (MDASMBR) descriptions. MDASM31 Status/Control Register Duplicated. 15.11.1.3 MDASM Status/Control Register (Duplicated) descriptions. Size Reset
0x30 60DC
MDASMSCRD
0x30 60DE
MDASMSCR
MDASM28 (MIOS Double Action Submodule 0x30 60E0 MDASMAR
0x30 60E2
MDASMBR
0x30 60E4
MDASMSCRD
0x30 60E6
MDASMSCR
MDASM29 (MIOS Double Action Submodule 0x30 60E8 MDASMAR
0x30 60EA
MDASMBR
0x30 60EC
MDASMSCRD
0x30 60EE
MDASMSCR
MDASM30 (MIOS Double Action Submodule 0x30 60F0 MDASMAR
0x30 60F2
MDASMBR
0x30 60F4
MDASMSCRD
0x30 60F6
MDASMSCR
MDASM31 (MIOS Double Action Submodule 0x30 60F8 MDASMAR
0x30 60FA
MDASMBR
0x30 60FC
MDASMSCRD
MOTOROLA A-18
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table A-10 MIOS1 (Modular Input/Output Subsystem) (Continued)
Address 0x30 60FE Access Symbol MDASMSCR Register MDASM31 Status/Control Register. Table 15-17 descriptions. MPIOSM Data Register. Table 15-26 descriptions. MPIOSM Data Direction Register. Table 15-27 descriptions. Reserved Size Reset
MPIOSM (MIOS 16-bit Parallel Port Submodule) 0x30 6100 0x30 6102 0x30 6104 0x30 6106 MPIOSMDR MPIOSMDDR
MBISM (MIOS Interface Submodule) 0x30 6800 0x30 6802 0x30 6804 0x30 6806 0x30 6808 0x30 680E 0x30 6810 0x30 6814 0x30 6816 read only MIOS1TPCR MIOS1VNR MIOS1MCR MIOS1 Test Control Register. Table 15-3 descriptions. Reserved MIOS1 Module Version Number Register. Table 15-4 descriptions. MIOS1 Module Control Register. Table 15-4 descriptions. Reserved
MCPSM (MIOS Counter Prescaler Submodule) MCPSMSCR Reserved MCPSM Status/Control Register. Table 15-10 descriptions. MIRSM0 Interrupt Status Register. Table 15-29 descriptions. Reserved MIRSM0 Interrupt Enable Register. Table 15-30 descriptions. MIRSM0 Request Pending Register. Table 15-31 descriptions. MIOS1 Interrupt Level Register Table 15-7 descriptions. MIRSM1 Interrupt Status Register. Table 15-33 descriptions. Reserved MIRSM1 Interrupt Enable Register. Table 15-34 descriptions. MIRSM1 Request Pending Register. Table 15-35 descriptions. MIOS1 Interrupt Level Register Table 15-8 descriptions.
MIRSM0 (MIOS Interrupt Request Submodule 0x30 6C00 0x30 6C02 0x30 6C04 0x30 6C06 read only MIOS1SR0 MIOS1ER0 MIOS1RPR0
MIRSM (MIOS Interrupt Request Submodule) 0x30 6C30 MIOS1LVL0
MIRSM1 (MIOS Interrupt Request Submodule 0x30 6C40 0x30 6C42 0x30 6C44 0x30 6C46 read only MIOS1SR1 MIOS1ER1 MIOS1RPR1
MIRSM (MIOS Interrupt Request Submodule) 0x30 6C70 MIOS1LVL1
NOTES: (TEST) reserved factory testing.
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA A-19
Table A-11 TouCAN (CAN 2.0B Controller)
Address Access Symbol Register Size Reset TouCAN_A (Note: descriptions apply TouCAN_B well) 0x30 7080 0x30 7082 0x30 7084 TCNMCR_A TTR_A CANICR_A TouCAN_A Module Configuration Register. Table 16-11 descriptions. TouCAN_A Test Register TouCAN_A Interrupt Configuration Register. Table 16-12 descriptions. TouCAN_A Control Register TouCAN_A Control Register Table 16-13 Table 16-16 descriptions. TouCAN_A Control Prescaler Divider Register/ TouCAN_A Control Register Table 16-17 Table 16-18 descriptions. TouCAN_A Free-Running Timer Register. Table 16-19 descriptions. Reserved TouCAN_A Receive Global Mask High. Table 16-20 descriptions. TouCAN_A Receive Global Mask Low. Table 16-20 descriptions. TouCAN_A Receive Buffer Mask High. 16.7.10 Receive Buffer Mask Registers descriptions. TouCAN_A Receive Buffer Mask Low. 16.7.10 Receive Buffer Mask Registers descriptions. TouCAN_A Receive Buffer Mask High. 16.7.11 Receive Buffer Mask Registers descriptions. TouCAN_A Receive Buffer Mask Low. 16.7.11 Receive Buffer Mask Registers descriptions. Reserved TouCAN_A Error Status Register. Table 16-21 descriptions. TouCAN_A Interrupt Masks. Table 16-24 descriptions. TouCAN_A Interrupt Flags. Table 16-25 descriptions. TouCAN_A Receive Error Counter/ TouCAN_A Transmit Error Counter. Table 16-26 descriptions. TouCAN_B 0x30 7480 0x30 7482 0x30 7484 0x30 7486 TCNMCR_B TTR_B CANICR_B CANCTRL0_B/ CANCTRL1_B TouCAN_B Module Configuration Register TouCAN_B Test Register TouCAN_B Interrupt Configuration Register TouCAN_B Control Register TouCAN_B Control Register
0x30 7086
CANCTRL0_A/ CANCTRL1_A
0x30 7088
PRESDIV_A/ CTRL2_A
0x30 708A 0x30 708C 0x30 708E 0x30 7090 0x30 7092
TIMER_A RXGMASKHI_A RXGMASKLO_A
0x30 7094
RX14MASKHI_A
0x30 7096
RX14MASKLO_A
0x30 7098
RX15MASKHI_A
0x30 709A 0x30 709C 0x30 709E 0x30 70A0 0x30 70A2 0x30 70A4
RX15MASKLO_A
ESTAT_A IMASK_A IFLAG_A RXECTR_A/ TXECTR_A
0x30 70A6
MOTOROLA A-20
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL
Table A-11 TouCAN (CAN 2.0B Controller) (Continued)
Address 0x30 7488 0x30 748A 0x30 748C 0x30 748E 0x30 7490 0x30 7492 0x30 7494 0x30 7496 0x30 7498 0x30 749A 0x30 749C 0x30 749E 0x30 74A0 0x30 74A2 0x30 74A4 0x30 74A6 Access Symbol PRESDIV_B/ CTRL2_B TIMER_B RXGMASKHI_B RXGMASKLO_B RX14MASKHI_B RX14MASKLO_B RX15MASKHI_B RX15MASKLO_B ESTAT_B IMASK_B IFLAG_B RXECTR_B/ TXECTR_B Register TouCAN_B Control Prescaler Divider Register/ TouCAN_B Control Register TouCAN_B Free-Running Timer Register Reserved TouCAN_B Receive Global Mask High TouCAN_B Receive Global Mask TouCAN_B Receive Buffer Mask High TouCAN_B Receive Buffer Mask TouCAN_B Receive Buffer Mask High TouCAN_B Receive Buffer Mask Reserved TouCAN_B Error Status Register TouCAN_B Interrupt Masks TouCAN_B Interrupt Flags TouCAN_B Receive Error Counter/ TouCAN_B Transmit Error Counter Size Reset
Table A-12 UIMB (U-Bus IMB3 Interface)
Address 0x30 7F80 0x30 7F90 0x30 7FA0 Access read only Symbol UMCR UTSTCREG UIPEND Register UIMB Module Configuration Register. Table 12-6 descriptions. Test Register Reserved Pending Interrupt Request Register. Table 12-7 descriptions. Size Reset
NOTES: (HSPEED) write-once.
Table A-13 SRAM (Static Access Memory)
Address Access Symbol SRAM_A 0x38 0000 0x38 0004 SRAMMCR_A SRAMTST_A SRAM_A Module Configuration Register. Table 20-1 descriptions. SRAM_A Test Register. SRAM_B 0x38 0008 0x38 000C SRAMMCR_B SRAMTST_B SRAM_B Module Configuration Register. Table 20-1 descriptions. SRAM_B Test Register. S,H, S,H, S,H, S,H, Register Size Reset
NOTES: (LCK) locks register (write-protected except test mode) write once.
MPC555 USER'S MANUAL
MPC555 INTERNAL MEMORY Rev. January 1999
MOTOROLA A-21
Table A-14 SRAM (Static Access Memory) Array
Address 0x3F 8000 0x3F 97FF 0x3F 9800 0x3F BFFF 0x3F C000 0x3F FFFF Access Symbol Reserved SRAM_A Array Bytes) SRAM_B Array Bytes) Register Size Reset
MOTOROLA A-22
MPC555 INTERNAL MEMORY Rev. January 1999
MPC555 USER'S MANUAL

Other recent searches


TMS320C28x - TMS320C28x   TMS320C28x Datasheet
SPS-93120FG - SPS-93120FG   SPS-93120FG Datasheet
SN74LV10A - SN74LV10A   SN74LV10A Datasheet
SN54LV10A - SN54LV10A   SN54LV10A Datasheet
SMA511 - SMA511   SMA511 Datasheet
SFF-8011 - SFF-8011   SFF-8011 Datasheet
ATA-2 - ATA-2   ATA-2 Datasheet
PG12FBUSV - PG12FBUSV   PG12FBUSV Datasheet
AO6604 - AO6604   AO6604 Datasheet
AO6604L - AO6604L   AO6604L Datasheet
A3141 - A3141   A3141 Datasheet
A3142 - A3142   A3142 Datasheet
UGS3140 - UGS3140   UGS3140 Datasheet
A3144 - A3144   A3144 Datasheet
UGS3120 - UGS3120   UGS3120 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive