CAS*/CS5 RAS*/CS4 ROW/CS2 COL/CS3 SWDEN* PREN

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CAS/CS5 RAS/CS4 ROW/CS2 COL/CS3 SWDEN* PREN

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CAS*/CS5
RAS*/CS4
ROW/CS2
COL/CS3
SWDEN*
PREN*
DBE0
DBE1
DBE2
DBE3
LACK* LIRQ* LDEN*
R/W*
CY7C960 TQFP View
IRQ* DS1* DENIN1* LAEN
REGION3/CS2
REGION2 WRITE* REGION1 REGION0 DENIN*
DS0*
LEDO
DENO*
STROBE
ABEN*
IACK*
DTACK*
Figure 3-8. CY7C960 Assignment (TQFP)
3.3.1
VMEbus Signals
AM[5:0] VMEbus Address Modifier
Input: Output:
Signals AM[5:0] VMEbus Address Modifier inputs. These input signals used decode VMEbus transaction type. CY7C960 provides support predefined user defined VMEbus Address Modifiers.
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SYSRESET*
IACKOUT*
IACKIN*
LEDI
LADI
VMEbus Address Strobe
Input: Output: Active:
Address Strobe VMEbus signal that informs VMEbus slaves that valid address VMEbus. This signal used CY7C960 qualify VMEbus Address Modi fiers AM[5:0] REGION[3:0] inputs determine slave cycle should performed.
DS0*, DS1* VMEbus Data Strobe
Input: Output: Active:
DS0* DS1* VMEbus Data Strobe inputs. These signals inform CY7C960 that either address broadcast data phase VMEbus cycle begun. These nals conjunction with VMEbus LWORD* LA[1] signals encode data transfer width number bytes, through This information necessary enable appropri CY7C964 data bytes.
IRQ* VMEbus Interrupt Request
Input: Output: Drive: Active:
IRQ* signal driven CY7C960 indicate that local interrupt request signal active. IRQ* should connected VMEbus interrupt request nals IRQ[7.1]* order implement standard VMEbus interrupt requester. This signal also used, following power reset, part configuration protocol using VMEbus load device configuration registers. this case shall connected VMEbus IRQ2*.
IACK* VMEbus Interrupt
Input: Output: Active:
IACK* signal further qualifies VMEbus address transaction. this signal serted CY7C960 decodes VMEbus address transaction Interrupt Acknowl
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edge cycle. During interrupt acknowledge cycle CY7C960 will match three bits VMEbus address (A[3:1]) against user programmed internal level. levels match, IACKIN* received active, VMEbus interrupt pending from device, then VMEbus interrupt acknowledge completed enabling vector onto data bus. This vector user defined, enabled using LDEN* signal. CY7C960 assumes that interrupter, hence responds interrupt acknowledge cycles without regard size STATUS/ID requested. VMEbus interrupt pending IACKIN* asserted device this VMEbus address cycle will disre garded.
IACKIN* VMEbus Interrupt Acknowledge
Input: Output: Active:
IACKIN* signal informs CY7C960 that other stream (daisy chain) VMEbus device responded VMEbus Interrupt Acknowledge cycle. When IACKIN* serted CY7C960 during VMEbus Interrupt Acknowledge, cycle device deter mines VMEbus interrupt pending same level being acknowledged. CY7C960 generates local interrupt acknowledge cycle respond pending inter rupt. local interrupt pending device asserts IACKOUT*, passing chain next interrupter VMEbus backplane.
IACKOUT* VMEbus Interrupt Acknowledge
Input: Output: Drive: Active:
CY7C960 asserts IACKOUT* signal during VMEbus interrupt acknowledge cycles there VMEbus interrupt pending device, VMEbus interrupt level being acknowledged does match that being requested CY7C960.
SYSRESET* VMEbus System Reset Input
Input: Output: Active:
SYSRESET* input CY7C960 halts local VMEbus operations causes device reinitialize internal register bits. This reinitialization either performed
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reading external serial PROM Initialization Master VMEbus. When SYSRESET* goes Low, outputs from CY7C960 become three state until first rising edge input.
WRITE* VMEbus Write Input
Input: Output: Active:
VMEbus WRITE* input encodes type VMEbus data cycle progress. This asserted when VMEbus WRITE operation progress. During such transaction, VMEbus address decodes properly, CY7C960 responds asserting local signal performing appropriate local cycle.
DTACK* VMEbus Data Acknowledge Output
Input: Output: Drive: Active:
DTACK* signal asserted CY7C960 when valid VMEbus transaction progress transaction remained valid proper length time. asser tion this signal informs VMEbus Master that slave either accepted data during write operations sourced data during read operations. This signal scinding output.
3.3.2
Local
Signals
LWORD* Long Word
Input: Output: Active:
This local version VMEbus signal LWORD* which, when active, indicates either transfer over VMEbus. VMEbus LWORD* signal nected directly A[0] bidirectional least significant CY7C964. LA[0]
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bidirectional least significant CY7C964 turn connected directly LWORD input CY7C960. This signal conjunction with DS0*, DS1*, LA[1] signals encode data transfer width number bytes, through This information necessary enable appropriate CY7C964 data bytes.
LA[1] PCLK Local Address Signal Init PROM Clock
Input: Output: Drive:
During CY7C960 initialization this sources receives serial PROM compatible clock. state this sampled immediately after power reset period expires. sampled High, then CY7C960 will source PROM clock signal (PCLK) during local initialization. sampled then CY7C960 will accept external clock which will advance data through internal serial chain. CY7C960 receives High data PDATA during first initialization clock cycle, this signal becomes LA[1] device expects configured from VMEbus. device receives data PDATA during first initialization clock cycle, CY7C960 will either source receive clock from this proceed load configura tion data from local serial data source. After initialization, this carries local address signal LA[1].
LA[2] PDATA AM[0] Local Address Init PROM Data Local code
Input: Output: Drive:
During device initialization CY7C960 receives serial data stream this signal: local serial method used, then serial configuration data comes from PROM; VMEbus method configuration used, then VMEbus A[2] signal used carry serially encoded configuration data, appropriate CY7C964 enabled CY7C960 provide this data PDATA. After system initialization this signal becomes local bidirectional address signal LA[2] LA[2]/AM[0] depending programming. CY7C960 programmed LA/AM multiplexing then VMEbus signals AM[5:0] will driven LA[7:2] CY7C960 between VMEbus accesses. rising edge
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LADI used local external decoding circuitry latch codes before this changes from providing information providing information. CY7C960 will assert LAEN after LADI rises which disables CY7C960 LA[7:1] drivers same time enables CY7C964 LA[7:0] drivers. section 3.5.3.1.
LA[7:3] AM[5:1] Local Address Signals
Input: Output: Drive:
LA[7:3] make remainder local bidirectional address bus. CY7C960 only sources local addresses during VMEbus block transfer operations. During single cycle interrupt acknowledge accesses lowest order address byte sourced from respective CY7C964. CY7C960 begins source least significant byte local address infor mation starting with second cycle VMEbus block transfer. This done increment local address proper amount, depending VMEbus word size transfer. CY7C960 programmed LA/AM multiplexing, then VMEbus signals AM[5:0] will driven LA[7:2] CY7C960 between VMEbus accesses. rising edge LADI used local external decoding circuitry latch codes before this changes from providing information providing information. CY7C960 will assert LAEN after LADI rises which disables CY7C960 LA[7:1] drivers same time enables CY7C964 LA[7:0] drivers.
PREN* Serial PROM Enable
Input: Output: Drive: Active:
PREN* signal enables serial initialization PROM. CY7C960 asserts this signal when receives active SYSRESET* input from VMEbus after power reset period. PREN* signal remains active duration CY7C960 local initializa tion cycle.
LDEN* Latch Data Enable
Input: Output:
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Drive: Active:
LDEN* signal used conjunction with PREN* signal select several potential latched data sources. During initialization sequence, PREN* LDEN* both driven time that Address Mask Compare registers CY7C964s loaded. When LDEN* driven when PREN* High, this signifies that interrupt vector enabled onto local interrupt acknowledge cycle progress.
RAS* CS[4] Address Strobe Chip Select
Input: Output: Drive: Active:
Programmable
RAS*/CS[4] output CY7C960 dual purpose whose function selected during initialization period. When configured this output controls dress strobe function DRAM. general purpose configuration, this output user programmable chip select.
CAS* CS[5] Column Address Strobe Chip Select
Input: Output: Drive: Active:
Programmable
CAS*/CS[5] output CY7C960 dual purpose whose function selected during initialization period. When configured this output controls column address strobe function DRAM. general purpose configuration, this output user programmable chip select.
CS[2] Address Enable Chip Select
Input: Output: Drive: Active:
Programmable
ROW/CS[2] dual purpose signal whose function selected during initialization period. When configured this output acts address enable signal, used
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conjunction with RAS. general purpose mode, this output becomes user grammable chip select. When configured DRAM operation, CY7C960 still provides CS[2] output from another pin: CS[2]/REGION[3].
CS[3] Column Address Enable Chip Select
Input: Output: Drive: Active:
Programmable
COL/CS[3] dual purpose signal whose function selected during initialization period. When configured this output acts column address enable signal, used conjunction with CAS. general purpose mode, this output becomes user programmable chip select.
DBE[3:0] Data Byte Enables [3:0]
Input: Output: Drive: Active:
Programmable
These four signals provide byte enables local circuitry, either DRAM I/O. size VMEbus data transaction decoded CY7C960 from state DS0*/DS1*/LWORD*/A1 VMEbus signals, appropriate byte enable signals driven. active state signal user programmable during configuration. DBE3 represents LD[7:0]. DBE0 represents LD[31:24].
CS[1:0] Chip Select [1:0]
Input: Output: Drive: Active:
Programmable
These signals chip select outputs that available whether CY7C960 config ured DRAM operations. behavior these pins determined during figuration.
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R/W* Read/Write Input: Output: Drive:
R/W* local signal that determines cycle progress read operation write operation. CY7C960 asserts this signal during write operations.
LIRQ* Local Interrupt Request Input: Output: Active:
LIRQ* local interrupt request input.
Asserting this active input causes
CY7C960 assert VMEbus IRQ* output signal.
LACK Local Data Acknowledge/Local Hold Input: Output:
LACK input used acknowledge local data transfer cycle. Asserting this active signal causes DTACK* driven VMEbus. user assert this signal continuously, which causes CY7C960 time data cycle acknowledgements: user withhold assertion LACK order handshake acknowledge.
CY7C960 been programmed local hold mode, then LACK also used keep CY7C960 local bus. LACK deasserted after LADI falls between
VMEbus operations then CY7C960 will three state local drivers place itself stand until LACK asserted again.
REGION[2:0] Local Slave Decode Inputs Input: Output:
REGION[2:0] inputs user programmable address decode inputs. External decod circuitry, such CY7C964's, drives these signals when VMEbus addresses match user defined values. CY7C960 uses these signals together with REGION[3] codes determine reaction VMEbus cycle. (See section 3.9.1, Region Mapping.)
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CS[2] REGION[3] Chip Select Local Slave Decode Input
Input: Output: Drive: Active:
Programmable
CS[2]/REGION[3] signal user configurable modes operation.
CY7C960 configured operation, becomes REGION[3] input, provid another decode input, total CY7C960 configured DRAM, then only three REGION inputs required, becomes CS[2]. (See section 3.9.1, Region Mapping.)
Clock Input
Input: Output:
CY7C960 will operate with input frequency less than MHz. However, VMEbus will suffer performance this clock slower. output events occur rising edge clock input. internal states timed this signal.
3.3.3
Local Buffer Control Signals
Local Data Select
Input: Output: Drive:
During multiplexed data VMEbus transactions this used CY7C964s select internal registers. During initialization, this signal determines which mask
compare registers loaded within CY7C964s.
LADI Latch Address
Input: Output: Drive:
Latch Address signal controls address latches within CY7C964 that contain address information written local bus. LADI signal asserted shortly after
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CY7C960 detects assertion VMEbus signal used externally latch local codes LA[31:1] values. system designs that CY7C960 with CY7C964s this signal directly connect LADI inputs CY7C964s.
LAEN Local Address Enable
Input: Output: Drive: Active:
Programmable
Local Address Enable signal enables local address output buffer within CY7C964s. state this sampled immediately after power reset period pires. sampled High then LAEN signal will active Low. sampled then LAEN signal will active High. system designs that CY7C960 with four CY7C964s, this signal connected only least significant device active High default weak internal pull down resis tor. LAEN inputs other three devices tied High, controlled external logic allowing multi port local accesses. This convention allows CY7C960 disable address from least significant CY7C964 that source least significant byte local address during block transfer operations.
LEDI Latch Enable Data
Input: Output: Drive:
LEDI designed control transparent latch type used within CY7C964. this output Low, data from VMEbus flows through local data bus. Asserting this signal High closes latch, maintaining data present rising edge. System designs that CY7C960 with CY7C964s this output directly associated LEDI input CY7C964s.
LEDO Latch Enable Data
Input: Output: Drive:
LEDO designed control transparent latch similar type used within CY7C964. this output Low, data from local data flows through VMEbus.
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Asserting this signal High closes latch, maintaining data present rising edge. System designs that CY7C960 with CY7C964s this output directly asso ciated LEDO input CY7C964s.
DENO* Data Enable
Input: Output: Drive: Active:
DENO* output controls VMEbus data drivers CY7C964s. When data driven onto VMEbus, level driven from this output. High level this output signifies that VMEbus drivers high impedance. This should nected DENO* pins CY7C964s.
DENIN*, DENIN1* Data Enable Signals
Input: Output: Drive: Active:
DENIN* DENIN1* outputs control latching sections VMEbus data. These control signals association with local SWDEN* signal allow VMEbus transfer widths transmitted local peripherals. These signals intended connected DENIN* DENIN1* inputs CY7C964s enable local drivers. section 3.6.3, Swap Buffer Control.
ABEN* Address Enable
Input: Output: Drive: Active:
ABEN* VMEbus address enable signal. CY7C960 asserts this signal during VMEbus block transfer read operations, enable second longword data information onto VMEbus. This output should connected corresponding ABEN* inputs four CY7C964s. pull resistor also needed this proper operation.
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STROBE CY7C964 Strobe Control
Input: Output: Drive:
STROBE output allows CY7C960 control register loading CY7C964s. Loading CY7C964 Address Mask Compare registers requires assertion STROBE signal, with signal providing signal that determines which registers, mask compare, loaded. STROBE output performs this function during system initialization. Designs that four companion CY7C964s should this output associated STROBE input four CY7C964 devices.
CY7C964 Control
Input: Output: Drive:
output informs external hardware that VMEbus block transfer operation progress. When VMEbus address decode cycle valid this signal asserts High. Designs that four companion CY7C964s should this output associated input four CY7C964 devices.
SWDEN* Swap Data Enable
Input: Output: Drive: Active:
SWDEN* signal controls local swap buffer. This buffer used move data proper section local data during appropriate byte word width transfers. CY7C960 local ordering convention matches that MC68020. This signal asserts when byte word width transfer, which always moved D[15:0] VMEbus, must D[31:16] local data bus. (See section 3.6.3, Swap Buffer Control.)
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