3.11.1 Introduction CY7C961 CY7C960 Slave VMEbus Interface Contro
|
|
|
Top Searches for this datasheet
CY7C961 Description
3.11.1 Introduction
CY7C961 CY7C960 Slave VMEbus Interface Controller with addition master block transfer capability. Full featured Slave boards built, using CY7C961, that offer flexible Master block transfer facility bursting data across VMEbus. CY7C961 receive instructions from VMEbus Master program ming registers locally. CY7C961 interprets instructions then moves data cordingly VMEbus Master. This optimizes performance utilization. CY7C961 true superset CY7C960. Signal pins have been added control CY7C964 functions. Unidirectional VMEbus pins have been changed bidirection additional signals have been provided complete master interface, such data port VMEbus requester signals. VMEbus Slave, CY7C961 behaves respect like CY7C960. more pins, master block transfer facility, cause addition BBSY*) full lock cycle support. From system perspective, this CY7C961 master block transfer capability viewed channel which resides slave card, controlled dual ported chip register file. possible program channel from VMEbus from local side interface, both. Once programmed, CY7C961 acquires VMEbus transfers data user selected protocols. Circuitry local side CY7C961 sees same control signals were described CY7C960. example, REGION inputs CY7C961 driven exter address decoder. address decoder sits local address bus, which driven from CY7C964s. local memory involved data transfer enabled through outputs DRAM control signals from CY7C961, they must config ured correctly REGION inputs being driven.
3-96
CY7C961 Description
LAEN321
DENIN1*
REGION[2:0] SELECTLM
10010011011 00101101100
AM[5:0 REGION/ 11000110101 CY7C964 Controller
VMECNT
STROBE
DENIN*
DENO*
MWB*
ABEN
LEDO
LADO
LAEN
BLT*
LEDI
LADI
Local Address Controller
LA[7:0]
00000001000 able 10101011111 11000111001 10110011000 00000000000 Power
Reset Generator
SYSRESET*
Channel Registers Timing Generator
LD[7:0]
DS0* DS1* DTACK* WRITE* BBSY* BERR* BGIN* BGOUT* Control Interface
10010011011 00101101100 Chip 11000110101 Select 00000001000 Output Pattern 10101011111
able
CS[2:0]
Controller
Data Byte Data Byte Lane Decoder Enable Controller
DBE[3:0] LBERR* LACK
Refresh Controller IRQ* IACK* IACKIN* IACKOUT* Interrupt Interface LOCK Controller DRAM Controller Local Control Circuit LDEN* PREN* SWDEN* R/W*
CAS*
RAS*
LIRQ
Figure 3-34. CY7C961 Block Diagram
This implies that VCOMP* outputs from CY7C964s cannot form part address decoder master operations, because they looking local address, VMEbus address, which definition must pointing somewhere other than
CY7C961's address space.
Figure 3-34
shows block diagram CY7C961. very similar CY7C960
block diagram (see Introduction), with addition some CY7C964 control signals, nals needed support VMEbus Master ransactions, other minor changes.
3.11.2 CY7C961 Lock Cycle Support
3.11.2.1 Overview
Lock commands Address Only Cycles With Handshake (ADOH) cycles that used lock other port(s) multiported resources, where port VMEbus. Each
3-97
CY7C961 Description
Slave's resource that addressed with lock command lock other accesses that resource. lock command signifies start locked sequence VMEbus cycles which ends with current VMEbus Master's tenure. CY7C961 allows locked cycles decoded, drives local lock indicator while ensuing VMEbus locked sequence progress.
3.11.2.2 Description
Each lock commands (A16, A24, A32, A40, A64) consists address phase which presented VMEbus handshaken targeted Slave. CY7C961 programmed decode lock commands decode regions. combina tion five lock commands enabled that region, only lock indicator signal provided. When lock command decoded, CY7C961 drives indicate beginning locked VMEbus sequence. lock indication will maintained long BBSY* remains asserted CY7C961. decoded lock cycle will cause chip selects byte enables become active. decoded lock cycle will interfere with slave accesses CY7C961. various signals associated with LOCK cycles. signal active during block transfer register accesses during CY7C961 block transfers. indicates default lock condition during master block transfer. This should considered when designing local resource lock control circuitry which used. lock default needed during master block transfers, CY7C961 signal used disable lock during master block transfers.
Figure 3-35 shows
3.11.3 CY7C961 Master Block Facility
3.11.3.1 Overview
CY7C961 Master Block Facility provides block transfer demand" capability slave cards built around Cypress CY7C961/CY7C964 chip set. This facility allows control writing short series commands CY7C961/CY7C964 chip set, telling much data move, where from, where what transfer protocol while moving Blocks moved over VMEbus indivisible single cycles BLTs. protocol menu includes D16, D32, MD32, D64. A16, A24, A32, A40,
3-98
CY7C961 Description
address spaces specified. Burst lengths from bytes megabytes requested. Eight registers accessible from VMEbus local side interface make facility simple configure simple control. facility busy sema phore, VMEbus Interrupt completion feature with programmable statusID byte, built requester grant daisychain.
BBSY*
MWB*
LOCK Indicator remains until deasserted after been deasserted.
A64/D16
A24/Serial
VMEbus locked sequence
WRITE*
VALID
etc.
VALID
DS0*
DS1*
DTACK*
LA10 LA12 LA14 LA16 LA18 LA20 LA22
LA24
REGION
DECODE delay
LADI
VALID
VALID
etc.
2425
VALID
LEDI
SWDEN*
Block transfer DRAM REFRESH BURST
RAS*
CAS*
LACK
DENIN*
"10"
"10"
R/W*
Figure 3-35. LOCK Cycle Timing
3-99
CY7C961 Description
expected that system designer will choose either local programming channel VMEbus programming design decode other support circuitry based that choice. There nothing design CY7C961 prevent dual porting control registers, dual porting, like multi master VMEbus control requires poll CY7C961 control register semaphore and/or added complexity hardware software design.
3.11.3.2 Master Block Transfer Control from VMEbus
control master block facility register access. Eight registers designed accessed over VMEbus single cycle masters. order reach Master Block facility, VMEbus address must cause SELECTLM* signal valid GION vector asserted CY7C961. Refer register access detail. assertion SELECTLM* blocks local response CY7C961. Instead, internal gating external buffer control signaling appropriate register access speci
Figure 3-36
WRITE* DS0* DS1* DTACK* LADI REGION SELECTLM DENIN LEDO
VALID
VALID
A[4:2]="010" TLM1
A[4:2]="010" TLM1
LA[4:2]="010"
LA[4:2]="010"
VALID
VALID
TLM1
TLM1
Chip Select Response
Figure 3-36. Control Register Access from VMEbus
3-100
CY7C961 Description
fied LA[4:2] substituted. CY7C961 asserts DTACK* valid register accesses BERR* error access attempted. Eight registers defined, selected LA[4:2].
3.11.3.3 Master Block Transfer Control from Local Side Interface
control master block facility register access. Eight registers designed accessed directly through control LA[4:2], LD[31:0], R/W*, SELECTLM*. local holdoff" feature CY7C961 must enabled CY7C961 must holdoff" state before register access begun. (See section 3.5.4 complete descrip tion Local Holdoff.") order reach Master Block facility, LA[4:2] assertion SELECTLM*. register write cycles, LD[31:0] must also SELECTLM*. response CY7C961 self timed acknowledge handshake provided. SELECTLM* must asserted minimum (eight periods) LA[4:2], R/W*, LD[31:0] must driven valid until SELECTLM* deasserted. register reads, CY7C961 drives LD[7:0] clocks after SELECTLM* sampled asserted three states LD[7:0] clock after SELECTLM* sampled deasserted. Refer
Figure 3-37 Local Register access signaling.
CY7C961 provides control signals CY7C964 control loading registers inside device operations such establishing local starting address starting address, both which could quantities stored inside CY7C964s.
LADI
LACK
VALID
LAEN
LA[4:2]
Register Address
LD(write)
DATA CY7C961/CY7C964
SELECTLM
LD(read)
DATA from CY7C961
LBERR
Figure 3-37. Control Register Local Access
3-101
CY7C961 Description
illegal register access attempted, CY7C961 will signal driving LBERR* within clocks after SELECTLM* asserted. LBERR* deasserts clock after SELECTLM* sampled deasserted.
3.11.3.4 Programming Master Block Facility
general, programming very simple. First semaphore must read. This register read unlocks facility. Next, values written Transfer Length, Transfer Type, Upper Address (optional), Master Block StatusID (optional). These parameters need refreshed each time facility used. After that, Starting Address writ ten, then Local Starting Address This last register write operation starts block transfer. CY7C961 will assert and, upon being granted VMEbus, move data until transfer length exhausted. Note that CY7C961 programmed through initialization stream release request VMEbus every byte boundary transfer progresses. This behavior useful providing VMEbus access high priority traffic interleaved with transaction. more than VMEbus master control block transfer facility, facility dual ported between local more VMEbus masters, Semaphore Test register polled master determine facility idle" busy." polling result idle", that register read sets semaphore busy", eliminating need read modify operation. semaphore written idle." semaphore changed register write, this operation always acknowledged with error sponse CY7C961. semaphore reset CY7C961 block transfer completion. another block transfer requires minimum three register accesses, namely, read Semaphore Test Set, write Starting Address, write Local Starting Address course parameters read (with some limitations) written before writing register. Once Local Starting Address register written, register write attempts greeted with error acknowledge, cancellation eration, reset semaphore. Register reads always permitted. CY7C961 equipped with BERR* LBERR* inputs which used interrupt transfer time after started (BBSY* asserted). consideration
3-102
CY7C961 Description
timing BERR* LBERR* assertion with respect progress needs given. These signals provide mechanism aborting transfers favor high priority VMEbus traffic.
Table 3-11. Master Block Transfer Control Registers
LA[4:0] Register Function
000xx 001xx 010xx 011xx 100xx 101xx 110xx 111xx
Semaphore Test (read only)
Transfer Length Multiplier (TLM0) Transfer Length Multiplier (TLM1) Transfer Type Local Starting Address Starting Address A40/A64 Upper Address
Master Block StatusID Interrupt Enable
3.11.3.5 Register Definitions
following descriptions apply equally VMEbus register local register access, written from VMEbus perspective. Local access occurs context local holdoff" previously described, error response LBERR* substituted BERR*.
3.11.3.5.1 Semaphore Test (read only)
Location 000xx semaphore test set. read cycle. CY7C961 responds with current value semaphore. Master Block resource CY7C961 idle, this read will return logic which reflected data bus. This register read causes semaphore busy. CY7C961 will respond additional register accesses. subsequent read semaphore will return logic LD[0] D[0] indicating that block transfer resource busy." semaphore cleared CY7C961 upon completion block transfer when illegal combination register values held when transfer attempted. interrupt completion feature enabled, semaphore clear delayed until interrupt generated block transfer completion serviced. When BERR* received during block transfer, transfer terminates semaphore cleared. interrupt completion feature enabled, interrupt will signaled termination semaphore clear delayed until that interrupt serviced.
3-103
CY7C961 Description
write location 000xx will cause CY7C961 drive BERR* clear sema phore. access seven other defined registers attempted before sema phore busy" state, CY7C961 will BERR* those attempts semaphore will remain idle state. CY7C961 drives status conditions LD[6:1] passed through D[6:1] VMEbus during semaphore read. normal value these status bits logic logic indicates condition which would prevent block transfer from starting (cause CY7C961 BERR write Local Starting Address GO). semaphore Test Status functions.
Table 3-12. Semaphore Test Status Bits
Table 3-12 summarizes
Status Error Indication
Semaphore. (Logic idle)
Master Block interrupt pending.
Transfer Length Multiplier registers Transfer Type undefined.
Data size incompatible with local starting address. starting address been updated.
Address alignment violated multiplexed data BLT. BERR* LBERR* asserted during transaction.
logic means that interrupt completion enabled block transfer terminated completed, interrupt signalled termination/completion been serviced VMEbus interrupt handler. always logic this case since semaphore must state busy." attempt access other registers block trans facility while logic will BERRed CY7C961. This status will clear with pending interrupt. logic indicates that both registers Transfer Length Multiplier1 Transfer Length Multiplier0 contain values zero. transfer length multiplier must nonzero. clear this status bit, nonzero value must written either Transfer Length Multiplier register. logic indicates value transfer type register undefined. clear this condition, valid code must written Transfer Type register. (See Transfer Type below.)
3-104
CY7C961 Description
logic means that either local starting address starting address compatible with programmed data size. This error condition amounts specify unaligned starting addresses block transfer. example, local starting address with 0x03 specified with data size would result unaligned transfer request. Similarly, starting address 0x02 specified operation would start unaligned address. Either condition would cause this status logic This status computed current values VMEbus local starting address Since Local Starting Address register written time block transfer started, alignment error local starting address will always cause CY7C961 assert BERR*. subsequent read Semaphore Test will indicate error this status bit. logic indicates violation restriction placed starting address when transaction type multiplexed data. restriction that starting address [7:0] equal local starting address [7:0]. This restriction addition address alignment requirement described with respect status above. restriction applies expressly transfer type codes: 0110011x", 0110111x", 0111010x", 0101011x", 0101111x", 0111111x". This status computed current values VMEbus local starting addresses. Since Local Starting Address register written time block transfer started, violation this restriction created when local starting address written causing CY7C961 assert BERR*. subsequent read Semaphore Test will indicate error this status bit. logic indicates that starting address been written since last master block transfer started. This status cleared writing Start Address.
3.11.3.5.2 Transfer Length Multiplier(1
registers, Transfer Length Multiplier1 Transfer Length Multiplier0 hold respec tively transfer length multiplier parameter. transfer length block transfer bytes computed multiplying transfer length multiplier block length factor that transfer type. block length factor function transfer data size shown
Table 3-13.
3-105
CY7C961 Description
Table 3-13. Transfer Length Calculation
Data Size Block Length Factor TLM1,TLM0 Transfer Length
Bytes Bytes Bytes
TLM[15:0] TLM[15:0] TLM[15:0] TLM[15:0]
BYTES BYTES BYTES BYTES
Bytes
example, TLM1= TLM0 data size (specified Transfer Type register), then transfer length block transfer would 1030 65,920 bytes. number data cycles always times transfer length multiplier, data bytes transferred obviously proportional width transaction. transfer length multiplier registers read/write with data sent/received LD[7:0] reflected D[7:0] VMEbus. Semaphore Test status word will logic both TLM1and TLM0 This error condition which will block transfer start. Both registers cleared after power SYSRESET*.
3.11.3.5.3 Transfer Type
Transfer type register specifies which possible block transfer operations performed. user select from among A40BLT, D64MBLT, D32BLT, D16BLT, D8BLT, single cycle block move options. codes shown valid contents transfer type register:
Table 3-14. Transfer Field Block Transfer Operations
Table 3-14
Transfer ype[7:0]
AmCode
Block Transfer Description
20,21,22,23,24,25
supervisory block transfer (D8BLT D16BLT D32BLT) supervisory program access D32) supervisory data access D32) supervisory block transfer (MBLT)
A8,A9,AA,AB,AC,AD B0,B1,B2,B3,B4,B5 66,67 28,29,2A,2B,2C,2D
nonprivileged block transfer (D8BLT D16BLT D32BLT) nonprivileged program access D32) nonprivileged data access D32) nonprivileged block transfer (MBLT)
3-106
B8,B9,BA,BB,BC,BD A0,A1,A2,A3,A4,A5 6E,6F
Table 3-15. Transfer Field Transfer [2:1]
Table 3-14. Transfer Field
7E,7F
48,49,4A,4B,4C,4D
5E,5F
D8,D9,DA,DB,DC,DD
D0,D1,D2,D3,D4,D5
18,19,1A,1B,1C,1D
56,57
C8,C9,CA,CB,CC,CD
C0,C1,C2,C3,C4,C5
10,11,12,13,14,15
98,99,9A,9B,9C,9D
90,91,92,93,94,95
74,75
40,41,42,43
Transfer ype[7:0]
with data moving from CY7C961interface VMEbus slave. master read with data moving CY7C961 interface, logic specifies master write Transfer Type register specifies block transfer data direction. Logic specifies undefined transfer type will prevent start block transfer. data size. Illogical combinations will reported Semaphore Test status defines this Transfer Type field. CY7C961 checks consistency between transfer type Bits [2:1] Transfer Type register specify data size block transfer.
Block Transfer Data Size AmCode
Data Size
Block Transfer Operations
block transfer (MBLT)
block transfer (D8BLT D16BLT D32BLT)
nonprivileged block transfer (MBLT)
nonprivileged data access D32)
nonprivileged program access D32)
nonprivileged block transfer (D8BLT D16BLT D32BLT)
supervisory block transfer (MBLT)
supervisory data access D32)
supervisory program access D32)
supervisory block transfer (D8BLT D16BLT D32BLT)
nonprivileged access D32)
supervisory access D32)
block transfer (MD32)
block transfer (D8BLT D16BLT)
3-107
Block Transfer Description
(continued)
CY7C961 Description
Table 3-15
CY7C961 Description
transfer type register read writen with data transmitted LD[7:0] reflected D[7:0] VMEbus. Illegal codes cause block transfer abort when transac tion received. Both undefined transfer type fields illogical transfer type data size
combinations will BERR when Local Starting Address written.
3.11.3.5.4 Local Starting Address
Local starting address register used write local block address used block transfer. This address bits address information provided data when register written. Local starting address loaded directly into CY7C964's local address counters CY7C961 local address register. read local starting address will yield only starting address LD[7:0] reflected D[7:0] data bus.
CY7C961 signal BLT* driven periods load local address into CY7C964s from bus. value rising edge BLT* stored CY7C964 counter Refer
Figure 3-38
control function this register activated only writes register. causes start block transfer signaling CY7C961 requester take VMEbus begin transfer. Once CY7C961 acquires VMEbus, will release VMEbus until block transfer finishes terminated BERR* during transfer attempt. BBSY* released when transfer length count exhausted, VMEbus boundary crossings. write register after transaction will BERRed CY7C961, block move aborted, semaphore reset.
3.11.3.5.5 Starting Address
Starting Address register used write VMEbus block address used block transfer. This address bits address information written data CY7C961. actually stored latch CY7C964s address also captured CY7C961 facilitate counting address boundary. read VMEbus Starting Address will yield only starting address LD[7:0] reflected D[7:0] data bus. Note that this specifier true byte address. CY7C961 takes care VMEbus LWORD* DS1*/DS0* encod ing. This register must written each time block transfer executed. Sema phore status register will indicate when starting address been
3-108
CY7C961 Description
WRITE* DS0* DS1* DTACK* LAEN321
VALID
VALID
VALID LOCAL START ADDR
VALID BYTE0 BYTE1 BYTE2 BYTE3 BYTE4
Local Start Address latched rising edge
BLT* MWB* LADI REGION SELECTLM* DENIN* LEDO R/W* RAS* BBSY*
VALID VALID VALID VALID VALID VALID VALID
Figure 3-38. Local Starting Address Block Transfer Start Timing
updated. This requirement guarantees that CY7C964 CY7C961 will using same VMEbus starting address.
3.11.3.5.6 A40/A64 Upper Address
A40/A64 Upper Address register register residing either CY7C961 CY7C964. Instead, facility reading/writing extended address information exter hardware slave card that part CY7C961/CY7C964 interface. Latch enable signaling allows reading writing during register access well data
3-109
CY7C961 Description
enable during address broadcast block transfer runs. extensions supported. latch signal capturing extended address from local data (SELECTLM* LEDI) where LEDI CY7C961 output. active enable driving latched data onto local data (LDEN* MWB*). extended address increm ented, VCOUT* appropriate CY7C964 LADO used count enable clock respectively extended address counting. Refer Figure 3-39 signaling. latch signal designed latch bits upper address from LD[31:0] passed through interface from D[31:0] when Upper Address written. enable signal
WRITE* DS0* DS1* DTACK* LADI REGION SELECTLM*
UPPER ADDR VALID VALID LA[4:2] 110" LA[4:2] 110" A[4:2] 110" A[4:2] 110" VALID VALID
UPPER ADDR
UPPER ADDR
U.A.
Enable Upper Address LDEN* MWB* Latch Upper Address LEDI DENIN* LEDO R/W* RAS*
Chip Select Response (!SELECTLM LEDI) !(MWB+LDEN)
Figure 3-39. Upper Address Register Access Timing
3-110
CY7C961 Description
designed allow stored address read from VMEbus when Upper Data read, well enable stored address onto when master block transfer address broadcast requires
3.11.3.5.7 Master Block StatusID Interrupt Enable
Master Block status Interrupt Enable CY7C961 register which holds Master Block statusID byte. This register read written. Bits register will reflected statusID byte sourced CY7C961 when Master Block interrupt viced. controls enabling interrupt completion: logic enables interrupt completion. When interrupter status read handler, statusID indicates completion status. Logic means normal completion. Logic means abnormal termination (BERR* LBERR* received during block transfer). interrupter Release Acknowledge (ROAK) interrupter. interrupt completion enabled, CY7C961 will reset semaphore interrupt acknowledge. interrupt completion enabled, CY7C961 will reset semaphore with BBSY deassertion block transfer. Refer
Figure 3-40 Interrupter timing.
3-111
CY7C961 Description
IRQ* IACK* IACKIN* WRITE* VMECNT DS0* DS1* DTACK* MWB* LADI REGION LEDI DENIN* LEDO LACK RAS* R/W* BBSY*
A32/D32 supervisory program access
A_last-8
A_last-4
A_last
IRQ_level
LA_last-8
LA_last-4
LA_last
IRQ_level
Status/Id
Figure 3-40. Interrupter Timing
3-112
CY7C961 Description
3.11.4 Description Addendum
CAS*/CS5
RAS*/CS4
ROW/CS2
COL/CS3
SWDEN
PREN
DBE0
DBE1
DBE2
DBE3
R/W*
LACK LIRQ* LDEN* REGION3/CS2 BERR* VMECNT REGION2 WRITE* REGION1 REGION0 DENIN*
SELECTLM* LBERR* IRQ*
CY7C961 TQFP View
LAEN321 BBSY* DS1* LWORD* DENIN1* LAEN
DS0*
LEDO
LADO
BGOUT*
DENO*
ABEN*
following signals either additional redefined from, CY7C960 descrip tions Chapter 3.3.
3.11.4.1 VMEbus Signals
AM[5:0] VMEbus Address Modifier Input: Output: Drive:
Signals AM[5:0] VMEbus Address Modifier I/Os.
SYSRESET*
STROBE
IACKOUT*
DTACK*
BGIN*
IACK*
MWB*
IACKIN*
BLT*
LEDI
LADI
When inputs, these signals
used decode VMEbus data transaction type. CY7C961 provides support both predefined user defined VMEbus Address Modifiers. During master block transfers VMEbus codes driven these signal pins.
VMEbus Address Strobe Input: Output:
3-113
CY7C961 Description
Drive: Active:
Address Strobe VMEbus signal that informs VMEbus slaves that valid address VMEbus. This signal used CY7C961 qualify VMEbus Address Modi fiers AM[5:0] REGION[3:0] inputs determine valid slave cycle should formed. During master block transfers VMEbus driven this signal pin.
DS0*,DS1* VMEbus Data Strobes
Input: Output: Drive: Active:
inputs, these signals inform
DS0* DS1* VMEbus Data Strobes.
CY7C961 that data phase VMEbus cycle begun. These signals conjunction with VMEbus LWORD* (connected LA[0]) signal encode data transfer width number bytes, through This information necessary enable appropriate CY7C964 data bytes. During master block transfers VMEbus DS0* DS1* driven these signal pins.
WRITE* VMEbus Write Line
Input: Output: Drive: Active:
VMEbus WRITE* line specifies data direction VMEbus data cycle prog ress. this signal asserted then VMEbus WRITE operation progress. During such transaction, VMEbus address decodes properly, CY7C961 responds asserting local R/W* signal performing appropriate local cycle. During master block transfers, VMEbus WRITE* driven this signal indicating direction data transfer.
DTACK* VMEbus Data Acknowledge
Input: Output:
3-114
CY7C961 Description
Drive: Active:
DTACK* signal asserted CY7C961 when valid VMEbus transaction progress remained valid proper length time. assertion this signal informs VMEbus Master that slave either accepted data during write opera tions sourced data during read operations. This signal rescinding output. master block transfers, CY7C961 receives VMEbus data acknowledge from slave.
VMEbus Request
Input: Output: Drive: Active:
Signal VMEbus Request output. This output open collector with state sink current asserted CY7C961 when VMEbus required block transfer.
BGIN* VMEbus Grant
Input: Output: Active:
BGIN* VMEbus Grant signal. generated VMEbus arbiter signals that CY7C961 VMEbus. BGIN* BGOUT* signals form grant daisy chain.
BGOUT* VMEbus Grant
Input: Output: Drive: Active:
BGOUT* VMEbus Grant signal. driven CY7C961 response assertion BGIN* signal when CY7C961 does want VMEbus.
3-115
CY7C961 Description
BBSY* VMEbus Busy
Input: Output: Drive: Active:
BBSY* VMEbus busy signal. driven CY7C961 indicate VMEbus being used block transfer. When block transfer operation done, CY7C961 drives BBSY* High then three states signal. response decoded VMEbus lock cycles, CY7C961 monitors BBSY* determine when locked VMEbus sequence ending.
BERR* VMEbus Error
Input: Output: Drive: Active:
BERR* VMEbus error signal. driven CY7C961 cases. First, decoded slave accesses which attempt illegally configure CY7C961 block transfer cility will result BERR* acknowledge. Second, BERR* will signaled acknowledge slave block data cycle LBERR* sampled asserted time VMEbus DSA* ceived CY7C961. BERR* three stated deassertion VMEbus signals DS0* DS1*. CY7C961 monitors BERR* during master block transfer operation, truncating block transfer BERR* acknowledge detected. BERR* assertion will also signal locked VMEbus sequence.
3.11.4.2 Local Buffer Control Signals
BLT*
Input: Output: Drive: Active:
BLT* driven clock periods during block transfer register access Local start address GO." local starting address block transfer latched into CY7C964
3-116
CY7C961 Description
internal counters High going edge this signal. CY7C961 BLT* should connected BLT* each CY7C964 interface.
MWB*
Input: Output: Drive: Active:
MWB* driven CY7C961 during block transfer register access Local starting address GO." remains state throughout master block transfer except byte local boundaries. When byte local boundary crossed, MWB* will pulsed High clock period. High transition this pulse increments interface CY7C964 local block counters. MWB* deasserted completion block transfer. MWB* also signals VMEbus lock status. MWB* driven decode VMEbus lock cycle. deasserted when VMEbus lock sequence complete. CY7C961 MWB* should connected MWB* each CY7C964 interface.
LADO
Input: Output: Drive:
LADO pulsed High CY7C961 VMEbus byte boundaries during master block transfers. LADO driven High same time VMEbus data strobes asserted last cycle address page. LADO driven clock after DTACK* detected that cycle. High transition LADO increments VMEbus block counters interface CY7C964s. CY7C961 LADO should connected LADO pins interface CY7C964s EXCEPT connected VMEbus addresses A[7:1].
Input: Output: Drive: Active:
High
driven High CY7C961 beginning block transfer's VMEbus tenure. deasserted block transfer's VMEbus tenure. CY7C961
3-117
CY7C961 Description
should connected pins each CY7C964 interface. This signal serve complete indicator local control purposes.
VMECNT
Input: Output: Drive:
VMECNT clock signal driven CY7C961 LADO CY7C964 connected VMEbus addresses A[7:1]. This signal adjusts VMEbus block counter this CY7C964 source LWORD correctly block transfers. VMECNT also burst clocks this block counter $h00 cases where VMEbus block starting address aligned byte boundary. clock pulse width period.
LAEN321
Input: Output: Drive: Active:
High
LAEN321 driven four periods during block transfer register access starting address GO." High transition happens clock before High transition BLT*. LAEN321 used conjunction with BLT* MWB* place interface CY7C964s BLT_STATE. CY7C961 LAEN321 should connected LAEN pins interface CY7C964s EXCEPT connected VMEbus addresses A[7:1].
3.11.4.3 Local Signals
LD[7:0] Local Data Signals
Input: Output: Drive:
LD[7:0] make local bidirectional data bus. These pins should connected LD[7:0] interface CY7C964 connected VMEbus data D[7:0]. During block trans register accesses block transfer complete interrupt acknowledge accesses, data read from written CY7C961 this data port.
3-118
CY7C961 Description
SELECTLM* Select Load Master Signal
Input: Output: Active:
SELECTLM* chip select expressly accessing eight CY7C961 registers that trol block transfer facility. decoded VMEbus slave cycle which SELECTLM* also asserted will interpreted CY7C961 block transfer register access. SELECTLM* timing should imitate that REGION input.
LBERR* Local Error Signal
Input: Output: Drive: Active:
LBERR* three distinct functions. First, provides mechanism aborting transfers progress. time after register access completes, LBERR* asserted cause completion (with error status). interrupt completion abled, IRQ* will asserted within periods after LBERR* assertion. second function LBERR* error signaling mechanism slave block transfer. Each time VMEbus DSA* signal asserted CY7C961, state LBERR* signal sampled. asserted, that VMEbus cycle will receive BERR* acknowledge instead DTACK* acknowledge. third function LBERR* error acknowledge register accesses during local holdoff." LBERR* will asserted (driven low) CY7C961 indicate error condition during register access progress. Note that LBERR* always driving CY7C961 during local holdoff."
3.11.4.4 Master Block Transfer Performance
From perspective local timing, there difference between local signaling master slave accesses. master block facility uses same circuits same self timed acknowledge constants slave. Master block transfers sample REGION each byte boundary. This allows block transfer example, start SRAM region transparently cross hardware boundary into DRAM region. master block facility performance limits CY7C961 internal synchronous state machines. periods minimum required VMEbus data cycle master write
3-119
CY7C961 Description
operations, periods master read VMEbus data cycles. Local signaling limits transfer rates megabytes second, MD32 megabytes/second. performance block transfer limited VMEbus slave response, with ideal slave response making block read performance megabytes/second block write perfor mance megabytes second possible. These are, course, burst maximums.
tained block transfer rate will megabytes/second ideal slave with local cycles
block transfers using single cycle protocol will considerably slower than true block protocols because CY7C961 must increment CY7C964 after each data cycle. this represents period overhead. ransfer rate will exceed mega bytes/second. single cycle protocol will down around megabytes/second. single cycle will megabytes/second.
transfers, CY7C961 will cross address boundaries without releasing VMEbus unless Interleave function programmed serial stream. Address strobe will cycled address rebroadcast. BBSY does have early release mode, asserted throughout block transfer. D64MBLT will rebroadcast byte boundaries. single cycle accesses specified, block move will consist indivis ible packet single cycle transfers sufficient satisfy transfer length parameter, trans type dictating code used.
3-120
CY7C961 Description
3.11.5 Examples Block Transfers
WRITE* DS0* DS1* DTACK* REGION MWB* LDEN* LEDO DENIN* RAS* LACK R/W* BBSY*
A64/D64 MBLT
ADDRESS ADDR.
DATA0 DATA4
DATA8 DATA12
ADDRESS ADDR.
DATA16 DATA20
DATA24 DATA28
DATA32 DATA36
VALID (DRAM REGION) VALID LA12 LA16 VALID LA20 LA24 LA28 LA32 LA36 LA40 LA44
UPPER ADD.
UPPER ADD.
Figure 3-41. A64/D64 MBLT Master Write
3-121
CY7C961 Description
WRITE* DS0* DS1* DTACK* REGION MWB* LDEN* LEDI DENIN* RAS* LACK R/W* BBSY*
A64/D64 MBLT BOUNDARY
ADDRESS ADD.
ADDRESS ADD.
VALID (DRAM REGION) VALID LA12 LA16 VALID LA20 LA24 LA28 LA32 LA36
UPPER ADD.
UPPER ADD.
Figure 3-42.
CY7C961 A64/D64 MBLT Master Read Example
3-122
CY7C961 Description
WRITE* DS0* DS1* DTACK* REGION LDEN* LEDI DENIN* RAS* LACK R/W* BBSY*
A40/D16
ADDRESS ADDR.
VALID (DRAM REGION) VALID etc.
UPPER ADD.
etc.
Figure 3-43.
CY7C961 A40/D16 Master Read Example
3-123
CY7C961 Description
WRITE*
A32/D32 supervisory program access
Burst clock increments CY7C964
VMECNT DS0* DS1* DTACK*
incements
MWB* REGION LEDO LACK RAS* R/W* BBSY*
LA12 LA16 LA20
Figure 3-44. A32/D32 Single Cycle Write Example
3-124
Other recent searches
XN01507 - XN01507 XN01507 Datasheet
XN1507 - XN1507 XN1507 Datasheet
SN74HC4020 - SN74HC4020 SN74HC4020 Datasheet
SN54HC4020 - SN54HC4020 SN54HC4020 Datasheet
NJM2574 - NJM2574 NJM2574 Datasheet
NJM2574RB1 - NJM2574RB1 NJM2574RB1 Datasheet
MBR1070 - MBR1070 MBR1070 Datasheet
IN74HC573A - IN74HC573A IN74HC573A Datasheet
I2153 - I2153 I2153 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
