Another method loading VMEbus block transfer address counters exists w

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CY7C964 Alternate Initiation Operation VIC068A VIC64
Another method loading VMEbus block transfer address counters exists within CY7C964. This method been placed within section document because completely compatible with block transfer initiation cycle. CY7C964 determines source loading VMEbus master block transfer count monitoring arrival sequence MWB* BLT* signals. typical block transfer initiation cycles, assertion MWB* occurs prior assertion BLT*. VMEbus master block transfer counter loads from local address pins, LA[7:0], described within section 4.5.5. Reversing arrival order these signals changes operation device. This done system design time swapping BLT* MWB* inputs CY7C964. proper operation, these signals must continue operate same manner they VIC, even though they longer connected associated input pins CY7C964 which have same name. Swapping these signals device changes that VMEbus master block transfer counter loaded. this mode loads from local data latch other functions within device operate same manner described Chapter 4.5. Loading accomplished with local cycle similar cycles needed load mask compare registers. This cycle operates follows: driven High, (most likely this signal connected LA2), MWB* input CY7C964 driven Low, (this actually connected open collector BLT* output VIC), STROBE serted. local data should driven appropriate value address load into counters. STROBE deasserted data latched into within CY7C964. local address decode signal used assert MWB* CY7C964, (BLT* VIC), must three state open collector output. This signal must driv High will unable perform block transfers. normal master block transfer initiation cycle then performed, with minor excep tion. lower bits address LA[7:0] which controlled VIC, must contain
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CY7C964 Alternate Initiation Operation VIC068A VIC64
desired lower address. This needed because operates typical block transfer initiation mode. upper address LA[31:8] will ignored CY7C964s during initiation cycle. This mode operation allows VMEbus master block transfer address counters loaded independent VMEbus address. This advantages some designs, cannot used source single cycle transfer addresses. This limitation should consid ered while performing design analysis this mode.
Table 4-14. Master Block Transfer Local Address Counter Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Select register Load register Minimum pulse width
LDS, MWB* valid STROBE falling edge LD[7:0] valid STROBE rising edge STROBE
LDS=1, MWB*=0
Hold Hold
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-8. CY7C964 Alternate Operation Block Diagram
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