4.5.1 Overview CY7C964 general purpose interface device that prov
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CY7C964 Operation
4.5.1 Overview
CY7C964 general purpose interface device that provides seamless support entire family VMEbus interface controllers. part also suitable many other general purpose interface applications.
Figure
block diagram device,
showing array latches, multiplexers, counters.
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-3. CY7C964 Block Diagram
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CY7C964 Operation
This section document dissects high level block diagram into lower level func tional blocks. General operational timing information presented block block basis. This information provided designers wish implement generically trolled interfaces. tables show control signal logic sequence needed operate communicate with each functions. Timing parameters included, which reference switching characteristics listed later this document.
CY7C964 operation controlled combination external control signals internal state logic. Three internal asynchronous state control operating mode device. These bits referred BLT_STATE, BLT_INIT DUAL_P ATH. BLT_STATE during block transfer operations. block transfer initiation cycle generates rising edge BLT_INIT signal. DUAL_P signal output transparent latch within device that latches state LADO. These internal state bits must proper state communicate with internal logic device. functional tables include references these signals when their state required operation. designer must perform appropriate cycle device clear these latches needed prior desired functional cycle. internal latch signals other control signals that called within tables specific operation considered don't cares.
Table 4-5. Examples References Control Signals Within Functional Tables
Note Note Note
BLT_STATE=(/BLT*
/MWB*)+(BLT_STATE
(/BLT*+/MWB*+LAEN))
BLT_INIT=(/BLT_STATE DUAL_P ATH=(LADO
/BLT*
/MWB*)+(BLT_INIT
/BLT*
/MWB*
BLT_INIT)+(DUAL_P
/BLT_INIT)
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CY7C964 Operation
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-4. CY7C964 Block Diagram: Address Counters Address Multiplexers
4.5.2
Master Block Transfer Local Address Counter (C1)
Master Block Transfer Local Address Counter supplies local address LA[7:0] during master block transfer operations. This synchronous counter cascadable using LCIN*/LCOUT* daisy chain. counter powers uninitialized state must initialized predictable operation. counter loads from LD[7:0] when both MWB* BLT* control signals active (Low). enable counter onto LA[7:0], internal asynchronous latch (BLT_STATE) must Local Address Multiplexer must lect counter falling edge MWB* BLT* increments controls High, shown proper state increment counter. further information Local Address Multiplexer, section 4.5.3.
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Table 4-7, selected. internal latch multiplexer must also
CY7C964 Operation
Table 4-6. Master Block Transfer Local Address Counter Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Load counter
LD[7:0] valid falling edge MWB* LD[7:0] valid falling edge BLT*
BLT*=0, LAEN=0 MWB*=0, LAEN=0 LAEN=1, FC1=1, BLT_STATE=11 LAEN=1, FC1=1, BLT_STATE=11 LAEN=1, FC1=1, BLT_STATE=1 STATE LAEN=1, FC1=1, BLT_STATE=1 STATE LAEN=1, FC1=1, BLT_STATE=11 LAEN=1, FC1=1, BLT_STATE=11 LAEN=1, FC1=1, BLT_STATE=11 LAEN=1, FC1=1, BLT_STATE=11
Hold Hold Prop Prop Hold Hold Prop Prop Prop
Increment counter
MWB* falling edge LA[7:0] valid BLT* falling edge LA[7:0] valid LCIN* valid MWB* falling edge LCIN* valid BLT* falling edge
Counter carry terminal count
falling edge LCOUT* valid BLT* falling edge LCOUT* valid LCIN* valid LCOUT* valid
Minimum pulse widths
BLT* MWB*
4.5.3
Local Address Multiplexer (S5)
Local Address Multiplexer routes outputs counters signals LA[7:0]. local address counter carry chain LCIN*/LCOUT* also controlled this multiplexer. High, counter drives LA[7:0] LCIN*/LCOUT* visible/ driven respectively. When Low, drives LA[7:0] attached LCIN*/LCOUT* daisy chain.
Table 4-7. Local Address Multiplexer Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Select counter Select counter Select carry chain Select carry chain
rising edge LA[7:0] valid falling edge LA[7:0] valid rising edge LCOUT* valid falling edge LCOUT* valid
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Prop Prop Prop Prop
CY7C964 Operation
4.5.4
Slave Block Transfer Local Address Counter/Latch (C2)
Slave Block Transfer Local address counter provides functions: counter slave block transfer operations transparent address latch VMEbus slave operations. When latch control signal LADI held counter transparent mode: Logic levels present will flow through device inputs local address multiplexer controls multiplexer must select counter source LA[7:0]. Driving either LADI High exclusively latches data present A[7:0]. counter increments LCIN* Low, High, rising edge occurs LADI. contents counter/latch enabled onto local data when LADI High. Counter initialized power predictable opera tion counter should loaded prior use.
Table 4-8. Slave Block Transfer Local Address Counter/Latch Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Load counter
A[7:0] valid rising edge A[7:0] valid LADI rising edge
LADI=0 D64=0 D64=1, FC1=0 D64=1 D64=1, FC1=0
Hold Hold Prop Hold Prop
Increment counter
LADI rising edge LA[7:0] LCIN* active LADI rising edge
Counter carry terminal count Minimum pulse width
LADI rising edge LCOUT* LADI
4.5.5
Master Block Transfer VMEbus Address Counter (C3)
VMEbus Master Block Transfer Address stores increments VMEbus address during master block transfer operations. counter loads from LA[7:0] rising edge MWB* provided that internal asynchronous latch BLT_STATE set. contents counter enabled onto A[7:0] pins internal asynchronous latch bits BLT_STATE multiplexer appropriate state. Depending state DUAL_PATH, either rising falling edge LADO increments Counter uses VCIN*/VCOUT* counter daisy chain. This counter uninitialized power should initialized prior predictable operation.
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CY7C964 Operation
Table 4-9. Master Block Transfer VMEbus Address Counter Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Load counter
LA[7:0] valid rising edge MWB* LADO falling edge A[7:0]
BLT_STATE=1 BLT_INIT=1 INIT
Hold
Increment counter
BLT_STATE=1 DUAL_PATH=13 BLT_INIT=0 BLT_STATE=11 DUAL_PATH=0 BLT_INIT=0
Prop
LADO rising edge A[7:0]
Prop
VCIN* valid LADO rising/ falling edge Counter carry LADO falling edge VCOUT* valid LADO rising edge VCOUT* valid Minimum pulse width LADO (High) LADO (Low) BLT_STATE=1 DUAL_PATH=13 BLT_INIT=0 BLT_STATE=11 DUAL_PATH=0 BLT_INIT=0
t134 Hold t135 Prop
Prop
4.5.6
VMEbus Address Latch (L8) Multiplexer (S3)
VMEbus Address Latch Multiplexer selects source VMEbus address signals A[7:0]. information supplied A[7:0] originates three sources: block transfer data pipeline latch VMEbus master block transfer counter VMEbus address latch VMEbus address latch control selection source signals A[7:0]. Latch uninitialized power predictable operation should loaded prior use.
Table 4-10. VMEbus Address Latch Multiplexer Operation
Table 4-10 shows latch information into
Logic
Functional Description
Operational Description
Required Condition
Parameter
Select
falling edge A[7:0] valid ABEN* falling edge A[7:0] valid falling edge A[7:0] valid
BLT_STATE=1 BLT_STATE=1 BLT_STATE=0
Prop Prop Prop Hold
Load
LA[7:0] valid LADO rising edge
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CY7C964 Operation
4.5.7
VMEbus Address Comparator
VMEbus Address Comparator made three logic elements: address mask register, address compare register, high performance, bit, equality comparator. compare mask registers control compare logic. mask register contains value that enables disables bits comparator. compare register contains pattern. enabled bits compare register matched against value A[7:0]. match detected (all active bits equal), VCOMP* output driven Low. Neither compare register mask register preset power must tialized predictable operation. writing compare register clears mask register. This prevents inadvertent address compares during configuration process. Chapter further information VMEbus address comparator.
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-5. CY7C964 Block Diagram: VMEbus Address Comparator
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CY7C964 Operation
Table 4-11. VMEbus Address Comparator Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Select compare register
LDS, MWB* valid STROBE falling edge LD[7:0] valid STROBE rising edge LDS, MWB* valid STROBE falling edge LD[7:0] valid STROBE rising edge A[7:0] valid VCOMP* valid A[7:0] valid VCOMP* invalid
LDS=1, MWB*=1
Hold Hold
Load compare register
Select mask register
LDS=0, MWB*=1
Hold Hold Prop Prop
Load mask register
Compare
Minimum pulse width
STROBE minimum pulse width
4.5.8
VMEbus Block ransfer Data Pipeline Multiplexer
Latches form stage high performance data pipeline block transfer operations. These latches load from local signals LD[7:0], drive VMEbus address signals A[7:0]. Latches load from local data signals LD[7:0] combina tion with multiplexer drive D[7:0]. first cycle block transfer, data LD[7:0] written latch During second local data fetch block transfer operation (D64=1), data from LD[7:0] written latch data within latch moves fetches must performed form block transfer data word. During modes operation (D64=0), data from LD[7:0] written latch This normal data path from LD[7:0] D[7:0] operation. Because latches implemented transparent latches, loaded from LD[7:0] when transparent (LEDO=0). None latches initialized power Therefore, predictable operation, these latches should written prior their use.
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CY7C964 Operation
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-6. CY7C964 Block Diagram: Block Transfer Data Pipeline Multiplexer
Table 4-12. VMEbus Block Transfer Data Pipeline Multiplexer Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Load register Load register Drive A[7:0]
LD[7:0] valid LEDO rising edge LD[7:0] valid DENO* falling edge rising edge A[7:0] valid LD[7:0] valid DENO* rising edge LD[7:0] valid LEDO rising edge rising edge D[7:0] valid falling edge D[7:0] valid DENO* LEDO
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LEDO=0 BLT_STATE=1
Load register Load register Multiplexer selects drive D[7:0] Multiplexer selects drive D[7:0] Minimum pulse width
Hold Hold Prop Hold t131 Hold t132 Prop Prop
CY7C964 Operation
4.5.9
VMEbus Block ransfer Data Demultiplexer
VMEbus block transfer data demultiplexer moves data from D[7:0]/A[7:0] LD[7:0]. demultiplexer consists three latches output tiplexer, During block transfer operations (D64=1), data written latches simultaneously rising edge LEDI. Multiplexer then selects either latch depending state source LD[7:0]. most applications, should connected LA2, showing that contains even words (addresses 1016.) contains words (address 1416.). Latch also used operating modes. None these latches initialized power predictable operation should initialized prior use.
LA[7:0]
LD[7:0]
Comp
D[7:0]
A[7:0]
VCOMP
Figure 4-7. CY7C964 Block Diagram: Block Transfer Data Demultiplexer
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CY7C964 Operation
Table 4-13. VMEbus Block Transfer Data Pipeline Demultiplexer Operation
Logic
Functional Description
Operational Description
Required Condition
Parameter
Load register Load register
D[7:0] valid DENIN* falling edge D[7:0] valid DENIN1* falling edge D[7:0] valid LEDI rising edge A[7:0] valid LEDI rising edge rising edge LD[7:0] valid rising edge LD[7:0] valid
DENIN1*=0, LEDI=0 LEDI DENIN*=0, LEDI=0 LEDI LEDO=0 LEDO=0 D64=1 LDS=1 D64=1
Hold Hold Hold Hold Prop Prop Prop Prop
Load register Load register Select
Select Select Minimum pulse width
falling edge LD[7:0] valid falling edge LD[7:0] valid DENIN* DENIN1* LEDI
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