Appendix Error Messages This appendix reference SpDE messages. er

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Appendix Error Messages
Appendix Error Messages
This appendix reference SpDE messages. error messages after different actions using QuickWorks tools. Export QuickLogic from Hierarchy Navigator's Process menu: Refer section this appendix titled Export Design Verifier. Import from SpDE's File menu: Refer section this appendix titled Import Design Verifier. Import Verilog from SpDE's File menu (Synplify-Lite Verilog Synthesis): Refer Synplify-Lite Documentation numbered error messages from QuickLogic tools: Refer section this appendix titled SpDE Tool Errors. Error Messages from other QuickLogic supported design tools: Refer supplemental documentation design tool.
Export Design Verifier
Most design verification performed QuickLogic netlist imported into SpDE. These errors presented Import Design Verifier section below. Some design errors, however, will prevent QuickLogic netlist from being exported from Hierarchy Navigator. These errors summarized below.
Schematic Errors
attribute instance <instance> does start with 'N'. attribute 'FIXED=' specified instance contains unrecognized value. valid FIXED attribute values. attribute without place attribute instance <instance>. specified instance, FIXED attribute been set, PLACE attribute not.
Appendix
QuickWorks Users Guide
FRAG_A symbol missing macro <macro> FRAG_F symbol missing macro <macro> FRAG_M symbol missing macro <macro> <net> illegally connected macro <macro> Master Cell macro been defined incorrectly. Refer Macro Library appendix details illustrations. Macro <macro> contains symbols which recognized primitives. illegal symbol been used definition Master Cell macro. Refer Macro Library appendix details illustrations. <net> ported macro <macro> There must 'hanging' nets Master Cell macro. Refer Macro Library appendix details illustrations. Schematic <sch> contains both primitive non-primitive symbols. Fragments which used define Master Cells have been mixed with other symbols same schematic. Master Cells must defined separate schematic. Schematic <sch> contains symbol which type CELL BLOCK. specified schematic uses symbol that compatible with QuickLogic tools. Symbol <symbol> schematic symbol exists design that schematic same name. Symbol type symbol <symbol> should BLOCK schematic that does define Master Cell symbol with type CELL. Symbol type symbol <symbol> should CELL schematic that defines Master Cell symbol without cell type CELL. Change cell type symbol editor.
QuickBoolean Fatal Errors
Equation already exists variable approximately line line Boolean File, filename variable name given appears left side equation more than once. second occurrence near specified line number.
Appendix
Appendix Error Messages
Must write Registered Equation variable before reference variable.dot_property dot_property (.clkf, .setf, .rstf) used VARIABLENAME before registered equation VARIABLENAME found. dot_properties after registered equation. Syntax error approximately line line Boolean file, filename QuickBoolean file cannot processed error near specified line number. This commonly caused illegal characters illegal equations (operators left side equation, mismatched parentheses, etc.). Input pin_name used Output equation Symbol symbol input signal QuickBoolean symbol been used left side QuickBoolean equation. schematic boolean file symbol symbol symbol exists there schematic QuickBoolean file associated with this symbol. This will happen have symbol without .QEQ file same name.
QuickBoolean Warnings
Warnings prevent QuickLogic netlist from being created.
symbol symbol pin_name unused Boolean file exists symbol QuickBoolean file used equations. symbol symbol Output Variable variable unused. variable exists left side equation QuickBoolean equation file, used input another equation output QuickBoolean symbol. symbol symbol Variable variable does have input pin. variable exists only input QuickBoolean equation file, there input symbol this variable. symbol symbol attached pin_name QuickBoolean symbol SYMBOLNAME attached
Appendix
QuickWorks Users Guide
Import Design Verifier
Design Verifier, which runs when design loaded into SpDE, presents Notes, Warnings, Errors interactive list box.
Notes
Notes intended bring situation designer's attention. situation probably problem, should verified nevertheless.
Gate <gate> used, being removed Design Verifier determined that gate being used. This "stripper" function deactivated from SpDE Tools Options dialog box.
Warnings
Warnings serve alert designer problematic situation, commonly associated with real problem.
Exceeded recommended limit high-drive nets many nets sourced HDPADS, CKDPADS, and/or double-buffers (parallel gates); Router able complete. described Router chapter, using less signals tandem with these pads guarantees routability. Gate <gate> cannot have fixed placement specified gate cannot have fixed placement. Fixed placements applied logic cells which utilize flip-flop logic cell, discussed Placer chapter. Gate <gate> There external defined input output design. path analyzer will able this gate defined start stop point analysis. name pad. <net> drives inputs specified fanout zero (the driving gate, other connections). <net> high fanout <fanout> specified exceeded recommended fanout limit bidirectional driver. speed-critical, employ buffering paralleling techniques, discussed Design Techniques chapter.
Appendix
Appendix Error Messages
<net> high input fanout <fanout> specified exceeded recommended fanout limit input driver. speed-critical, employ buffering paralleling techniques, discussed Design Techniques chapter. <net> high logic cell fanout <fanout> specified exceeded recommended fanout limit logic cell driver. speed-critical, employ buffering paralleling techniques, discussed Design Techniques chapter. <pin#> (<gate>) drives reset, disabling ATVG restricted testing pins (see ATVG chapter) driving sets resets, directly indirectly. These pads restricted testing pins, ATVG must disabled. <pin> (gate <gate>) paralleled, disabling ATVG restricted testing pins (see ATVG chapter) wired parallel with another pin. These pads restricted testing pins, ATVG must disabled.
Errors
Errors flag genuine error conditions which will prevent parts from being programmed. However, tools still experimental purposes examination.
Gate <gate> floating input specified gate more unconnected inputs. Floating inputs allowed. <net> driven multiple pads specified driven more than pad. cannot driven multiple pads. <net> fanout drivers specified many high-drive pads. Remove high-drive re-try. <net> driver specified does have driving cell, thus inputs attached cells floating.
Appendix
QuickWorks Users Guide
Fatal Errors
Fatal errors flag serious error conditions which will prevent tools from being run.
Clock <net> multiple drivers specified driven more than clock pad. Clock nets must driven only clock pad. Dual drive gate <gate> illegally connected have tried double-buffering, incorrectly. Refer DoubleBuffering appendix more details. were double-buffering, than illegally tied outputs gates together. Gate illegally connected outputs gates have their outputs tied together illegally. were trying double-buffer these gates, refer double-buffering index details. Gate <gate> placed incompatible cell specified gate invalid fixed placement. bi-directional macro have been placed input cell, vice versa. Gates <gate> <gate> placed same cell gates cannot placed same cell. High-drive <net> opposing pads corner net, driven high-drive pad, cannot drive pair bi/tripads which degree angle each other, corner chip (i.e. top, right side). Move pads away from corner re-try. High-drive <net> pads bottom Multiple high-drive pads (HD2PAD, HD3PAD, HD4PAD) must have fixed placements. Multiple high-drive pads must placed same side chip (all bottom chip). This error will also occur driving tri-state enables directly from HDPADs. this case, cannot driven from HDPAD opposite side chip from HDPAD. <net> uses clock drive logic inputs output CKPAD middle output CKtPAD cannot used drive logic except clock pins, asyncronous presets clears. Gates latches qualify clock pins. Consider using high-drive outputs CKtPAD,
Appendix
Appendix Error Messages
<net> driven more than logic outputs specified driven more than logic cells. driven logic cells case double-buffering (See Design Techniques chapter), never driven logic cells. <net> driven multiple sources specified illegal configuration multiple drivers. only valid configuration multiple drivers two, three, four high-drive pads. <net> both sides specified been wired both inside outside boundary single pASIC. Often, attached outside chip pad, example) will named accidentally with name already used inside chip. <pad> must pre-placed When using HDPADS drive enables more than tri/bipads, tri/bipads must pre-placed either same side adjacent sides HDPAD placement. tri/bipads located opposite side HDPAD. there less pads driven from HDPAD, then verifier will perform placement automatically. Used <number> bi-directional pads with <max> available have used more general pads than available chosen device. Remember that some positions require special pads, such input-only pads clock pads. Look Pads index more help. Used <number> clock pads with <max> available have used more clock pads than available chosen device. There only clock pads (CKPADS) each pASIC device. Look Clock Pads index more help. Used <number> flip-flops with <max> available have used more flip-flops your design than available chosen device. Used <number> input-only pads with <max> available have used more HDPADs your design than available chosen device. There HDPADS available pASIC devices. Look High Drive Pads index more help.
Appendix
QuickWorks Users Guide
SpDE Tool Errors
SpDE reports user errors using Error dialog box. These errors represent design system errors which fixed user. tables below organized tool code; first letters error code indicate tool. XX-(starting with letters)
xx0100 xx0199 Memory SpDE requested more memory than Windows currently available. closing other applications re-run SpDE. still problem, re-starting windows. Many memory problems solved creating larger Windows swap file (see Virtual Memory section System Requirements appendix). Windows offers very efficient memory management-refer Microsoft Windows User's Guide complete details.
CH-Chip file QDIF file converter load design files)
CH0001 CH0002 Error loading binary file: <filename>. Cannot save QDIF file: <filename>. converter software having trouble loading source design saving destination. This could full disk, lack write read access files.
DB-The SpDE Database module
DB0001 DB0002 Invalid Package Type invalid package type been chosen QuickLogic chip chosen. Refer QuickLogic documentation design entry package using valid package types.
ED-EDIF Netlist reader
ED0002 ED0003 Syntax error line <line number> line <line number> EDIF file, illegal syntax been used. ED0004 ED0005 ED0006 Integer '<integer>' large line <line number> Integer '<integer>' large line <line number> Integer '<integer>' range line <line number> line <line number> EDIF file, number <integer> allowed range.
Appendix
Appendix Error Messages
ED0007
Invalid symbol '<symbol>' line <line number> EDIF file contains string <symbol> with invalid character line <line number>. Unexpected file EDIF file ended pre-maturely. This usually because error that occurs during creation EDIF file. Expected line <line number> open parentheses expected (but found) EDIF file line <line number> order comply with EDIF syntax.
ED0008
ED0009
EQ-QuickBoolean Netlister
EQxxxx QuickBoolean Error Design Entry QuickBoolean chapter complete error messages QuickBoolean tool
ET-EDIF Netlist Reader (EDIF SpDE Translator)
ET0006 Package type specified unknown: <package> package specified EDIF file which SpDE does recognize. Refer QuickLogic documentation your design entry tool valid package types. Package incorrect bonding used EDIF file which does exist bonded out) selected package. Either number package type incorrect. Device name specified: Using default. Part Package attributes were present EDIF file. Refer your third party interface documentation details including these attributes.
ET0007
ET0012
GP-Graphing Package
GP0001 GP0002 Error opening clipboard Error opening picture Grapher could properly open picture clipboard with Windows calls. re-booting your computer. Error closing picture Error closing clipboard Grapher could properly close picture clipboard with Windows calls. re-booting your computer.
GP0003 GP0005
Appendix
QuickWorks Users Guide
GP0004
Error putting picture onto clipboard Grapher could complete operation copying graph clipboard. memory, Windows could unstable. re-booting.
JE-LOF Netlister
JE0001 Could open file <filename> <Filename> specified user either does exist does have read attribute. support part <part> device used current design (<part>) currently supported Netlister. Contact QuickLogic details.
JE0002
LS-Load Save Files
LS0001 LS0004 Could open binary file <filename>. <Filename> specified user either does exist does have read attribute. LS0002 LS0005 Wrong part file version file <file>.
version specified part file exists SpDE data directory. Check your WIN.INI file insure that ini-path entry [SpDE] section been properly set. LS0003 LS0006 Unknown part name <part>. part specified design file does exist does have associated part file. Check your WIN.INI file insure that ini-path entry been properly set. LS0007 0010 Part File Errors These errors will occur SpDE cannot find current, valid part file. this error occurs, want re-install SpDE. LS0011 Unknown package type: <package> package specified QDIF file which SpDE does recognize. Refer QuickLogic documentation your design entry tool valid package types.
Appendix
Appendix Error Messages
LS0200
<Error> approximately line <line number> parsing error <Error> occurred while reading line <line number> QDIF file.
PA-Path Analyzer
PA000x Clipboard Errors These errors indicate that Path Analyzer could Windows clipboard properly. re-booting your computer.
PK-Packer (Level Optimizer)
PK0000 PK0001 PK0002 PK0003 Cannot pack many logic cells many HDPADS (input-only pads) used many pads used many CKPADS (clock pads) used design requires more specified resources than available selected pASIC device. fewer specified components select larger device. Illegal fixed location cell been assigned incompatible location. example, high-drive placed bi-directional pin. Consult device reference appendix move fixed placement appropriate location.
PK0004
PR-Programmer Interface
PR0000 PR0029 Programmer Initialization Errors programmer could properly initialize test pASIC(s) being programmed. part could incorrectly inserted socket, damaged, wrong part type, already programmed. This could also improperly configured serial port, serial port which 100% compatible, wrong socket adapter. PR0030 PR0079 port communication errors port could fully initialized. Verify that correct port been selected that cable properly attached. problem persists, there problem with serial port serial card configuration.
Appendix
QuickWorks Users Guide
PR008x
Signature Programming Error signature bits could programmed successfully device programmer. This probably part. this error occurs more than part, then your programmer could damaged.
QS-QDIF Schematic Conversion
QS0000 Unable open <file> Schematic Generator unable access indicated file. file exist, directory have read permission. Can't load <file> Could load QDIF file. file corrupt valid QDIF file. Unable close <file> Schematic Generator unable access indicated file. disk space directory have write permission.
QS0001
QS0002
RT-Router
RT0000 RT0002 Could complete routing Could complete hi-drive routing router does have enough resources complete routing. case hi-drive routing, refer Router chapter Special Routing Cases section. Otherwise, re-placing after changing placer seed.
Appendix
Appendix Error Messages
RT0003
express wires channel <x><y>. Re-run placer with another seed. Router requires more express wires than available specified channel. This problem most often caused excess signals attached high-drive input pads, many double-buffers. described Router chapter, employing four fewer signals tandem with these pads guarantees routability these signals.
SD-SDF Writer
SD0001 Cannot open file: <filename> writer open file that needs create. This could full disk, write-protected file directory.
SP-SpDE
SP0004 SPDE.INI read-only does exist. SpDE could find initialization file spde.ini saving defaults. This could mean that file been erased that file read-only.
SQ-Sequencer
SQ0000 Sequencer could complete. Re-run Router with different seed. Sequencer could determine order which program Via-Links part after routing attempts Rerunning Placer with different seed will correct problem.
UI-User Interface
UI0001 There (are) <number> dll(s) SpDE's path SpDE detected DLL's (.DLL) that needs directory that current SpDE directory. Contact QuickLogic. Cannot convert chip file <filename> SpDE could convert chosen chip (.CHP) file latest version. Possibly non-chip file, chip file from very version SpDE been selected. Unable complete command "<command>" successfully SpDE tried execute command <command> without success.
UI0002
UI0003
Appendix
QuickWorks Users Guide
UI0004
Invalid directory: <directory> chosen directory cannot accessed. This happen chosen directory drive that been "joined" network directory. Also, directory exist. Can't change specified directory chosen directory cannot changed properly. This will happen chosen directory drive that been "joined" network directory. SPDE.INI read only. Cannot save options
UI0005
UI0006 UI0023 UI0024
SpDE could read and/or modify SPDE.INI file. Make sure this file read-only directory. also check win.ini file under [SpDE] that ini-path points directory where this file exists. (.spderc home directory users) UI0008 PKZIP.EXE found path file cannot properly compressed unless PKZIP version 1.01 path. Either PKZIP path, file manually using PKZIP 1.01. Unable command: <command> Reason: <reason> SpDE could Windows application because <reason>. This could indicate improper configuration. printer connected SpDE could detect printer device under windows. Check printer setup Windows Control Panel. Printer SpDE could print default device. Check printer setup Windows Control Panel. File <filename> from later version SpDE. have chosen open file that created from later version SpDE than running currently. intend this, check configuration, re-install latest SpDE tools. Unable convert <filename> SpDE could properly convert <filename> current version SpDE. Contact QuickLogic help.
UI0009
UI0010
UI0011
UI0015
UI0016
Appendix
Appendix Error Messages
UI0017
Can't initialize gang programmers have configuration problem with gang programmers, problem with your serial card. Programmer chapter more information. gang programmers found Check make sure gang programmers connected, plugged that correct port been chosen. automatic place route tools were Check Place Route option settings. have chosen Tools after tools have already been run. wish iterate: change seeds Tools Options, then re-run tools with Selected Tools. Cannot process SPDE.INI file SPDE.INI file been corrupted. Contact QuickLogic.
UI0018
UI0019
UI0020 UI0021
UI0022
Error opening report file <filename> SpDE could open report file created. This could happen were memory load chosen editor, chosen editor could loaded properly. Change chosen editor from View-Preferences. Cannot load QDIF file <filename> error detected while reading QDIF file. file have syntax error (see QDIF appendix QDIF syntax), file have been damaged. Ini-path found win.ini. Using c:\pasic\spde\data SpDE expects find variable ini-path under heading [SpDE] win.ini file. installation program will this automatically. Check win.ini file, re-install SpDE. Save Error error detected while trying save file. This caused write-protect violation insufficient disk space.
UI0034
UI0037
UI005x
Appendix
QuickWorks Users Guide
UI006x
Load Error error detected while trying load file. This caused choosing wrong file type load, trying load file without read attribute.
VE-SpDE Physical Viewer
VE0007 VE0010 VE0012 Value must between <min> <max>
value have entered allowable range. Enter value between <min> <max>. VE0009 VE0011 (unsigned) integer value value have entered does represent proper integer value. SpDE expecting unsigned integer, make sure number positive. Always make sure integers have decimal points.
VG-Verilog Netlister
VG0001 Error: Cannot open file: <filename> Verilog netlister cannot open output file trying create. This could full disk read-only directory.
VL-ViewLogic Netlister
VL0000 VL0004 VL0006 Error: Cannot open file <filename>
ViewLogic netlister could access specified file. Check ViewLogic environment variables, write access specified directory, existence specified file. VL0005 VL0007 Cannot write file: <filename> ViewLogic Netlister could write specified file. Check available disk space write permission specified directory file.
Internal Errors
These errors indicated message Internal Error, Win32s Error, Internal Error, Fatal Error accompanied their usually cryptic nature. These errors should Appendix
Appendix Error Messages occur-they indicate inconsistency SpDE's data structures. these errors encountered, record text error completely contact QuickLogic Corporation.
Memory Errors
tools cannot execute properly, error message like "Unable toolname, check path", error message with reference being memory then probably running many applications Windows. Close unnecessary applications again. After memory error occurs, best save your work re-start Windows. When memory error occurs, tool close properly leave Windows somewhat unstable state. memory because improper Virtual Memory Settings. Check Tutorial Chapter section Virtual Memory more details.
Appendix
QuickWorks Users Guide
Appendix

Appendix Error Messages This appendix reference SpDE messages. er

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