SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer
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APPLICATION NOTE 9501
SXT6234 E-Rate Multiplexer
16-E1/E3 Multiplexer/Demultiplexer
Introduction
SXT6234 E-Rate Multiplexer offers simple economic approach building E1/E2, E2/E3 E1/E3 multiplexers demultiplexers. This application note provides system designer with 16E1/E3 multiplexer/ demultiplexer design example. brief overview fundamental E1/E3 protocol included establish common reference with readers. additional information, refer ITU-T General Aspect Digital Transmission Systems, Recommendations G.700G.772. Related documentation includes SXT6234 Data Sheet SDB6234 E1/E3 Demo Board User Guide.
Standard
standard designed support transmission thirty digitized voice channels. Analog-Digital conversion each channel based Nyquist sampling theory. This theory says that digitize analog signal that contains sufficient information allow accurate analog reconstruction, signal must sampled frequency that least twice channel bandwidth. Sampling 8,000 second industry-accepted rate. This rate allows accurate reproduction voice-grade 4-kHz bandwidth channel. sampling produces series narrow pulses with microseconds (µsec) period. magnitude height each analog sample digitally encoded binary value. Furthermore, sampling pulse duration less than µsec during µsec period. Consequently, possible interleave sampled pulses from other signals within µsec period. standard interleaves thirty-two channels; Thirty channels transmit digitized analog signals, remaining channels send signaling synchronization information. shown Table each channel assigned specific time-slot.
Standards
International Telecommunication Union Telecommunication Standardization Sector (ITU-T) standardized specifications. ITU-T formerly known Consultive Committee International Telephone Telegraph (CCITT).
Standard European Hierarchy
accommodate higher transmission speeds, carriers developed hierarchy levels shown Table
Table Frame
Time slot Type information Synchronization Speech Signaling Speech 1-15 17-32
Table Standard Hierarchy
Level Number System Number Voice Circuits rate Mbps
1920
2.048 8.448 34.368 139.264
Frame length bits Frame duration µsec time slots constitute frame. Each slot bits. Consequently frame bits time slots bits/frame Since 8000 frames transmitted each second, rate bits /frame 8000 frames/second 2.048 Mbps.
Standard
second level standard. standard multiplexes four channels into single 8.448 Mbps channel 2.048 Mbps 8.448 Mbps). recommendations, defined ITU-T G.742 G.745, exist this multiplexing. G.742 SXT6234 shown Table G.742 uses positive justification intended digital paths between countries.
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer Table Frame Assignments
Number Number Type Information
Standard
third level standard. nominal bit-rate 34.368 Mbps result multiplexing four 8.448 Mbps channels.
1-10 13-212 213-216 217-424 425-428 429-636 637-640 641-644 645-848
1-10 13-212 5-212 5-212 9-212
Frame alignment Alarm indication signal remote multiplex equipment reserved national Bits from tributaries Justification control bits Bits from tributaries Justification control bits Bits from tributaries Justification control bits Bits from tributaries available justification Bits from tributaries available negative justification
Table Frame Assignments
Number 1-10 13-384 385-388 389-768 769-772 773-1152 1153-1156 1157-1160 1161-1536 Number 1-10 13-384 5-384 -384 9-384 Type Information Frame alignment Alarm indication remote digital multiplex equipment reserved national Bits from tributaries Justification service bits Bits from tributaries Justification service bits Bits from tributaries Justification service bits Bits from tributaries available justification Bits from tributaries
Table Frame
Standard rate Frame length Frame duration Bits tributaries Maximum justification rate tributaries 8.448 Kbits/s bits 100.39 µsec bits Kbit/s
Table Frame Usage
bits Usage Frame
Table Frame Usage
bits Usage Frame
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer
Multiplexing Method
multiplexing method uses cyclic interleaving tributary numbering order. This conforms with positive justification recommendation ITU-T G.742 G.751.
Table Frame
Standard rate Frame length Frame duration Bits tributaries Maximum justification rate tributary G.751 kbit/s 1536 bits 44.7 µsec bits 22.375 kbit/s
CODEC pins externally accessible, allowing either HDB3 multiplexer demultiplexer. Alternatively, SXT6234 used 5-channel HDB3 CODEC. Access provided Alarm Indication Signal (AIS) National Bit. Four auxiliary speed data flag channels available stuffing bits each tributary channel.
Figure SXT6234 E-Rate Multiplexer
HDB3 Decode HDB3 Decode HDB3 Decode HDB3 Decode Elastic Store Elastic Store Elastic Store Elastic Store HDB3 Encode SXT6234 E-Rate Multiplexer
Justification
Justification process changing data rate digital signal from inherent rate different rate without loss information. Positive justification method which data rate used convey signal higher bitrate than original signal. Positive justification normally achieved assigning some time-slots frame handle additional information that result from justification. signal justification unnecessary, these timeslots contain regular channel information they might remain empty. justification service digits indicate these time-slots contain information digits justifying digits. justification control signal standard defined bits (see frame tables). Three bits used show type justification; fourth stuffing bit.
SXT6234 E-Rate Demultiplexer
HDB3 Encode
HDB3 Decode
HDB3 Encode Demux HDB3 Encode
E-Rate Multiplexer
SXT6234 single-chip solution multiplexing four tributaries into high speed stream demultiplexing high speed stream back into four tributaries. required circuitry been integrated into SXT6234; there need external framer. SXT6234, fabricated with 1.2-micron CMOS technology, packaged 100-pin PQFP package. This device consists multiplexer block, demultiplexer block, four HDB3 Encoder/Decoders each tributary, HDB3 Encoder/Decoder high speed stream. SXT6234 supports multiplexing formats: multiplexes four channels into channel. other format multiplexes four channels into channel. Both fully compliant with ITU-T recommendations, G.742 G.751 respectively.
HDB3 Encode
E1/E3 Multiplexer Block Diagram
block diagram E1/E3 Multiplexer shown Figure LINE INTERFACE Receive clocks from pulse data. Accepts either HDB3 encoded signals (clocks along with positive negative data), data (clock data). This depends whether Line Interface Unit (LIU) performs HDB3 coding.
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer Figure E1/E3 Multiplexer
2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps LXT305/LXT332 Line Interface Line Interface Line Interface Line Interface HDB3 Decode HDB3 Decode HDB3 Decode HDB3 Decode Elastic Store Elastic Store Elastic Store Elastic Store SXT6234 E-Rate
HDB3 Encode CLK,
2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps
Line Interface Line Interface Line Interface Line Interface
HDB3 Decode HDB3 Decode HDB3 Decode HDB3 Decode
Elastic Store Elastic Store Elastic Store Elastic Store
SXT6234 E-Rate
Line Interface
34368 Kbps CLK,
HDB3 Encode HDB3 Decode HDB3 Decode HDB3 Decode HDB3 Decode Elastic Store Elastic Store Elastic Store Elastic Store SXT6234 E-Rate
HDB3 Encode
2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps
Line Interface Line Interface Line Interface Line Interface
HDB3 Decode HDB3 Decode HDB3 Decode HDB3 Decode
Elastic Store Elastic Store Elastic Store Elastic Store
SXT6234 E-Rate
HDB3 Encode
2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps
Line Interface Line Interface Line Interface Line Interface
HDB3 Decode HDB3 Decode HDB3 Decode HDB3 Decode
Elastic Store Elastic Store Elastic Store Elastic Store
SXT6234 E-Rate
HDB3 Encode CLK,
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer
SXT6234, E1/E2 STAGE tributary does perform HDB3 decoding, then signals routed SXT6234 onboard HDB3 decoder. inputs clock decoder data input signals (both positive negative). onboard HDB3 decoder then outputs data clock Elastic Store multiplexer portion SXT6234. provides HDB3 decoding, then data clock sent directly elastic store multiplexer portion SXT6234 external pin. Each four-tributary group interleaved into single, intermediary data stream. onboard crystal oscillator drives data from multiplexer rate 8.448 MHz. stuffing algorithm implemented SXT6234 ensures tributary rate integrity output. SXT6234 contains elastic store buffers manage bit-stuffing process. data sent tributary E-Rate Multiplexer, stage E2/E3. SXT6234, STAGE tributary does provide HDB3 encoding, then encoding performed SXT6234; positive negative data output provided. activity monitor provides tributary fail notification when necessary. provides HDB3 encoding, data clock passed multiplexer input. multiplexer portion SXT6234 interleaves four asynchronous rate data streams into single data stream. Depending user configuration, either onboard crystal oscillator external reference clock drives data output frequency from multiplexer rate 34.368 Mbps. stuffing algorithm implemented SXT6234 ensures tributary rate integrity output.
Figure SXT6234 Multiplexing Function
LREFCK MNAT MAIS AUX1 MLDPI1 MLDNI1 HDB3 Decoder MLNRZ1 MLCK1 MLFAIS1 Elastic Store Tributary Tributary Tributary Tributary MHDPO HDB3 Encoder MHDNO MESA1 MSYNC MLNRZO1 MHNRZ MLBPV1
MHMUX
MHNRZI MHHDB3C
E1/E3 Demultiplexer Block Diagram
block diagram E1/E3 demultiplexer shown Figure LINE INTERFACE Receive clocks from pulse data. does provide HDB3 decoding, then passes HDB3 encoded signals SXT6234. These signals consist clock (positive negative) data. does provide HDB3 decoding, then passes data clock SXT6234.
Multiplexer Block Diagram
block diagram Figure shows used SXT6234 accomplish multiplexing function. Only tributary been referenced. tributaries omitted clarity, they same tributary
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer
SXT6234, E3/E2 STAGE does HDB3 decoding then signals routed SXT6234 onboard HDB3 decoder. inputs clock decoder data input signals (both positive negative). onboard HDB3 decoder then outputs data clock Elastic Store multiplexer portion SXT6234. provides HDB3 decoding, data clock received demultiplexer portion SXT6234. Four rate data streams recovered from data sent from SXT6234 four tributaries. SXT6234, E2/E1 STAGE demultiplexer portion SXT6234 recovers four data streams from intermediary stream. does provide HDB3 encoding, streams HDB3 encoded sent positive negative voltages line interface. (LXT305 LXT332) provides HDB3 encoding stream sent data line interface.
Figure E1/E3 Demultiplexer
LXT305/LXT332 SXT6234 E-Rate Multiplexer Demux 34368 Kbps Line Interface CLK, HDB3 Decoder HDB3 Encoder HDB3 Encoder HDB3 Encoder HDB3 Encoder Line Interface SXT6234 E-Rate Multiplexer Line Interface Line Interface Line Interface 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps 2048 Kbps
HDB3 Encoder HDB3 Encoder HDB3 Encoder HDB3 Encoder
SXT6234 E-Rate Multiplexer Demux HDB3 Decoder
HDB3 Encoder HDB3 Encoder HDB3 Encoder HDB3 Encoder
Line Interface Line Interface Line Interface Line Interface
Demux HDB3 Decoder
SXT6234 E-Rate Multiplexer Demux HDB3 Decoder
HDB3 Encoder HDB3 Encoder HDB3 Encoder HDB3 Encoder
Line Interface Line Interface Line Interface Line Interface
SXT6234 E-Rate Multiplexer Demux HDB3 Decoder
HDB3 Encoder HDB3 Encoder HDB3 Encoder HDB3 Encoder
Line Interface Line Interface Line Interface Line Interface
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer Demultiplexer Block Diagram
Figure shows used SXT6234 perform demultiplexing function. Only tributary been referenced. tributaries omitted clarity, they same tributary
Alarms
multiplexer demultiplexer sides contain following alarm provisions: Input Loss Alarms receive line interfaces. Output Fail Alarms transmit line interfaces. Frame Loss Alarm line. With multiplexer demultiplexer: Alarm equations are: ME1FAISi MELOSi DE1FAISi DE2AISDj DE2FLOSj DE3LOS DE3FLOS DE3AISD ME2FAISj ME2LOSj DE2FAISj ME3AIS DE3LOS DE3FLOS DE3AISD DE3LOS (DE3FLOS&~DE3LOS) DEAISD
Figure SXT6234 Demultiplexing Function
DNAT DAIS DHNRZI Demux DHDMXC DLNRZO1 DLNRZI1 MODESEL DLCO1 DLCI1 Tributary Tributary Tributary Tributary DHDPI DHDNI DHHDB3C HDB3 Decoder DSYNC FLOS DHAISO AUXO1 DHNRZO HDB3 DHBPVO Encoder
Auxiliary Channels
Within standards, there four extra bits used justification (bits 641-644 frame, bits 1157-1160 frame). These bits used four auxiliary channels that would provide rate KHz, rate KHz. examples these used are:
DHNRZO DHBPVO
Voice Channel Maintenance. Data Counter implemented with parity circuit that would count data bits during frame incoming stream.
National Bits
bits accessible compliance with ITU-T recommendation. However, these bits also used auxiliary channel rate
Microcontroller
E1/E3 multiplexer design improved using microcontroller control alarms other settings. microcontroller, such Intel 87C51 sufficient. microcontroller could monitor alarms, provide alarm history, update control panel even sound audible alert necessary. This microcontroller could monitor switches loop-back instructions, test update National Bit, check configuration jumpers E1/E2 E2/E3 functions.
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer Table Multiplexer Description
Input LFRECK MNAT MAIS MHMUXC Reference clock tributary data used reference functions. National Input. input. High speed multiplexer clock input. Tributary Input AUX1 Auxiliary data input signal this clocked into frame stuffing location (J1) when justification such that tributary data placed this location. high alarm signal MESA1 indicates this condition during current frame. Positive data input. Clocked positive transition clock MCKL1. Negative data input. Clocked positive transition clock MCKL1. Clock input tributary channel Force tributary Active high signal forces (all data LREFCK clock. Tributary Output MLNRZO1 MLNRZ1 MLBPV1 MESA1 HDB3 decoder output clocked rising edge MCKL1. Multiplexer tributary input clocked falling edge clock signal MLCK1. HDB3 decoder bipolar violation alarm. This open collector output pulses when bipolar violation occurs decoding process. Multiplexer justification status tributary high indicates stuffing current frame. indicates information bit. When externally filtered, this used indicate elastic store failure incorrect tributary frequency. Output MHRZO MSYNC Multiplexer output data clocked rising edge MHMUXC. Multiplexer frame synchronization pulse high speed clock cycle synchronous with last frame. HDB3 Decoder MHNRZI MHHDB3C MHDPO MHDNO HDB3 encoder input clocked rising edge MHHDB3C. HDB3 encoder clock input. When used conjunction with multiplexer, this should tied multiplexer clock (MHMUXC). HDB3 encoder positive data output. Positive rail clocked rising edge MHHDB3C. HDB3 encoder negative data output. Negative rail clocked rising edge MHHDB3C.
MLDPI1 MLDNI1 MCKL1 MLFAIS1
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SXT6234 E-Rate Multiplexer 16-E1/E3 Multiplexer/Demultiplexer Table Demultiplexer Description
Demultiplexer Input DHNRZI DHDMXC MODESEL input clocked rising edge DHDMXC. Clock input. Mode selection multiplexer demultiplexer operation. selects 4E1/E2 multiplexing. high selects 4E2/E3 multiplexing. HDB3 Decoder DHDPI DHDNI DHHDB3C DHNRZO DHBPVO HDB3 decoder positive rail input clocked rising edge DHHDB3C. HDB3 decoder negative rail input clocked rising edge DHHB3C. Clock input HDB3 decoder When used conjunction with demultiplexer this should tied demultiplexer clock DHMUXC. HDB3 decoder data clocked rising edge DHHDB3C. HDB3 decoder bipolar violation alarm. This active high signal pulses when bipolar violation occurs decoding process. HDB3 Encoder DLNZO1 DLCO1 Tributary output. This signal clocked rising edge DHDMXC transitions coincident with falling edge DLCO1. Demultiplexer side recovered clock tributary This clock duty cycle gapped points frame where tributary data present. maximum clocks frame word will match that multiplexer tributary input. This signal clocked rising edge DHDMXC. HDB3 encoder input clocked rising edge DLCI1. Clock input HDB3 encoder Multiplexer Output DNAT DAIS DSYNC FLOS DHAIS National output. output. Pulse high speed clock cycle synchronous with last frame. Loss frame alarm. Active high frame loss alarm that occurs when demux detected frame word. Input detect. Active high alarm occur when condition (AIS) detected DHNRZI input. This alarm does trip input frame signal (i.e., tributaries multiplexer side). Auxiliary Output AUXO1 DLDPO1 DLDNO1 Auxiliary flag data output that contains data value input AUX1. HDB3 encoder positive rail output clocked rising edge DLCI1. HDB3 encoder negative output clocked rising edge DLCI1.
DLNRZI1 DLCI1
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