µPD16661A COLUMN (SEGMENT) DRIVER WITH BUILT-IN µPD16661A co

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

µPD16661A COLUMN (SEGMENT) DRIVER WITH BUILT-IN µPD16661A co

Datasheet Thumbnail

Top Searches for this datasheet

INTEGRATED CIRCUIT
µPD16661A
COLUMN (SEGMENT) DRIVER WITH BUILT-IN
µPD16661A column (segment) driver which contains capable full-dot drive. With outputs, this driver display bits built-in. driver combined with
µPD16666 display from (640 dots). µPD16661 upwardly compatible with µPD16661A.
FEATURES
Display incorporated: bits Logic voltage: Duty: 1/240 Output count: outputs Capable gray scale display: gray scales (frame thinning-out) Memory management: packed pixel system 8/16-bit data
ORDERING INFORMATION
Part Number Package (TAB)
information contained this document being issued advance production cycle device. parameters device change before final production Corporation, discretion, withdraw device prior production.
Document S11498EJ1V0PM00 (1st edition) Date Published October 1996 Printed Japan
1996
µPD16661A
NAMES
Classification Name Function
UBEB BMODE GMODE REFRHB TEST RESETB DOFEB OSC1 OSC2 FRMB DOUTB Y160 VCC1 VCC2
Data buses pins) Address buses pins) Chip select Read signal Write signal High byte enable Ready signal (Ready state Specifies allocation locations (No. Specifies allocation locations (No. Specifies allocation locations (No. Specifies liquid-crystal panel allocation direction. Master/slave switching (Master mode Data switching bits, bits) Gray scale data weight reverse switching (When data [1,1], black, white) Self-diagnosis reset Test test mode, on-chip pull-down buffer) Reset signal Display input signal Oscillator external resistor Oscillator external resistor Column drive signal output, input) Frame signal output, input) driver drive level selection signal (1st line) driver drive level selection signal (2nd line) Display output signal Liquid-crystal drive output Grounding (two pins; three 3.3-V pins) power power Liquid-crystal drive analog power Liquid-crystal drive analog power Liquid-crystal drive analog power
Control Signals
Liquid-Crystal Drive Powers
Note
3.3-V D0-D15, A0-A16, CBS, OEB, WEB, UBEB, RDY, BMODE, GMODE, PL0, PL1, PL2, DIR, OSC1, OSC2, RESETB, DOFEB, TEST, STB, FRMB, DOUTB
µPD16661A
BLOCK DIAGRAM
PL0, TEST Control CSB, WEB, UBEB Input control address Address management circuit Arbiter bits
BMODE GMODE REFRHB RESETB Data control Data latch
Frame thinning-out
STOP
control
OSC1
oscillator OSC2 DOFFB Liquid-crystal timing generation
FRMB
Internal timing generation Data latch Self-diagnosis circuit
operation
operation
Level shifter operation operation
Liquid-crystal drive circuit outputs
FRMB
DOUTB
Y160
µPD16661A
BLOCK FUNCTIONS
Address management circuit address management circuit converts addresses transferred from system through into addresses compatible with memory built-in RAM. This function used address size (480 dots) with eight these LSIs, thus making possible configure liquid-crystal display system without difficulty. Arbiter arbiter adjusts contention between access from system read liquidcrystal drive side. Static (single port) bits Data control data controls data transfer direction means Read/Write from system. mode switched 8/16 bits BMODE pin, relation between display data gray scale switched GMODE pin. Frame thinning-out control frame thinning-out control indicates four gray scales with three frame thinning-out. thinning-out method changed terms columns lines, i.e., pixels, unit. Internal timing generation Internal timing each block generated from FRMB signals. oscillator oscillator generates clock which will become criterion frame frequency Master mode. 480th this oscillation becomes frame frequency. example, frame frequency required oscillation frequency 38.4 kHz. oscillator built-in capacity, please adjust required oscillation frequency with external resistor. Slave mode, oscillation stopped. Liquid-crystal timing generation Master mode, FRMB (frame signal) (column drive signal strobe) generated. control This circuit realizes four gray-scale displays. (10) Data latch Reads latches 160-pixel data from RAM. (11) Data latch Latches 160-pixel data synchronously with signal. (12) Level shifter level shifter converts from operating voltage (3.3 internal circuit liquid-crystal drive circuit driver interface voltage
µPD16661A
(13) Decodes gray scale display data make compatible with liquid-crystal drive voltages (14) Liquid-crystal drive circuit Selects liquid-crystal drive powers which compatible with gray scale display data display signal (DOFFB), generate liquid-crystal applied voltage. (15) Self-diagnosis circuit Automatically detects operation timing between master chip slave chip external noise generates refresh signal column drivers.
MEMORY
Address Unused Display data Nos. Display data Nos.
Description
Address Image Diagram (Example VGA-Size Configuration)
Column direction specified with Y160 Line direction specified with Address progress direction Y160 Y160 Y160
L240
Address progress direction
L240
Y160
Y160
Y160
Y160
µPD16661A
DATA BUSES
byte data lined data based Little Endian NEC/Intel-series bus.
16-Bit Data (BMODE
Byte-unit access
00001H 00003H 00005H
Addresses proceed shown right.
00000H 00002H 00004H
Word-unit access
00000H 00002H 00004H
Addresses proceed shown right.
access from system performed units words bits), bytes bits), UBEB (high byte enable) used show whether valid data bytes either both) D15.
UBEB MODE selected Read Dout Dout Dout Dout
Write
Output disable
Don't Care High impedance
µPD16661A
8-Bit Data (DMODE
Addresses proceed shown right.
00000H 00001H 00002H
MODE
Note Note Note Note
selected Read Write Output disable
Dout
Don't Care High impedance 1RWH through should left open because they internally pulled down.
µPD16661A
Relationship Between Data Bits Pixels
display four gray scales, each pixel consists bits. configured with four pixels pixels word) using packed pixel system. BMODE Byte-unit bits) access
Pixel Pixel Pixel
Pixel
Pixel
Pixel
Pixel
Pixel
00000H 00001H Liquid-Crystal Panel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
Word-unit bits) access
Pixel Pixel Pixel
00000H Pixel Pixel Liquid-Crystal Panel
Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
00000H
00001H Pixel Pixel
00000H
00002H Pixel
00003H
00002H
BMODE
Pixel Pixel Pixel Pixel Pixel
Pixel
Pixel
Pixel
00000H 00001H Liquid-Crystal Panel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel
00000H
00001H
00002H
00003H
µPD16661A
Relationship Between Display Data Gray-Scale Level
GMODE
Liquid-Crystal State Display State
Dn+1
Gray Scale Level Display State
GMODE
Liquid-Crystal State Display State
Dn+1
Gray Scale Level Display State
µPD16661A
ALLOCATION ADDRESS MANAGEMENT
Addresses managed allow eight these LSIs used configure liquid-crystal display size (480 dots). eight these LSIs connected same sharing CSB, WEB, pins. screen liquid crystal display treated memory area system, more this need decoded. PL0, PL1, pins used specify determine arrangement. pins used determine directions (vertical, horizontal) liquid-crystal display.
µPD16661A
Addresses Size Horizontally
Specified with Specified with L239 0EE00 L240 0EF00 0F000 0F100 00000 00100 Y153 Y160 Y153 Y160 Y153 Y160 Y153 0009E 0019E Y160
00026 00028 00126 00128
0004E 00050 0014E 00150
00076 00078 00176 00178
0EE26 0EE28 0EF26 0EF28 0F026 0F028 0F126 0F128
0EE4E 0EE50 0EF4E 0EF50 0F04E 0F050 0F14E 0F150
0EE76 0EE78 0EF76 0EF78 0F076 0F078 0F176 0F178
0EE9E 0EF9E 0F09E 0F19E
L239 1DE00 L240 1DF00 Y153 Y160
1DE26 1DE28 1DF26 1DF28 Y153 Y160
1DE4E 1DE5E 1DF4E 1DF5E Y153 Y160
1DE76 1DE78 1DF76 1DF78 Y153 Y160
1DE9E 1DF9E
Specified with 0009E 0019E 00078 00076 00178 00176 00050 0004E 00150 0014E 00028 00026 00128 00126 00000 00100 Y160 Y153 Y160 Y153 Y160 Y153 Y160 Y153
Addresses Size Vertically
Specified with
0EE9E 0EF9E 0F09E 0F19E 0EE76 0EF76 0F076 0F176
0EE78 0EF78 0F078 0F178
0EE50 0EF50 0F050 0F150
0EE4E 0EF4E 0F04E 0F14E
0EE28 0EF28 0F028 0F128
0EE26 0EF26 0F026 0F126
0EE00 0EF00 0F000 0F100
L239 L240
1DE9E 1DF9E Y153 Y160 Y153 Y160
1DE78 1DE76 1DF78 1DF76
1DE50 1DE4E 1DF50 1DF4E Y153 Y160
1DE28 1DE26 1DF28 1DF26 Y153 Y160
1DE00 L239 1DF00 L240
µPD16661A
µPD16661A
INTERFACE
Function (Ready) built-in uses single-port RAM. prevent contention between access from side reading liquid-crystal drive side, performs Wait operation CPU. Timing
UBEB
OEB/WEB Hi-z Hi-z
Wait state
Ready state access time
Connection uses 3-state buffer. When more this used, pins each wire-connected pull-up resistor installed externally.
Ready input Pull-up resistor Column driver
Column driver
µPD16661A
Access Timing Read timing
UBEB Hi-z Hi-z Dout Hi-z Hi-z
Write timing
UBEB Hi-z Hi-z
µPD16661A
GRAY SCALE CONTROL
Four gray scales expressed with 3-frame thinning-out. thinning-out method changed with nine pixels, that pixels lines liquid-crystal panel. Frame thinning-out method
Frame Gray scale Gray scale Gray scale Gray scale Lines Frame Frame Columns
µPD16661A
LIQUID-CRYSTAL TIMING GENERATION
Reset State circuit placed reset state, internal counter zero-cleared. After cancelling reset, display function operates during 4-frame cycle even when DOFFB
RESETB FRMB DOUTB
Internal state Display Display
Liquid-Crystal Timing Generating Circuit circuit Master mode when FRMB signals generated timed with duty ratio 1/240. Generates driver drive voltage selection signals driver. FRMB generated twice frame. generated times half frame; times frame. Generation FRMB signals
OCS1
FRMB frame
Generation signals
µPD16661A
SELF-DIAGNOSIS FUNCTION
This function check whether operation timing each column driver delayed external noise. slave chip compares master chip generated internally. When they mismatched, slave chip sends refresh signal column drivers. When refresh signal accepted, column drivers internally reset, timing initialized. this time, while REFRHB during 4frame cycle, display OFF. checked mismatch once every frame rising edge FRMB.
(Master) Mismatch (Master) (Slave) (Slave)
Mismatch
REFRHB Initialized Initialized
Block configuration (Slave side)
RESETB Internal reset
REFRHB Self-diagnosis circuit
Internal Signal Internal Signal
µPD16661A
SYSTEM CONFIGURATION EXAMPLE
example configuring liquid-crystal panel half-VGA size (480 across down) using four these LSIs drivers. Each column driver sets with PLO, pins. pins each column driver level. Only column drivers master; others slave. Signals supplied from master column driver slave column driver driver. Connect oscillator resistor OSC1 OSC2 pins master, leave these pins open slave. signals from system D15, A16, CSB, OEB, WEB, UBEB, RDY, RESETB, D0FFB) connected parallel column driver. Connect pull-up signal signal. TEST used test LSI, open grounded when system configured.
DOFFB RESETB Control CSB, WEB, UBEB OSC1 Master OSC2 Y160 Y160 Slave
FRMB
DOFFB REFRHB
driver
driver
Y160
Scan direction
Y160
Scan direction
Slave
Slave
µPD16661A
POWER SUPPLY SEQUENCE CHIP
recommended apply power following sequence. VCC2 input VCC1 VDD, sure apply drive voltages last.
VCC2 VCC1
Input
(A0-A16, CSB, DEB, WEB, UBEB, D0-D15, DOFFB)
more
RESETB VCC2 more
Note
more
Note
more
Notes need turned same time. Turn power chip reverse sequence power application sequence.
µPD16661A
EXAMPLE CONNECTING INTERNAL SCHOTTKY BARRIER DIODE MODULE REINFORCE POWER SUPPLY PROTECTION (Use Schottky barrier diode with less.)
VCC1
Connect diodes enclosed dotted line when (GND)
µPD16661A
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply Voltage Supply Voltage Input/Output Voltage Input/Output Voltage Input/Output Voltage Operating Temperature Storage Temperature Symbol VCC1 VCC2 VI/O1 VI/O2 VI/O3 Tstg Rating -0.5 -0.5 -0.5 VCC1 -0.5 VCC2 -0.5 VCC1 +125 Unit Note
signals (FRMB, STB, DOUTB, 3.3-V signals (MS, DIR, PL0-PL2, A0-A16, CSB, OEB, WEB, UBEB, RDY, D0-D15, RESETB, OSC1, OSC2, DOFEB, TEST1, GMODE, BMODE, REFRHB) Liquid-crystal drive powers (V0, Y1-Y160) Recommended Operating Range
Parameter Supply Voltage Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Voltage Input Voltage External Resistor Symbol VCC1 VCC2 ROSC MIN. TYP. MAX. VCC1 VCC2 VCC1 Unit Note
signals (FRMB, STB) 3.3-V signals (MS, DIR, PL0-PL2, A0-A16, CSB, OEB, WEB, UBEB, RDY, D0-D15, RESETB, OSC1, OSC2, DOFEB, TEST1, GMODE, BMODE, REFRHB)
µPD16661A
Characteristics (Unless otherwise specified, VCC1 VCC2
Parameter High-Level Input Voltage VCC1 Low-Level Input Voltage VCC1 High-Level Input Voltage VCC2 Low-Level Input Voltage VCC2 High-Level Input Voltage VCC2 Low-Level Input Voltage VCC2 High-Level Output Voltage VCC1 Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VCC1 -0.4 VCC2 VCC2 VCC2 VCC2 MIN. VCC1 VCC1 TYP. MAX. Unit Low-Level Output Voltage VCC1 High-Level Output Voltage VCC1 VOL1 VOH2 VCC1 -0.4 2mA*3 Low-Level Output Voltage VCC1 VOL2 VCC2 -0.4 Low-Level Output Voltage VCC2 Input Leakage Current VOL3 2mA*5 Other than TEST pin, VCC2 Pull-down (TEST pin) VCC2 Master, VCC1 Master, VCC2 Slave, VCC1 Slave, VCC2 Note
High-Level Output Voltage VCC2
VOH3
Input Leakage Current
Current Consumption Display Operation
IMAS1
Current Consumption Display Operation
IMAS2
Current Consumption Display Operation Current Consumption Display Operation Liquid-Crystal Driving Output Resistance
ISLV1
ISLV2
signals (FRMB, STB) 3.3-V signals (MS, DIR, PL0-PL2, A0-A16, CSB, OEB, WEB, UBEB, RDY, D0-D15, RESETB, DOFEB, TEST1, GMODE, BMODE) DOUTB REFRHB RDY, OSC2 pins With frame frequency without output load access D15, A16, UBEB GND, CSB, OEB, VCC2) This refers resistance value between (either when load current (ION passed Y160.
µPD16661A
Characteristics Display data transfer timing Master mode (Unless otherwise specified, VCC1 VCC2 frame frequency (fOSC 33.88 kHz), output load:
Parameter Clock Cycle Time High-Level Width Low-Level Width Rise Time Fall Time STB-FRMB Delay Time FRMB-STB Delay Time Symbol tCYC tCWH tCWL tPSF tPFS
tCYC tCWL (Output) tCWH VCC1 VCC1 tPSF FFMB (Output) tPFS tPSF tPFS VCC1 VCC1
MIN.
TYP. 2/fOSC 1/fOSC 1/fOSC
MAX.
Unit
Note
µPD16661A
Slave mode (Unless otherwise specified, VCC1 VCC2
Parameter Clock Cycle Time High-Level Width Low-Level Width Rise Time Fall Time FRMB Setup Time FRMB Hold Time Symbol tCYC tCWH tCWL tSFR tHFR MIN. TYP. MAX. Unit Note
tCYC tCWL (Input) tCWH VCC1 VCC1 tSFR FFMB (Input) tHFR tSFR tHFR VCC1 VCC1
µPD16661A
Items common master slaves (Unless otherwise specified, VCC1 VCC2
Parameter Output Delay Time (L1, DOUTB) Output Delay Time Y160) Symbol tDOUT1 tDOUT2 MIN. TYP. MAX. Unit Note Without output load Without output load
(Output)
VCC1
tDOUT1 DOUTB
tDOUT1 VCC1
tDOUT2
tDOUT2
Y160
µPD16661A
Characteristics Graphic access timing (Unless otherwise specified, VCC1 VCC2 frame frequency (fOSC 33.88 kHz))
Parameter OEB/WEB Recovery Time Address Setup Time Address Hold Time Output Delay Time Float Time Ready State Time (Without Contention) Ready State Time (With Contention) Data Access Time (Read Cycle) Data Float Time (Read Cycle) CSB-OEB Time (Read Cycle) OEB-CSB Time (Read Cycle) Write Pulse Width (Write Cycle) Data Setup Time (Write Cycle) Data Hold Time (Write Cycle) CSB-WEB Time (Write Cycle) WEB-CSB Time (Write Cycle) Reset Pulse Width RDY-OEB Time RDY-WEB Time Symbol tRYR tRYZ tRYF1 tRYF2 tACS tCSOE tOECS tCSWE tWECS tWRES tRDOE tRDWE MIN. 1200 TYP. MAX. Unit Note
Load circuit
VCC2
Load circuit
VCC2
Display affected time from rise long. tRDOE tRDWE recommended less than 1000
µPD16661A
OEB/WEB recovery time
OEB/WEB VCC2 VCC2
Read cycle
UBEB VCC2 tCSOE tRYR Hi-z VCC2 tACS Hi-z VCC2 VCC2 tRYF tRDOE tOECS VCC2 VCC2 tRYZ VCC2 VCC2 VCC2
µPD16661A
Write cycle
UBEB VCC2 tCSWE tRYR Hi-z VCC2 Hi-z VCC2 VCC2 tRYF tRDWE tWECS VCC2 VCC2 tRYZ VCC2 VCC2 VCC2
Reset pulse width When power
VCC2 tWRES RESETB VCC2
When power stabilized
RESETB VCC2 tWRES
µPD16661A
Characteristics oscillator (VCC2
Parameter Oscillation Frequency Frame Frequency Symbol FOSC MIN. 66.1 TYP. 74.4 MAX. 82.6 Unit Note External resistor External resistor
Relationship between oscillation frequency, frame frequency frequency relationship between oscillation frequency, frame frequency frequency follows: Frame frequency Oscillation frequency
frequency
Oscillation frequency
µPD16661A
REFERENCE
Semiconductor Device Reliability Quality Control System Semiconductor Device Mounting Technology Manual (IEI-1212) (C10535E)
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.

µPD16661A COLUMN (SEGMENT) DRIVER WITH BUILT-IN µPD16661A co

Top Searches for this datasheet

Other recent searches