Dual Video/Memory Clock Generator Integrated Circuit Systems ICS9

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Dual Video/Memory Clock Generator Integrated Circuit Systems ICS9

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ICS90C61A
Dual Video/Memory Clock Generator
Integrated Circuit Systems ICS90C61A dual clock generator applications. simultaneously generates clocks. clock video memory, other video clock. This data sheet supplies sales order information, functional overview, signal details, block diagram, AC/DC characteristics, timing diagrams, package mechanical information.
Features
Dual Clock generator IBM-compatible Western Digital Imaging Video Graphics Array (VGA) devices, 8514/A chip sets Integral loop filter components Generates seven video clock frequencies derived from 14.318 system clock reference frequency Video clock which selectable among seven internally generated clocks external clocks On-chip generation four memory clock frequencies CMOS technology Available 20-pin PLCC, SOIC, packages Extended frequency capabilities custom frequency patterns
Description
Integrated Circuit Systems Video Graphics Array Clock Generator (ICS90C61A) capable producing different output frequencies under firmware control. video output frequency derived from 14.318 system clock available PC/XT/AT Personal System/2 computers. designed work with Western Digital Imaging Video Graphics Array 8514/A devices optimize video subsystem performance. video clock output seven internallygenerated frequencies external inputs. selection video clock frequency done through four inputs. SEL0 SEL1 VGATTL FCLKSEL
Configuration
SEL0 SEL1 latched SELEN signal. VGATTL FCLKSEL used direct inputs VCLK selection. Table truth table VCLK selection. input truth table have been designed allow direct connection many Western Digital Imaging controllers 8514/A chip sets. MCLK output four internally-generated frequencies shown Table 1-2. various VCLK MCLK frequencies derived from 14.318 input frequency. VCLKE MCLKE input tristate VCLK MCLK outputs facilitate board level testing. ICS90C61A capable extended frequency output custom applications. page details.
20-Pin PLCC, SOIC J-4, J-7, J-10
Note: ICS90C61AN (DIP) pin-out identical ICS90C61AM (SOIC) pin-out.
90C61ARevA111095
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ICS90C61A
ICS90C61A Interface
ICS90C61A system interfaces: System Controller, user-programmable inputs. Figure shows Integrated Circuit Systems Clock ICS90C61A connected controller. Western Digital Imaging controllers normally have status that indicates controller that working with clock chip. When working with clock chip controller changes clock inputs, VCLK1 VCLK2, outputs. These outputs used select required video frequency.
Figure ICS90C61A Interface
Note: should placed close possible ICS90C61A AVCC pin.
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ICS90C61A
System Inputs
system inputs are: REFCLK SEL0 SEL1
Analog Filters
analog filters integral ICS90C61A device. external components required. This feature reduces board space requirements component costs. Phase jitter reduced externally-generated noise cannot easily influence phase-locked loop filter.
ICS90C61A uses system 14.318 clock reference generate frequencies both video memory clocks. Data lines commonly used inputs VSEL0 VSEL1 video frequency selection.
User-Definable Inputs
user-definable inputs are: EXTCLK FCLKIN VLCKE, MCLKE MSELO-1 VGATTL, FCLKSEL
Inputs from Controller
controller input ICS90C61A SELEN
ICS90C61A programmed generate different video clock frequencies using inputs SEL0, SEL1, VGATTL, FCLKSEL. signals VGATTL FCLKSEL supplied controller case Western Digital Imaging controllers. inputs SEL0-1 latched with signal SELEN. SELEN input should active pulse. This active pulse generated Western Digital Imaging controllers during writes internal register 3C2h. Note: Only SEL0 SEL1 latched with signal SELEN.
EXTCLK FCLKIN additional inputs that internally routed VCLK output. additional inputs useful supporting modes that require frequencies provided ICS90C61A. VCLKE MCLKE output enable signals VCLK MCLK.When low, respective output tristated. MSEL0-1 memory clock (MCLK) select lines. Table shows MCLK frequencies selected. signals this group have internal pull-up resistors. VGATTL FCLKSEL video clock (VCLK) select lines that select additional VCLK frequencies. Table 1-1.
Outputs Controller
outputs from ICS90C61A controller are: MCLK VCLK
MCLK VCLK clock outputs controller.
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ICS90C61A
Power Considerations
ICS90C61A product requires AVCC supply free fast rise time transients. This requirement several ways highly dependent characteristics host system. adapter card unique that must function unknown environment. volt power quality dependent only quality power supply resident host system, also other cards plugged into host's backplane. Power supply noise ranges from fair terrible. adapter manufacturer control over this, must assume worst. best solution create clean volts deriving from volt supply using zener diode dropping resister. resistor volt Zener diode least costly accomplish this. .047 microfarad bypass capacitor tied from AVCC AGND insures good high-frequency decoupling this point. Laptop notebook computers have entirely different problems with power. Typically they have volt supply; however, they much quieter electrically. Because designer complete control system architecture, place sensitive components systems such RAMDAC Dual Video/Memory Clock away from DRAM other noise-generating components. Most systems provide power that clean enough allow jitter-free Dual Video/Memory Clock performance volt supply decoupled with resistor microfarad Tantalum capacitor. Digital inputs that desired held static logical high level should tied volts this will result excessive current drain through protection diode. internal pull-up resistors will adequately keep these inputs high.
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ICS90C61A
Table VCLK SELECTION
FCLKSEL VGATTL SEL0 SEL1 VCLK FREQUENCY (MHz) ICS90C61A-PR2** REFCLK 16.108 32.216 44.744 25.057 28.089 EXTCLK* 36.242 FCLKIN*
Table MCLK SELECTION
MSEL1 MSEL0 MCLK FREQUENCIES (MHz) ICS90C61A-PR2** 41.612 37.585 36.242 44.744
*Note: FCLKIN EXTCLK programmed output custom frequencies applications which require this capability. Custom frequencies these addresses require significant volume committment and/or one-time mask charge. Contact Sales details. **Note: "dash number" specified, then "-PR2" will supplied since this version completely compatible with original WD90C61 frequency set.
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ICS90C61A
Figure ICS90C61A Functional Block Diagram
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ICS90C61A
Descriptions
following table provides descriptions 20-pin ICS90C61A packages: NUMBER Note: CLK1, EXTCLK, FCLKIN, SEL0, SEL1,VGATTL, FCLKSEL, SELEN, MSEL0, MSEL1, VCLKE, MCLKE input pins have internal pull-up resistors. SYMBOL REFCLK FCLKIN EXTCLK SEL0 SEL1 SELEN VGATTL FCLKSEL MSEL0 DGND MSEL1 MCLK MCLKE AVCC AGND VCLKE VCLK DVCC TYPE DESCRIPTION Reference input clock from system. Feature clock input pin. External clock input additional frequency. Control input VCLK selection. Control input VCLK selection. Strobe latching VSEL(0,1) (low enable). Control input VCLK selection. Control input FCLK selection. Select input MCLK selection. Ground Digital Circuit. Select input MCLK selection. Memory Clock Output. Connection. Enable input MCLK output (high enables output). Power supply analog circuit. Ground analog circuit. Connection. Enable input VCLK output (high enables output). Video Clock Output. Power supply Digital Circuit.
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ICS90C61A
Absolute Maximum Ratings
Ambient temperature under bias Storage temperature Voltage inputs outputs with respect 70°C -40°C 125°C volts
Standard Test Conditions
characteristics below apply following standard test conditions, unless otherwise noted. voltages referenced Ground). Positive current flows into referenced pin. Operating temperature range Power supply voltage 70°C 4.75 5.25 volts
Note: Stresses above those listed under Absolute Maximum Rating cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Characteristics
SYMBOL PARAMETER Input Voltage UNITS CONDITIONS PINS SEL0-1, SELEN, VGATTL, MSEL0-1, FCLKSEL, VCLKE, MCLKE, EXTCLK SEL0-1, SELEN, VGATTL, MSEL0-1, FCLKSEL, VCLKE, MCLKE, EXTCLK FCLKIN FCLKIN
Input High Voltage
ICCD ICCA Cout
Input Voltage Input High Voltage Input Leakage Current Output Voltage Output High Voltage Digital Supply Current Analog Supply Current Internal Pull-up Resistors Input Capacitance Output Capacitance
-1.5
ohms
15pF
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ICS90C61A
Timing Characteristics
following notes apply parameters presented this section. REFCLK 14.318 1/FC units nanoseconds (ns). Maximum jitter within range after triggering scope. Rise fall time between VDC. Output loading 15pF Duty cycle measured 1.4V
SYMBOL Tpwen Tsuen Thden
PARAMETER Enable Pulse Width Setup Time Data Enable Hold Time Data Enable Rise Time Fall Time
SELEN TIMING REFERENCE INPUT CLOCK
NOTES
Phase-Jitter max. Duty Cycle 42.5% min. 57.5% max. Phase-Jitter max. Duty Cycle 40%min. max.
MCLK VCLK TIMINGS Rise Time Fall Time Frequency Error Maximum Frequency Propagation Delay Pass Through Frequency Output Enable Tristate (into time
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ICS90C61A
Ordering Information
ICS90C61A-XXXN ICS90C61A-XXXM ICS90C61A-XXXV
Example:
XXXX-XXX
Package Type
N=DIP (Plastic) M=SOIC V=PLCC
Pattern Number digit number parts with code patterns)
Note: Unless specific pattern ordered, will shipped.
Device Type (consists digit numbers) Prefix
ICS, AV=Standard Device; GSP=Genlock Device
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Dual Video/Memory Clock Generator Integrated Circuit Systems ICS9

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