PARALLEL EEPROM WITH SOFTWARE DATA PROTECTION FAST ACCESS TIME: 9

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PARALLEL EEPROM WITH SOFTWARE DATA PROTECTION FAST ACCESS TIME: 9

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M28C64
PARALLEL EEPROM WITH SOFTWARE DATA PROTECTION
FAST ACCESS TIME: 90ns SINGLE SUPPLY VOLTAGE POWER CONSUMPTION FAST WRITE CYCLE: Bytes Page Write Operation Byte Page Write Cycle: ENHANCED WRITE DETECTION: Ready/Busy Open Drain Output (only M28C64) Data Polling Toggle PAGE LOAD TIMER STATUS HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY: Endurance >100,000 Erase/Write Cycles Data Retention Years JEDEC APPROVED BYTEWIDE SOFTWARE DATA PROTECTION DESCRIPTION M28C64 power Parallel EEPROM fabricatedwith SGS-THOMSON proprietary single polysilicon CMOS technology. device offers fast access time with power dissipation requires power supply.
A0-A12
PDIP28
PLCC32
SO28 (MS) mils
TSOP28 x13.4mm
Figure Logic Diagram
DQ0-DQ7
Table Signal Names
Address Input Data Input Output Write Enable Chip Enable Output Enable Ready Busy Supply Voltage Ground
M28C64
AI01350B
Note: function only available M28C64.
June 1996
1/19
M28C64
Figure Connections
Figure Connections
AI01351C
AI01352D
M28C64
M28C64 M28C64
AI01354C
Warning: Connected.
Warning: Connected, Don't Use.
Figure Connections
Figure TSOP Connections
M28C64
AI01353C
Warning: Connected. 2/19
Warning: Connected.
M28C64
Table Absolute Maximum Ratings
Symbol TSTG VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)
Value +0.6 4000
Unit
Notes: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also SGS-THOMSON SURE Program other relevant quality documents. 100pF through 1500; MIL-STD-883C, 3015.7
Figure Block Diagram
RESET
CONTROL LOGIC
DECODE
A6-A12 (Page Address)
ADDRESS LATCH
ARRAY
A0-A5
ADDRESS LATCH
DECODE
SENSE DATA LATCH
BUFFERS
PAGE LOAD TIMER STATUS TOGGLE DATA POLLING
AI01355
DQ0-DQ7
3/19
M28C64
Table Operating Modes
Mode Standby Output Disable Write Disable Read Write Hi-Z Hi-Z Hi-Z Data Data
Chip Erase
Note: VIL; VIH; VIH;
Hi-Z
DESCRIPTION (cont'd) M28C64 outputs Ready/Busy write status, M28C64-aaaX (aaa access time) Ready/Busy status relevant Connected (NC). circuit been designed offer flexible microcontroller interface featuring both hardware software handshaking with Ready/Busy, Data Polling Toggle Bit. M28C64 supports byte page write operation. Software Data Protection (SDP) also possible using standard JEDEC algorithm. DESCRIPTION Addresses (A0-A12). address inputs select 8-bit memory location during read write operation. Chip Enable (E). chip enable input must enable read/write operations. When Chip Enable high, power consumption reduced. Output Enable (G). Output Enable input controls data output buffers used initiate read operations. Data (DQ0 DQ7). Data written read from M28C64 through pins. Write Enable (W). Write Enable input controls writing data M28C64. Ready/Busy (RB). Ready/Busy open drain output that used detect internal write cycle (this function applies only M28C64).
OPERATION order prevent data corruption inadvertent writeoperations internal comparatorinhibits Write operation below (see Table Access memory write mode allowed after power-up specified Table Read M28C64 accessed like static RAM. When with high, data addressed presented pins. pins high impedance when either high. Write Write operations initiated when both high.The M28C64 supports both controlled write cycles. Address latched falling edge which ever occurs last Data rising edge which ever occurs first. Once initiated write operation internally timed until completion. Page Write Page write allows bytes consecutively latched into memory prior initiating programming cycle. bytes must located single page address, that A6-A12 must same bytes. page write initiated during byte write operation. Following first byte write instruction host send another address data with minimum data transfer rate 1/tWHWH (see Figure 13). transitionof detected within tWHWH, internal programming cycle will start.
4/19
M28C64
Chip Erase contents entire memory erased Chip Erase command setting Chip Enable Output Enable +7.0V. chip cleared when 10ms pulse applied Write Enable pin. Microcontroller Control Interface M28C64 provides write operation status bits status that used minimize system write cycle. These signals available port bits memory during programming cycle only, signal separate pin. Figure Status Assignment
PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP=Data Polling =Toggle PLTS=Page Load Timer Status
Data Polling (DQ7). During internal write cycle, attempt read last byte written will produce complementary value previously latched bit. Once write cycle finished true logic value appears read cycle. Toggle (DQ6). M28C64 offers another determining when internal write cycle completed. During internal Erase/Write cycle, will toggle from (the first read value "0") subsequent attempts read memory. When internal cycle completed toggling will stop device will accessible Read Write operation. Page Load Timer Status (DQ5). Page Write mode data latched
100µs after previous byte. bytes input. Data output (DQ5) indicates status internal Page Load Timer. read asserting Output Enable (tPLTS). indicates timer running, High indicates time-out after which write cycle will start data input. Ready/Busypin (available only M28C64). provides signal open drain output which during erase/write cycle, which released completion programming cycle. Software Data Protection M28C64 offers software controlled write protection facility that allows user inhibit write modes device including Chip Erase instruction. This useful protecting memory from inadvertent write cycles that occur uncontrolled conditions. M28C64 shipped standard "unprotected" state meaning that memory contents changed required user. After Software Data Protection enable algorithm issued, device enters "Protect Mode" operation where further write commands have effect memory contents. device remains this mode until valid Software Data Protection (SDP) disable sequence received whereby device reverts "unprotected" state. Software Data Protection fully nonvolatile changed power on/off sequences. enable Software Data Protection (SDP) device requires user write (with Page Write) three specific data bytes three specific memory locations Figure Similarly disable Software Data Protection user write specific data bytes into different locations Figure (with Page Write). This complex series ensures that user will never enable disable Software Data Protection accidentally.
5/19
M28C64
Figure Software Data Protection Enable Algorithm Memory Write
WRITE Address 1555h Page Write Instruction (Note Page Write Instruction (Note
WRITE Address 1555h
WRITE Address 0AAAh
WRITE Address 0AAAh
WRITE Address 1555h
WRITE Address 1555h WRITE enabled
Write Page bytes)
ENABLE ALGORITHM
WRITE MEMORY WHEN
AI01356B
Note: Address bits A12) differ during these specific Page Write operations.
Figure Software Data Protection Disable Algorithm
WRITE Address 1555h
WRITE Address 0AAAh
Page Write Instruction
WRITE Address 1555h
WRITE Address 1555h
WRITE Address 0AAAh
WRITE Address 1555h
Unprotected State
AI01357
6/19
M28C64
MEASUREMENT CONDITIONS
Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages 20ns 0.4V 2.4V 0.8V 2.0V
Figure Testing Equivalent Load Circuit
1.3V
1N914
Note that Output Hi-Z defined point where data longer driven.
3.3k
Figure Testing Input Output Waveforms
2.4V
DEVICE UNDER TEST 30pF
2.0V 0.8V
AI00826
0.4V
includes capacitance
AI01129
Table Capacitance
Symbol COUT Parameter Input Capacitance Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested.
Table Read Mode Characteristics 70°C 85°C; 4.5V 5.5V)
Symbol ICC1 ICC2
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL inputs) Supply Current (CMOS inputs)
Test Condition VIL, VIL, -0.3V
Unit
Supply Current (Standby) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage
-400
+0.5
Note: I/O's open circuit.
Table Power Timing 70°C 85°C)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once 4.5V) Write Inhibit Threshold Unit
Note: Sampled only, 100% tested.
7/19
M28C64
Table Read Mode Characteristics 70°C 85°C; 4.5V 5.5V)
Symbol Parameter Test Condition tAVQV tELQV tGLQV tEHQZ tGHQZ
M28C64 -120 -150 Unit
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
VIL, VIL,
tAXQX
Note: Output Hi-Z defined point which data longer driven.
Figure Read Mode Waveforms
A0-A12 tAVQV tGLQV tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA Hi-Z
AI00749B
Note: Write Enable High
8/19
M28C64
Table Write Mode Characteristics 70°C 85°C; 4.5V 5.5V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH1 tWHWH tWHRH tWHRL tEHRL tDVWH tDVEH tCES tOES tOES tWES tCEH tOEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Write Enable Input Valid Chip Enable Input Valid Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Write Enable High Ready/Busy Chip Enable High Ready/Busy Data Valid before Write Enable High Data Valid before Chip Enable High Note Note VIL, 0.15 Test Condition VIL, Unit
Note: With external pull-up resistor.
9/19
M28C64
Figure Write Mode Waveforms Write Enable Controlled
A0-A12 tAVWL tELWL tGHWL
VALID tWLAX
tWHEH
tWLWH1
tWHGL
tWLDV DQ0-DQ7 DATA tDVWH
tWHWL
tWHDX
tWHRL
AI01126
Figure Write Mode Waveforms Chip Enable Controlled
A0-A12 tAVEL tGHEL tWLEL
VALID tELAX
tELEH
tEHGL
tELDV DQ0-DQ7 DATA tDVEH tEHDX
tEHWH
tEHRL
AI00751
10/19
M28C64
Figure Page Write Mode Waveforms Write Enable Controlled
A0-A12
Addr
Addr
Addr
Addr
tPLTS tWHWL tWLWH DQ0-DQ7 Byte Byte tWHWH Byte tWHWH Byte tWHRH
tWHRL
Byte
AI00752C
Figure Software Protected Write Cycle Waveforms
tWLWH tAVEL A0-A5 tWHDX A6-A12 1555h tDVWH DQ0-DQ7 Byte Byte Byte
AI01358
tWHWL
tWHWH
tWLAX Byte Address
0AAAh
1555h
Page Address
Note: through must specify same page address during each high transition after software code been entered. must high only when both low.
11/19
M28C64
Figure Data Polling Waveform Sequence
A0-A12
Address last byte Page Write instruction
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI00753C
Figure Toggle Waveform Sequence
A0-A12
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI00754D
Note: First Toggle forced
12/19
M28C64
Figure Chip Erase Waveforms
tWHEH
tGLWH tELWL tWLWH2 tWHRH
AI01484B
Table Chip Erase Characteristics 70°C 85°C; 4.5V 5.5V)
Symbol tELWL tWHEH tWLWH2 tGLWH tWHRH Parameter Chip Enable Write Enable Write Enable High Chip Enable High Write Enable Write Enable High Output Enable Write Enable High Write Enable High Write Enable Test Condition Unit
13/19
M28C64
ORDERING INFORMATION SCHEME
Example:
M28C64
Speed -120 -150 90ns 120ns 150ns
Write Monitoring blank function active function
Package PDIP28 PLCC32 SO28 mils TSOP28 13.4mm
Temperature Range
Parts shipped with memory content "1's" (FFh). list available options (Speed, Package, Temperature Range, etc. refer current Memory Shortform catalogue. further information aspect this device, please contact SGS-THOMSON Sales Office nearest you.
14/19
M28C64
PDIP28 Plastic DIP, mils width
Symb
PDIP28
3.94 0.38 3.56 0.38 1.14 0.20 34.70 14.80 12.50 2.54 15.20 3.05 1.02 5.08 1.78 4.06 0.56 1.78 0.30 37.34 16.26 13.97 17.78 3.82 2.29 0.100
inches 0.155 0.015 0.140 0.015 0.045 0.008 1.366 0.583 0.492 0.598 0.120 0.040 0.200 0.070 0.160 0.021 0.070 0.012 1.470 0.640 0.550 0.700 0.150 0.090
PDIP
Drawing scale
15/19
M28C64
PLCC32 lead Plastic Leaded Chip Carrier, rectangular
Symb
PLCC32
2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 1.27 0.10 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.050
inches 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 0.004 0.140 0.095 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530
D2/E2
PLCC
Drawing scale
16/19
M28C64
SO28 lead Plastic Small Outline, mils body width
Symb
SO28
2.46 0.13 2.29 0.35 0.23 17.81 7.42 1.27 10.16 0.61 0.10 2.64 0.29 2.39 0.48 0.32 18.06 7.59 10.41 1.02 0.050
inches 0.097 0.005 0.090 0.014 0.009 0.701 0.292 0.400 0.024 0.004 0.104 0.011 0.094 0.019 0.013 0.711 0.299 0.410 0.040
SO-b
Drawing scale
17/19
M28C64
TSOP28 lead Plastic Thin Small Outline, 13.4mm
Symb
TSOP28
1.25 0.20 0.95 0.17 0.10 13.20 11.70 7.90 0.55 0.50 0.10 1.15 0.27 0.21 13.60 11.90 8.10 0.70 0.022
inches 0.049 0.008 0.037 0.007 0.004 0.520 0.461 0.311 0.020 0.004 0.045 0.011 0.008 0.535 0.469 0.319 0.028
TSOP-c
Drawing scale
18/19
M28C64
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics Rights Reserved SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil Canada China France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
19/19

PARALLEL EEPROM WITH SOFTWARE DATA PROTECTION FAST ACCESS TIME: 9

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