High-Speed CMOS High Speed CMOS Exchange Switches Bi-directional FIFO

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High-Speed CMOS High Speed CMOS Exchange Switches Bi-directional FIFO

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QS725420A PRELIMINARY
High-Speed CMOS High Speed CMOS Exchange Switches Bi-directional FIFO
QS3383 QS32383 QS725420A
Fast cycle times: 20/25/30/35 36-bit FIFO buffers Full 36-bit word width Selectable 36/18/9-bit word width port Fully asynchronous operation port port Synchronous control both ports Enable, request, address control inputs sampled rising clock edge Synchronous request/acknowledge "handshake" capability Device comes into known default state reset Asynchronous output enables
Five status flags port: Full, Almost-Full, Half-Full, Almost-Empty, Empty Almost-Full flag Almost-Empty flag programmable Mailbox registers with synchronized flags Data-retransmit function Automatic byte parity checking three-state outputs CMOS-compatible Space-saving PQFP TQFP packages Pin-compatible functionally equivalent Sharp LH5420 LH543601
DESCRIPTION
QS725420A contains FIFO buffers, FIFO FIFO These operate parallel, opposite directions, bi-directional data buffering. FIFO FIFO each organized words bits. QS725420A ideal either wide unidirectional applications bi-directional data applications where component count board area need reduced. QS725420A 36-bit ports, port port Each port port-synchronous clock, ports operate asynchronously relative each other. Data flow initiated port rising edge appropriate clock; gated corresponding edge-sampled enable, request, read/write control signals. maximum operating frequency, clock duty cycle vary from 60%. lower frequencies, clock waveform quite asymmetric, long minimum pulse-width conditions clock-HlGH clock-LOW remain satisfied; QS725420A fully static part.
FIGURE
FUNCTIONAL BLOCK DIAGRAM
WRITE PORT
FIFO
READ PORT
READ
FIFO
WRITE
PORT CONTROL
PORT CONTROL
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY DESCRIPTION (Continued)
Conceptually, port clocks free-running, periodic "clock" waveforms, used control other signals which edge-sensitive. However, there actually absolute requirement that these "clock" waveforms must periodic. "asynchronous" mode operation possible, both directions, independently, appropriate enable request inputs continuously asserted, enough aperiodic "clock" pulses suitable duration generated external logic cause necessary actions occur. synchronous request/acknowledge handshake facility provided each port FIFO data access. This request/acknowledge handshake resolves FIFO full empty boundary conditions when ports operated asynchronously relative each other. FIFO status flags monitor extent which each FIFO buffer been filled. Full, Almost-Full, Half-Full, Almost-Empty, Empty flags included each FIFO. Almost-Full Almost-Empty flags programmable over entire FIFO depth, automatically initialized eight locations from respective FlFO boundaries reset. data block fewer words retransmitted desired number times. mailbox registers provide separate path passing control words status words between ports. Each mailbox new-mail-alert flag, which synchronized reading port's clock. This mailbox function facilitates synchronization data transfers between asynchronous systems. Data-bypass mode allows Port directly transfer data from Port reset. this mode, device acts registered transceiver under control Port instance, master processor Port data bypass feature send receive initialization configuration information directly, from peripheral device Port during system startup. word-width-select option provided Port 36-bit, 18-bit, 9-bit data access. This feature allows word-width matching between Port Port with additional logic needed. also ensures maximum utilization bandwidths. byte parity check flag each port monitors data integrity. Control-register (zero) selects parity mode, even. This initialized data parity reset; reprogrammed even parity, back again parity, desired.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE FUNCTIONAL BLOCK DIAGRAM
BYPASS
MBF1 MBF2
MAILBOX REGISTER
COMMAND PORT REGISTER COMMAND PORT REGISTER RESET LOGIC
MAILBOX REGISTER
FIFO MEMORY ARRAY
PORT SYNCHRONOUS CONTROL LOGIC PORT SYNCHRONOUS CONTROL LOGIC R/WB REQB ACKB
R/WA REQA ACKA
WRITE POINTER
READ POINTER
FIXED PROGRAMMABLE STATUS FLAGS
FIXED PROGRAMMABLE STATUS FLAGS
D35A-D0A READ POINTER PORT WRITE POINTER PORT
D35B-D0B WS0,
PARITY CHECKING
FIFO MEMORY ARRAY
PARITY CHECKING
RESOURCE REGISTERS
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE PINOUTS 132-Pin Quad Flat Package (Top view)
VCCO D10A VSSO VCCO VSSO
VSSO VCCO VSSO D10B D11B VCCO
D11A D12A D13A D14A VSSO D15A D16A D17A R/WA REQA ACKA MBF2 D18A D19A VSSO D20A D21A D22A D23A
VCCO D24A D25A D26A VSSO D27A D28A D29A VCCO D30A D31A D32A VSSO D33A D34A D35A D35B D34B VSSO D33B D32B D31B VCCO D30B D29B D28B VSSO D27B D26B D25B VCCO
D12B D13B D14B D15B VSSO D16B D17B MBF1 ACKB REQB R/WB D18B D19B D20B VSSO D21B D22B D23B D24B
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE PINOUTS 144-Pin Quad Flat Package (Top view)
VCCO D10A VSSO VCCO VSSO VSSO VCCO VSSO D10B D11B VCCO
D23A D22A D21A D20A VSSO D19A D18A MBF2 ACKA REQA R/WA D17A D16A D15A VSSO D14A D13A D12A D11A
VCCO D24A D25A D26A VSSO D27A D28A D29A VCCO D30A D31A D32A VSSO D33A D34A D35A D35B D34B VSSO D33B D32B D31B VCCO D30B D29B D28B VSSO D27B D26B D25B VCCO
MDSF-00018-01
APRIL 1995
D24B D23B D22B D21B VSSO D20B D19B D18B R/WB REQB ACKB MBF1 D17B D16B VSSO D15B D14B D13B D12B
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY DESCRIPTION
Signal Name D17A D16A D15A D14A D13A D12A D11A D10A PQFP TQFP Signal Name ACKB REQB R/WB D18B D19B D20B D21B D22B D23B D24B D25B D26B D27B D28B D29B D30B D31B D32B D33B D34B D35B D35A D34A D33A D32A D31A D30A D29A D28A D27A D26A D25A D24A D23A D22A D21A PQFP TQFP Signal Name D20A D19A D18A MBF2 ACKA REQA R/WA VSSO VCCO VSSO VCCO VSSO VSSO VCCO VSSO VCCO VSSO VSSO VCCO VSSO VCCO VSSO VSSO VCCO VSSO VCCO VSSO PQFP TQFP
NOTES: Supply internal logic. Connected each other. VCCO Supply output drivers only. Connected each other.
D10B D11B D12B D13B D14B D15B D16B D17B MBF1
Supply internal logic. Connected each other. VSSO Supply output drivers only. Connected each other.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY DESCRIPTION
Name Vcc, Type(1) I/O/Z I/O/Z Description GENERAL Power, Ground Reset PORT R/WA A0A, A1A, Port Free-Running Clock Port Edge-Sampled Read/Write Control Port Edge-Sampled Enable Port Edge-Sampled Address Pins Port Level-Sensitive Output Enable Port Request/Enable FIFO Retransmit Port Bi-directional Data FIFO Full Flag (Write Boundary) FIFO Programmable Almost-Full Flag (Write Boundary) FIFO Half-Full Flag FIFO Programmable Almost-Empty Flag (Read Boundary) FIFO Empty Flag (Read Boundary) New-Mail-Alert Flag Mailbox Port Parity Flag Port Acknowledge PORT R/WB Port Free-Running Clock Port Edge-Sampled Read/Write Control Port Edge-Sampled Enable Port Edge-Sampled Address Port Level-Sensitive Output Enable Port Word-Width Select Port Request/Enable FIFO Retransmit Port Bi-directional Data FIFO Full Flag (Write Boundary) FIFO Programmable Almost-Full Flag (Write Boundary) FIFO Half-Full Flag FIFO Programmable Almost-Empty Flag (Read Boundary) FIFO Empty Flag (Read Boundary) New-Mail-Alert Flag Mailbox Port Parity Flag Port Acknowledge
REQA
D35A-D0A
MBF2
ACKA
WS0, REQB
D35B-D0B
MBF1
ACKB
NOTES: Power Voltage Level, Input, Output, High Impedance.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY ABSOLUTE MAXIMUM RATINGS
Supply Voltage Ground -0.5V +7.0V Input Voltage VIN(1) .-0.5V 0.5V Output Current Max. Sink Current/Pin(2) Maximum Power Dissapation Temperature Range with Power Applied -55° +125°C TSTG Storage Temperature -65° +125°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional- reliability-type failures.
Notes: Negative undershoot 1.5V amplitude permited once cycle. Only output shorted time, period exceeding Seconds.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Input HIGH Voltage Input Voltage(1) Output HIGH Voltage Output Voltage Leakage Input Leakage Test Conditions Logic HIGH Inputs Logic Inputs VOUT VCC, 5.5V, -0.5 Units
Note: Negative undershoot 1.5V amplitude permited once cycle.
POWER SUPPLY CHARACTERISTICS
Symbol ICC2 ICC3 Parameter Operating Current Max.
(1,2)
Units
Standby Current(1) Inputs VIHMIN (Clocks Idle) Power Down Current(1) Inputs 0.2V (Clocks Idle) Power Down Current(1) Inputs 0.2V (Clocks Max.)
ICC4
Notes: ICC, ICC2, ICC3, ICC4 dependent upon actual output loading, ICC4 also dependent cycle rates. Specified values with outputs open (for ICC: CLSD pF); and, ICC4, operating minimum cycle times. using worst case conditions data pattern.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY
TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times (10% 90%) Input Timing Reference Levels. 1.5V Output Reference Levels 1.5V Output Load
FIGURE
OUTPUT LOAD CIRCUIT
OUTPUT
Includes scope capacitances.
CAPACITANCE
25°C, Name COUT Description(1) Input Capacitance Output Capacitance Conditions VOUT Units
Note: Capacitance guaranteed tested.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY ELECTRICAL CHARACTERISTICS (0°C 70°C, 10%)
Symbol tRWS tRWH tRQS tRQH tACK tMBF tRSS tRSH tFRL tFWL Parameter(1) Clock Cycle Frequency Clock Cycle Time Clock HIGH Time Clock Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Read/Write Setup Time Read/Write Hold Time Request Setup Time Request Hold Time Address Setup Time(6) Address Hold Time(6) Data Output Access Time Acknowledge Access Time Output Hold Time(6) Output Enable Time(2) D35-D0 LOW-Z Output Disable Time(2) HIGH D35-D0 HIGH-Z Clock Flag Valid (Empty Flag) 17.6 Clock Flag Valid (Full Flag) 17.6 Clock Flag Valid (Half-Full Flag) 17.6 Clock Flag Valid (Almost-Empty Flag) Clock Flag Valid (Almost-Full Flag) Clock Flag Valid (Mailbox Flag) Data Parity Flag Valid 13.6 Reset/Retransmit Pulse Width 32/20 Reset/Retransmit Setup Time(3) Reset/Retransmit Hold Time(3) Reset Flag Valid First Read Latency(4) First Write Latency(5) Bypass Data Setup Bypass Data Hold Bypass Data Access 10.4 10.4 12.8 Speed (ns) Units 28.5 40/25
52/30 65/35
Notes: Timing measurements performed TEST CONDITION levels. Values guaranteed design, currently production tested. tRSS and/or tRSH need unless rising edge occurs while being asserted, else rising edge occurs while being asserted. tFRL minimum first-write-to-first-read delay, following empty condition, which required assure valid read data. tFWL minimum first-read-to-first-write delay, following full condition, which required assure successful writing data. tAS, address setup times hold times need only satisfied clock edges which occur while corresponding enables being asserted. First number used only when enabled: tRSS tRSH.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY OPERATIONAL DESCRIPTION
Reset device reset whenever asynchronous reset (RS) input taken LOW, least rising edge falling edge both CLKA CLKB occur while LOW. reset operation required after powerup, before first write operation occur. QS725420A fully ready operation after being reset. device programming required default states described below acceptable. reset operation initializes read-address write-address pointers FIFO FIFO those FlFOs' first physical memory locations. respective outputs enabled, initial contents these first locations appear outputs. FIFO mailbox status flags updated indicate empty condition. addition, programmable-status-flag offset values initialized eight. Thus, AE1/AE2 flags asserted within eight locations empty condition, AF1/AF2 flags likewise asserted within eight locations full condition, FIFO #1/FIFO respectively. Bypass Operation During reset (whenever LOW) device acts registered transceiver, bypassing internal FIFO memories. Port acts master port. write read operation port during reset transfers data directly from port Port considered slave, cannot perform write read operations independently during reset. direction bypass data transmission determined R/WA control input, which does overridden input. Here, "write" operation means passing data from Port Port a"read" operation means passing data from Port Port bypass capability used pass initialization configuration data directly between master processor peripheral device during reset. Address Modes Address pins select device resource accessed each port. Port three resourceregister-select inputs, which select between FIFO access, mailbox-register access, control-register access (write only), programmable flag-offset-value register access. Port single address input, A0B, select between FIFO access mailbox-register access. status resource-register-select inputs sampled rising edge enabled clock (CKA CKB). Resource-register select-input address definitions summarized Table FIFO Write Port writes FlFO port writes FlFO write operation initiated rising edge clock (CKA CKB) whenever appropriate enable (ENA ENB) held HIGH; appropriate request (REQA REQB) held HIGH; appropriate read/ write control R/WB) held LOW; FIFO address selected address inputs (A2A-A0A A0B); prescribed setup times hold times observed these signals. Setup times hold times must also observed data-bus pins (D0A-D35A D0B-D35B). TABLE RESOURCE-REGISTER ADDRESSES Resource FIFO Mailbox
PORT
AF2, AE2, AF1, Flag
Offset Registers (36-bit Mode) Control Registers (Parity Mode)
Flag Offset Registers Flag Offset Registers Flag Offset Registers
Flag Offset Registers Resource
PORT FIFO Mailbox
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY
Normally, appropriate output enable signal (OEA OEB) HlGH, disable outputs that port, that data word present from external sources gets stored. However, "loopback" mode operation also possible, which data word supplied outputs internal FlFO "turned around" port read back into other FlFO. this mode, outputs port disabled. remain within specification timing parameters, clock cycle frequency must reduced slightly below value which otherwise would permissible that speed grade QS725420A. When FIFO full condition reached, write operations locked out. Following first read operation from full FIFO, another memory location freed corresponding full flag de-asserted HIGH). first write operation should begin earlier than first write latency (tFWL) after first read operation from full FIFO, ensure that correct read data retrieved. FIFO Read Port reads from FlFO port reads from FlFO read operation initiated rising edge clock (CKA CKB) whenever appropriate enable (ENA ENB) held HIGH; appropriate request (REQA REQB) held HIGH; appropriate read/write control (R/WA held HIGH; FIFO address selected address inputs (A2A-A0A A0); prescribed setup times hold times observed these signals. Read data becomes valid data-bus pins (D35A-D0A D35B-D0B) time after rising clock (CKA CKB) edge, provided that data outputs enabled.
assertive LOW, asynchronous, output enable control input signals. Their effect only enable disable output drivers respective port. Disabling outputs does disable read operation; data transmitted corresponding output register will remain available later, when outputs again enabled, unless subsequently overwritten.
When empty condition reached, read operations locked until valid write operation(s) loaded additional data into FlFO. Following first write empty FIFO, corresponding empty flag (EF) will asserted (HIGH). first read operation should begin earlier than first read latency (tFRL) after first write empty FIFO, ensure that correct read data retrieved. Dedicated FIFO Status Flags dedicated FIFO status flags included full FF2), half-full HF2), empty EF2). indicate status FIFO FF2, HF2, indicate status FIFO Full flag asserted following rising clock edge write operation that fills FIFO. Full flag deasserted following falling clock edge read operation full FIFO. Half-Full flag updated following rising clock edge read write operation FIFO. Empty flag asserted following rising clock edge read operation that empties FIFO. Empty flag de-asserted following falling clock edge write operation empty FlFO. Programmable Status Flags Four programmable FIFO status flags provided: almost-full AF2), almost-empty (AE1 AE2). Thus, each port programmable flags monitor status internal FIFO buffer memories. offset values these flags initialized eight locations from respective FIFO boundaries during reset reprogrammed over entire FIFO depth. Almost-Full flag asserted following rising clock edge write operation that fills FIFO. Almost-Full flag de-asserted following falling clock edge read operation full FlFO. AlmostEmpty flag asserted following rising clock edge read operation that empties FIFO. AlmostEmpty flag de-asserted following falling clock edge write operation empty FIFO.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY
Flag offsets written read through port data bus. four programmable FIFO status flag offsets simultaneously through single 36-bit status word, each programmable flag offset individually through four 8-bit status words. Table illustrates data format flag-programming words Also, Table defines meaning each five flags, both dedicated flags flagprogramming flags, QS725420A. WARNING: Control inputs which affect computation flag values port generally should change while clock that port HIGH, since some updating flag values takes place falling edge clock. Mailbox Operation mailbox registers provided passing system hardware software control/status words between ports. Each port read mailbox write other port's mailbox. Mailbox access performed rising edge controlling FlFO's clock, with mailbox address selected enable HIGH. That writing mailbox register reading from mailbox register synchronized CKA; writing mailbox register reading from mailbox register synchronized CKB. R/WA/B OEA/B pins control direction availability mailbox-register accesses. Each mailbox register New-Mail-Alert Flag (MBF1 MBF2), which synchronized reading port's clock. These new-mail-alert flags status indicators only cannot inhibit mailbox-register read write operations. Request/Acknowledge Handshake synchronous, request/acknowledge handshake feature provided each port, perform boundary synchronization between asynchronous-operated ports. this feature optional. When used, request input (REQA/B) sampled rising clock edge. With REQA/B HIGH, R/WA/B determines whether FIFO read operation FIFO write operation being requested. acknowledge output (ACKA/B) updated during following clock cycle(s). ACKA/B meets setup hold time requirements enable input (ENA ENB). Therefore, ACKA/B tied back enable input directly gate FIFO accesses, slight decrease maximum operating frequency. assertion ACKA/B signifies that REQA/B asserted. However, ACKA/B does depend logically ENA/B; thus assertion ACKA/B does prove that FIFO write access FIFO read access actually took place. While REQA/B being held HIGH, ACKA/B considered synchronous, predictive boundary flag. That ACKA/B acts synchronized predictor Almost-Full flag write operations, synchronized predictor Almost-Empty flag read operations. Outside "almost-full" region "almost-empty" region, ACKA/B remains continuously HIGH whenever REQA/B held continuously HIGH. Within "almost-full" region "almost-empty" region, ACKA/B occurs only every third cycle, prevent overrun FlFO's actual full empty boundaries, ensure that tFWL (first-write latency) tFRL (first-read latency) specifications satisfied before ACKA/B received. "almost-full region" defined "that region, where Almost-Full flag being asserted"; "almost-empty region" "that region, where Almost-Empty flag being asserted." Thus, extent these "almost" regions depends system programmed offset values Almost-Full flags Almost-Empty flags. system programmed them, then these offset values remain their default values, eight each case. write attempt unsuccessful because corresponding FlFO full, read attempt unsuccessful because corresponding FIFO empty, ACKA/B asserted response REQA/B. REQ/ACK handshake used, then REQA/B input used second enable input, possible minor loss maximum operating speed. this case, ACKA/B output ignored. WARNING: Whether REQ/ACK handshake being used, REQA/B input port must asserted corresponding FIFO operate. MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY
Data Retransmit retransmit operation resets read-address pointer corresponding FIFO back first FIFO physical memory location, that data reread. write pointer affected. status flags updated, block data words, which previously been written into read from FIFO, retrieved. block retransmitted bounded first FIFO memory location FIFO memory location addressed write pointer. FIFO retransmit initiated strobing LOW. FIFO retransmit initiated strobing LOW. Read write operations FIFO should stopped while corresponding retransmit signal being asserted. Parity Check Parity check flags, PFB, asserted (LOW) whenever there parity error data word present port data port data bus, respectively. inputs parity-evaluation logic come directly (via isolation transistors) from data-bus bonding pads, each case. Thus, provide parity-error indications whatever 36-bit words present port port respectively, regardless whether these words originated within QS725420A external system. four bytes 36-bit data word grouped D0-D8, D9-D17, D18-D26, D27-D35. parity each 9-bit byte individually checked, four single-bit parity indications logically inclusive-ORed produce parity-flag output. Parity checking initialized parity reset, reprogrammed even parity parity during operation. Control-register (zero) selects parity mode, even (see Table nine bits each byte treated alike parity logic. byte parity over nine bits compared with parity mode control register, generate byte-parity-error indication. Then, four byteparity-error signals NORed together compute assertive-LOW parity-flag value. Word-Width Selection Port word width data access Port selected control inputs. both tied HIGH 36-bit access; they both tied single-byte access. double-byte access, tied HIGH tied LOW. single byte-access double-byte access modes, FIFO write operations port essentially pack data form 36-bit words, viewed from port Similarly, single-byte double-byte FIFO read operations port essentially unpack 36-bit words through series shift operations. FIFO status flags updated following last access which forms complete 36-bit transfer. Since values each status flag computed logic directly associated with FlFOmemory arrays, logic associated with port flag values reflect array fullness situation terms complete 36-bit words, terms bytes double bytes. However, there such restriction switching from writing reading, from reading writing, port long tRWS, tDS, satisfied, R/WB change state after single-byte double-byte access, only after full 36-bit-word access. Also, word-width-matching feature continues operate properly "loopback" mode. Note that programmable word-width-matching feature only supported FlFO accesses. Mailbox data bypass operations support word-width matching between port port Tables Figures summarize word-width selection Port TABLE PORT WORD-WIDTH SELECTION Port Data Width 36-Bit (Reserved) 18-Bit 9-Bit
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY TABLE RESOURCE-REGISTER PROGRAMMING
ResourceRegister Address
D35A
Resource-Register Contents
NORMAL FIFO OPERATION
MAILBOX
D35A
AF2, AE2, AF1, FLAG REGISTER (36-BIT MODE)
D35A
Offset(1)
D34A-D27A
D26A
Offset(1)
D25A-D18A
D17A
Offset(1)
D16A-D9A
Offset(1)
D7A-D0A
CONTROL REGISTER (WRITE-ONLY) PARITY
D35A
8-BIT FLAG OFFSET REGISTER
D35A
Parity Mode
8-BIT FLAG OFFSET REGISTER
D35A
Offset(1) Offset(1) Offset(1)
D7A-D0A D7A-D0A D7A-D0A
D7A-D0A
8-BIT FLAG OFFSET REGISTER
D35A
8-BIT FLAG OFFSET REGISTER
Offset(1) Notes: four programmable-flag offset values initialized eight during reset operation. parity HIGH; even parity LOW. parity mode initialized during reset operation.
D35A
TABLE
FLAG DEFINITION TABLE(1)
Valid Full-Word Read Cycles Remaining Valid Full-Word Write Cycles Remaining Flag Flag HIGH Flag Flag HIGH
Flag
Note: Programmable almost-empty offset value (default value: Programmable almost-full offset value (default value:
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE 36-18 FUNNELING THROUGH FIFO
36-Bit Data Stream D35A Bits 35-18 (2nd Halfword) 18-Bit Data Stream D35B
D18A PORT
alfw
D18B
Halfword, then Halfword
17-0 Bits lfword (1st
D17B
PORT
D17A
Bits 17-0 (1st Halfword)
Halfword, then Halfword
FIGURE 36-9 FUNNELING THROUGH FIFO
36-Bit Data Stream D35A 9-Bit Data Stream D35B
D27A PORT D26A
Bits 35-27 (4th Byte)
D27B
Byte, then Byte, then Byte, then Byte
PORT D26B Bits 26-18 (3rd Byte)
D18A
D18B
Byte, then Byte, then Byte, then Byte
D17A
D17B
Bits 17-9 (2nd Byte)
Byte, then Byte, then Byte, then Byte
Bits (1st Byte)
Byte, then Byte, then Byte, then Byte
Notes: heavy black borders register segments indicate main data path, suitable most applications. Alternate paths feature different ordering bytes within word, port funneling process does change ordering bits within byte. Halfwords (Figure bytes (Figure transferred parallel form from port port word-width setting changed during system operation; however, clock intervals should allowed these signals settle before again attempting read data D35-D0, three dummy words should passed through initially. Also, incomplete data words occur when word width changed from shorter longer inappropriate point data block passing through FIFO.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE 18-36 DEFUNNELING THROUGH FIFO
36-Bit Data Stream D35A 18-Bit Data Stream D35B
D18A PORT
alfw
D18B PORT
D17A
D17B
Bits 17-0 (1st Halfword)
Halfword, then Halfword
FIGURE 9-36 DEFUNNELING THROUGH FIFO
36-Bit Data Stream D35A 9-Bit Data Stream D35B
D27A PORT D26A
Bits 35-27 (4th Byte)
D27B PORT D26B
D18A
Bits 26-18 (3rd Byte)
D18B
Byte, then Byte, then Byte, then Byte
D17A
D17B
Bits 17-9 (2nd Byte)
Bits (1st Byte)
Notes: heavy black borders register segments indicate only data paths used. other byte seqments port participate data path during defunneling. funneling process does change ordering bits within byte. Halfwords (Figure bytes (Figure transferred parallel form from port port word-width setting changed during system operation; however, clock intervals should allowed these signals settle before again attempting send data, three dummy words should passed through initially. Also, incomplete data words occur when word width changed from shorter longer, inappropriate point data block passing through FIFO.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY TIMING DIAGRAMS FIGURE RESET TIMING
Notes: overrides other input signals, except R/WA, operates asynchronously. operates whether and/or asserted. However, least rising edge falling edge both must occur while being asserted LOW), with timing defined tRSS tRSH. Otherwise, tRSS, tRSH need unless rising edge and/or occurs while that clock enabled. parity check initialized odd-byte parity reset. flag offsets initialized eight locations from boundary reset.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE DATA BYPASS TIMING
R/WA
D35-D0B
BYPASS DATA
BYPASS
D35-D0A
PREVIOUS DATA BYPASS
BYPASS
Notes: tRSS, tRSH need unless rising edge and/or occurs while that clock enabled. Port considered master port bypass operation. Thus, CKA, control transmission data between ports reset.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE PORT FIFO READ/WRITE
READ FROM FIFO R/WA WRITE FIFO
D35-D0A
PREVIOUS DATA DATA DATA
VALID VALID
VALID
Notes: port parity error flag (PFA) reflects parity status data present data bus. status does gate read write operations. left during write operation, then previous data held output latch written back into FIFO
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE PORT FIFO READ/WRITE
READ FROM FIFO R/WB WRITE FIFO
PREVIOUS DATA DATA DATA
D35-D0B
VALID VALID
VALID
Notes: port parity error flag (PFB) reflects parity status data present data bus. status does gate read write operations. left during write operation, then previous data held output latch written back into FIFO
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE PORT MAILBOX ACCESS
WRITE MAILBOX R/WA READ FROM MAILBOX
MBF2
MAXIMUM CYCLES LATENCY
MBF1
D35-D0A
MAILBOX
MAILBOX
Notes: Both edges MBF2 synchronized port clock, CKA. Both edges MBF1 synchronized port clock, CKB. There maximum clock cycles synchronization latency before MBF1 asserted indicate valid mailbox data. status mailbox flags does prevent mailbox read write operations.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE PORT MAILBOX ACCESS
WRITE MAILBOX R/WB READ FROM MAILBOX
MBF1
MAXIMUM CYCLES LATENCY
MBF2
D35-D0B
MAILBOX
MAILBOX
Notes: Both edges MBF2 synchronized port clock, CKA. Both edges MBF1 synchronized port clock, CKB. There maximum clock cycles synchronization latency before MBF2 asserted indicate valid mailbox data. identical there maximum clock cycle. status mailbox flags does prevent mailbox read write operations.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE FLAG PROGRAMMING
LOAD FLAG POSITIONS R/WA READ FLAG POSITIONS
D35-D0A
FLAG DATA
FLAG DATA
AE1, AE3,
Notes: valid flag address codes data formats, flag programming words table. flag status altered flag programming, updated flags will valid within time tRF. control register loaded shown here, with A2A, A1A, HLL. However, available reading back.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE EMPTY FLAG TIMING
(CKB) R/WA (R/WB) (ENB)
(EF1)
(CKA)
R/WB (R/WA)
(ENA)
Notes: A2A, A1A, A0A, held HIGH FIFO access port held HIGH FIFO access port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation.
FIGURE ALMOST-EMPTY FLAG TIMING
(CKB) R/WA (R/WB) (ENB)
(AE1)
(CKA)
R/WB (R/WA) (ENA)
Notes: A2A, A1A, A0A, held HIGH FIFO access port held HIGH FIFO access port Parameters without parentheses apply FIFO operation. Parameters with parentheses apply FIFO operation.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE FULL FLAG TIMING
(CKB) R/WA (R/WB) (ENB)
(FF1)
(CKA) R/WB (R/WA) (ENA)
Notes: A2A, A1A, held HIGH FIFO access port held HIGH FIFO access port Parameters without parentheses apply FIFO Parameters with parentheses apply FIFO
FIGURE ALMOST-FULL FLAG TIMING
(CKB) R/WA (R/WB) (ENB)
(AF1)
(CKA) R/WB (R/WA) (ENA)
Notes: A2A, A1A, held HIGH FIFO access port held HIGH FIFO access port Parameters without parentheses apply FIFO Parameters with parentheses apply FIFO
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE HALF-FULL FLAG TIMING
(CKB) R/WA (R/WB) (ENB)
(HF1)
(CKA)
R/WB (R/WA) (ENA)
Notes: A2A, A1A, held HIGH FIFO access port held HIGH FIFO access port Parameters without parentheses apply FIFO Parameters with parentheses apply FIFO
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE FIFO RETRANSMIT TIMING
R/WB
R/WA
Notes: tRSS tRSH need unless rising edge occurs while clock enabled. tRSS time needed deassert before returning normal FIFO cycle. tRSH time needed before asserting after normal FIFO cycle. Read write operations FIFO should disabled while being asserted.
FIGURE FIFO RETRANSMIT TIMING
R/WA
R/WB
Notes: tRSS tRSH need unless rising edge occurs while clock enabled. tRSS time needed de-assert before returning normal FIFO cycle. tRSH time needed before asserting after normal FIFO cycle.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE FIFO WRITE READ OPERATION NEAR-EMPTY REGION
R/WA
D35A-D0A
R/WB D35B-D0B PREVIOUS DATA
Notes: A2A, A1A, A0A, held HIGH FIFO access. held HIGH. held LOW. tFRL (first-read latency) first read following empty condition begin earlier than tFRL after first write empty FIFO, ensure that valid read data retrieved.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE FIFO WRITE READ OPERATION NEAR-EMPTY REGION
R/WB
D35B-D0B
R/WA D35A-D0A PREVIOUS DATA
Notes: A2A, A1A, A0A, held HIGH FIFO access. held HIGH. held LOW. tFRL (first-read latency) first read following empty condition begin earlier than tFRL after first write empty FIFO, ensure that valid read data retrieved.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE FIFO WRITE READ OPERATION NEAR-FULL REGION
R/WA
D35A-D0A
R/WB D35B-D0B PREVIOUS DATA
Notes: A2A, A1A, A0A, held HIGH FIFO access port held HIGH FIFO access port held HIGH. held LOW. tFWL (first-write latency) first write following full condition begin earlier than tFWL after first read from full FIFO, ensure that valid write data written.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE FIFO WRITE READ OPERATION NEAR-FULL REGION
R/WB
D35B-D0B
R/WA D35A-D0A PREVIOUS DATA
Notes: A2A, A1A, A0A, held HIGH FIFO access port held HIGH FIFO access port held HIGH. held LOW. tFWL (first-write latency) first write following full condition begin earlier than tFWL after first read from full FIFO, ensure that valid write data written.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE PORT DOUBLE-BYTE FIFO READ ACCESS 36-TO-18 FUNNELING
BITS 17-0 BITS 35-18 BITS 17-0 BITS 35-18 BITS 17-0
D17B-D0B
WORD
WORD
BITS 17-0 BITS 35-18 BITS 17-0
WORD
BITS 35-18
D35B-D18B
BITS 35-18
WORD
WORD
WORD
Notes: held HIGH FIFO access. held LOW. held HIGH held double-byte access.
FIGURE DOUBLE-BYTE FIFO WRITE ACCESS 18-TO-36 DEFUNNELING
D17B-D0B
BITS 17-0 BITS 35-18 BITS 17-0 BITS 35-18 BITS 17-0 BITS 35-18
WORD
WORD
WORD
Notes: held HIGH FIFO access. held HIGH. held HIGH held double-byte access.
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY FIGURE PORT SINGLE-BYTE FIFO READ ACCESS 9-TO-36 DEFUNNELING
D8B-D0B
BITS
BITS 17-9
BITS 26-18
BITS 35-27
BITS
WORD
WORD
BITS 26-18 BITS 35-27 BITS BITS 17-9
D17B-D9B
BITS 17-9
WORD
WORD
BITS 35-27 BITS BITS 17-9 BITS 26-18
D26B-D18B
BITS 26-18
WORD
WORD
BITS BITS 17-9 BITS 26-18 BITS 35-27
D35B-D27B
BITS 35-27
Notes: held HIGH FIFO access. held LOW. both held single-byte access.
WORD
WORD
FIGURE PORT SINGLE-BYTE FIFO WRITE ACCESS 9-TO-36 DEFUNNELING
D8B-D0B
BITS BITS 17-9 BITS 26-18 BITS 35-27 BITS BITS 35-18
WORD
WORD
Notes: held HIGH FIFO access. held HIGH. both held single-byte access.
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY FIGURE WRITE REQUEST/ACKNOWLEDGE HANDSHAKE
Outside "almost-full" region, acknowledge continuous continuous request. Starting third cycle after entering "almost-full" region, acknowledge occurs every third cycle prevent underrun "empty" condition.
(CKB) R/WA (R/WB) tRQS REQA (REQB) tACK ACKA (ACKB)
tACK tACK tACK
(AF2)
Notes: FIFO access occur, must held HIGH required setup hold times. tied directly directly gate FIFO accesses. indicates where write would take place, were tied must maintained HIGH throughout entire clock cycle generated. When REQ/ACK handshake used, ignored, tied HIGH used second enable. Parameters without parentheses apply port Parameters with parentheses apply port
FIGURE READ REQUEST/ACKNOWLEDGE HANDSHAKE
Outside "almost-empty" region, acknowledge continuous continuous request. Starting third cycle after entering "almost-empty" region, acknowledge occurs every third cycle prevent underrun "empty" condition.
(CKB) R/WA (R/WB) tRQS REQA (REQB) tACK ACKA (ACKB)
tACK
tACK
tACK
(AE1)
Notes: FIFO access occur, must held HIGH required setup hold times. tied directly directly gate FIFO accesses. indicates where read would take place, were tied must maintained HIGH throughout entire clock cycle generated. When REQ/ACK handshake used, ignored, tied HIGH used second enable. Parameters without parentheses apply port Parameters with parentheses apply port
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.
QS725420A PRELIMINARY ORDERING INFORMATION Example:
QS72 5420A Specialty Memory Product Prefix (QS72) Part Number 5420A Package (132-Pin PQFP) (144-Pin TQFP) Speed
QUALITY SEMICONDUCTOR, INC.
MDSF-00018-01
APRIL 1995
QS725420A PRELIMINARY
MDSF-00018-01
APRIL 1995
QUALITY SEMICONDUCTOR, INC.

High-Speed CMOS High Speed CMOS Exchange Switches Bi-directional FIFO

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