Atmel PLDs' Architectures Simplify Timing Calculation This applic

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Atmel PLDs' Architectures Simplify Timing Calculation This applic

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Atmel PLDs' Architectures Simplify Timing Calculation
This application note shows different graphical timing models that help user visualize A.C. timing various Atmel families devices. Because their deterministic path-independent delays, timing calculation becomes straight forward. Atmel PLDs have regular AND-OR architecture which simplifies timing calculation. A.C. timing parameters clearly stated data book. Even complex designs only takes minutes calculate delays hand. design engineer access tools such Atmel-ViewPLD, he/she easily predict performance PLD. software packages with timing simulation capabilities design engineer know performance immediately after design entered check results timing simulator quickly modify design meet system timing requirements. Atmel offers complete design entry package called Atmel-ViewPLD that such timing simulator.
Architectures/Timing Models
AT22V10 represents classic PAL-type architecture with programmable fixed structure. very small A.C. timing parameters describe delays that occur implementation register combinatorial logic shown Figure example, output described following Boolean equation: OUTPUT SELECT; SELECT inputs I/Os delay will simply time signal propagate from through AND-OR array, macrocell, output pin. This described A.C. parameter tPD. ATV750/ATV750B ATV2500/ ATV2500B, with more advanced macrocells, maintain same AND-OR structure AT22V10. Because this, they also described same AT22V10 timing model. Even when using buried registers found ATV750/ATV750B ATV2500/ ATV2500B, method calculation delays stays same.
Programmable Logic Device Application Note
Figure AT22V10, ATV750, ATV750B, ATV2500 ATV2500B Timing Model
INPUT FEEDBACK
INPUT
0239B
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ample, Abeldescription binary counter look like: COUNT.d COUNT.fb counter implemented using only internal buried registers ATV750, ATV750B, ATV2500 ATV2500B. this case minimum cycle time will equal (clock feedback) (feedback setup). Figure This also equal 1/(FMAX internal). Figure shows registered data path pin-to-pin delay, might described output logic: REG_A.d !C1; signals from either input pins, then minimum cycle time will (setup time input pin) (clock output) which equal 1/(FMAX external). Figure shows data propagates typical Mealy statemachine, which state bits inputs combinatorial outputs: COUNT.d (COUNT.FB +1); FULL (COUNT.FB ^HFF); Figure 1/(FMAX internal)
INPUT
this case, will take FULL delay from rising edge clock driving counter changing FULL's output value. Figure based upon Figure with addition A.C. parameters help describe features ATV5000 ATV5100. These devices have both synchronous asynchronous modes operation. With addition synchronous clocking option, devices perform higher clock rate. A.C. parameters have either suffix (synchronous) (asynchronous) distinguish registered clocking options. Input latch setup hold time additional requirements when latch used. latch bypassed, delay added. these devices, parameter broken down further show different delay paths separately. TPD1 tPD2 similar traditional parameter. TPD1 delay from combinatorial output. TPD2 delay from internal feedback nodes combinatorial output pin. TPD3 delay from internal combinatorial feedback.
Figure 1/(FMAX external)
INPUT
6-138
CMOS
CMOS
TPD4 delay from internal feedback, through AND/OR array, internal combinatorial feedback. ATV5000 ATV5100 Buried Logic Cells user configure internal combinatorial registered feedbacks. Having combinatorial feedback enables designer expand logic without sacrificing pins. Also, term feedbacks ATV5000 ATV5100 take regional array inputs make them available other quadrants. most straightforward determine delays look documentation generated software after design been reduced fitted. reduced equation looks like: OUTA WATCHDOG "Product term "Product term C_OUT;"Product term Determine whether logic registered combinatorial. Determine whether OUTA internal node output pin.
Figure Mealy Machine Delay Path
INPUT
Figure ATV5000 ATV5100 Timing Model
tPD1
tPD2
INPUT LATCH INPUT
tPD3
tPD4 tCFS tCFA tSFS tSFA tSIS tSIA tEA2 tER2 tEA1 tER1
tCOS tCOA
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Find source each components that makes product terms. analyze various cases, let's assume following: OUTA combinatorial. will look OUTA implemented output versus OUTA implemented combinatorial node. WATCHDOG internal registered node, through directly from inputs, C_OUT internal combinatorial node (this covers signal sources). Table summarizes various timing requirements. Case (Figure typical Mealy state machine where internal state registers decoded form combinatorial output. total delay from clock output tPD2. Case pin-to-pin delay. A.C. parameter that tPD1. Case internal combinatorial feedback's delay from AND/OR array output pin: tPD2. Case "buried Mealy" where internal state registers decoded placed output pin. Instead result Table Registered Feedback P.T. Combinatorial Output OUTA Combinatorial Node OUTA Case tPD2 Case tPD4
implemented internal combinatorial node where logic only useful internal design. Case delay from internal combinatorial feedback: tPD3. Case delay from internal combinatorial node another internal combinatorial node.
Conclusion
graphical representation A.C. timing models illustrate simple determine performance logic implemented Atmel PLD. Atmel complex PLDs, even with their high counts advanced features, have simple timing calculation. They aren't harder than common AT22V10.
Input from Pins P.T. Case tPD1 Case tPD3
Internal Combinatorial Node P.T. Case tPD2 Case tPD4
Figure Typical Mealy State Machine
tPD1
tPD2
INPUT LATCH INPUT
tPD3
tPD4 tCFS tCFA tSFS tSFA tSIS tSIA tEA2 tER2 tEA1 tER1
tCOS tCOA
PALand Abelmay registered trademarks others. 6-140
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