Intel SmartVoltage Technology Program Erase Read Operation Increased P

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4-MBIT (256K 512K SmartVoltage BOOT BLOCK FLASH MEMORY FAMIL28F400BV-T 28F400CV-T 28F004BV-T 28F400CE-T 28F004BE-T
Intel SmartVoltage Technology Program Erase Read Operation Increased Programming Throughput Very High-Performance Read Access Time Output Enable Time Access Output Enable Time Access Output Enable Time Power Consumption Read Current Read Current x16-Selectable Input Output 28F400 High Performance 32-bit CPUs x8-Only Input Output Architecture 28F004B Space-Constrained 8-bit Applications Optimized Array Blocking Architecture 16-KB Protected Boot Block 8-KB Parameter Blocks 96-KB Main Block Three 128-KB Main Blocks Bottom Boot Locations Absolute Hardware-Protection Boot Block Software EEPROM Emulation with Parameter Blocks Extended Temperature Operation
Extended Cycling Capability Block Erase Cycles (Commercial Temperature) Block Erase Cycles (Extended Temperature) Automated Word Byte Write Block Erase Industry-Standard Command User Interface Status Registers Erase Suspend Capability SRAM-Compatible Write Interface Automatic Power Savings Feature Typical Active Current Static Operation Reset Deep Power-Down Input ICCTypical Provides Reset Boot Operations Hardware Data Protection Feature Erase Write Lockout during Power Transitions Industry-Standard Surface Mount Packaging 40-Lead TSOP 44-Lead PSOP JEDEC Compatible 48-Lead TSOP 56-Lead TSOP Footprint Upgradeable from 2-Mbit 8-Mbit Boot Block Flash Memories ETOX Flash Technology
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Other brands names property their respective owners Information this document provided connection with Intel products Intel assumes liability whatsoever including infringement patent copyright sale Intel products except provided Intel's Terms Conditions Sale such products Intel retains right make changes these specifications time without notice Microcomputer Products have minor variations this specification known errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290530-003
4-MBIT (256K 512K SmartVoltage BOOT BLOCK FLASH MEMORY FAMILCONTENTS
PAGE
CONTENTS
Power Consumption Active Power Automatic Power Savings Standby Power Deep Power-Down Mode Power-Up Down Operation Connected System Reset Transitions Power Supply Decoupling Trace Printed Circuit Boards ABSOLUTE MAXIMUM RATINGS COMMERCIAL OPERATING CONDITIONS Applying Voltages Characteristics Characteristics EXTENDED OPERATING CONDITIONS Applying Voltages Characteristics Characteristics ADDITIONAL INFORMATION Ordering Information References Revision History
PAGE
PRODUCT FAMILY OVERVIEW Features SmartVoltage Products Main Features Applications Pinouts Descriptions PRODUCT DESCRIPTION Memory Blocking Organization Boot Block Parameter Blocks Main Blocks PRODUCT FAMILY PRINCIPLES OPERATION Operations Read Operations Read Array Intelligent Identifiers Write Operations Command User Interface Status Register Program Mode Erase Mode Boot Block Locking Complete Protection Boot Block Locking Boot Block Unlocking
4-MBIT SmartVoltage BOOT BLOCK FAMIL
PRODUCT FAMILY OVERVIEW
This datasheet contains specifications branches products SmartVoltage 4-Mbit boot block flash memory family suffix products feature operating range 7V-3 suffix products offer operation Both products also operate high-speed access times Throughout this datasheet 28F400 refers 4-Mbit products while 28F004B refers 4-Mbit boot block products Also term 7V'' generally refers full voltage range 7V-3 Section provides overview flash memory family including applications pinouts descriptions Sections describe memory organization operation these products Finally Sections contain family's operating specifications
program erase operation been added
switching write protection switch (not complete write protection take advantage write-capability allow connecting disconnecting from line
Enhanced circuits optimize performance
allowing operation down (using product) using boot block products today should account differences listed above also allow connecting disconnecting from line writes desired
Main Features
Intel's SmartVoltage technology most flexible voltage solution flash industry providing discrete voltage supply pins read operation program erase operation Discrete supply pins allow system designers optimal voltage levels their design 28F400BV 28F004BV 28F400CE 28F004BE provide program erase capability 28F400BV 28F004BV allows reads with while 28F400CE 28F004BE allows reads with Since many designs read from flash memory large percentage time read operation using ranges provide great power savings read performance issue however provides faster read access times
Features SmartVoltage Products
SmartVoltage boot block flash memory family offers identical operation with program products except differences listed below other functions equivalent current products including signatures write commands pinouts
replaced (Don't Use) Connect control signal this case logic-level signal placed pin) Tables works
Table SmartVoltage Provides Total Voltage Flexibility Product Name 28F004BV-T 28F400BV-T 28F400CV-T 28F004BE-T 28F400CE-T Width 7V-3 10%V
4-MBIT SmartVoltage BOOT BLOCK FAMILFor program erase operations operation eliminates need system voltage converters while operation provides faster program erase situations where available such manufacturing designs where in-system design simplicity however just hook same source 28F400 28F004B boot block flash memory family high-performance 4-Mbit bit) flash memory family organized either Kwords bits each (28F400 only) Kbytes bits each (28F400 28F004B) Separately erasable blocks including hardwarelockable boot block bytes) parameter blocks bytes each) main blocks (one block bytes three blocks bytes) define boot block flash family architecture Figures memory maps Each block independently erased programmed times commercial temperature times extended temperature boot block located either (denoted suffix) bottom suffix) address order accommodate different microprocessor protocols boot code location hardware-lockable boot block provides complete code security kernel code required system initialization Locking unlocking boot block controlled (see Section details) Command User Interface (CUI) serves interface between microprocessor microcontroller internal operation boot block flash memory products internal Write State Machine (WSM) automatically executes algorithms timings necessary program erase operations including verifications thereby unburdening microprocessor microcontroller these tasks Status Register (SR) indicates status whether successfully completed desired program erase operation Program Erase Automation allows program erase operations executed using industrystandard two-write command sequence Data writes performed word (28F400 family) byte (28F400 28F004B families) increments Each byte word flash memory programmed independently other memory locations unlike erases which erase locations within block simultaneously 4-Mbit SmartVoltage boot block flash memory family also designed with Automatic Power Savings (APS) feature which minimizes system battery current drain allowing very power designs provide even greater power savings boot block family includes deep power-down mode which minimizes power consumption turning most flash memory's circuitry This mode controlled usage discussed Section along with other power consumption issues Additionally provides protection against unwanted command writes invalid system conditions that occur during system reset power-up down sequences example when flash memory powers-up automatically defaults read array mode during warm system reset where power continues uninterrupted system components flash memory could remain non-read mode such erase Consequently system Reset signal should tied reset memory normal read mode upon activation Reset signal Section 28F400 provides both byte-wide word-wide input output which controlled BYTE Please Table Figure detailed description BYTE operations especially usage DQ15 28F400 products available EPROM-compatible pinout housed 44-lead PSOP (Plastic Small Outline) package 48-lead TSOP (Thin Small Outline thick) package 56-lead TSOP shown Figures respectively 28F004 products available 40-lead TSOP package shown Figure Refer Characteristics Table Section (commercial temperature) Section (extended temperature) complete current voltage specifications Refer Characteristics Table Section (commercial temperature) Section (extended temperature) read write erase performance specifications
4-MBIT SmartVoltage BOOT BLOCK FAMILThe 4-Mbit flash memory products also excellent design solutions digital cellular phone telecommunication switching applications requiring very power consumption high-performance highdensity storage capability modular software designs small form factor package 4-Mbit's blocking scheme allows easy segmentation embedded code with Kbytes hardware-protected boot code four main blocks program code parameter blocks Kbytes each frequently updated data storage diagnostic messages phone numbers authorization codes) Intel's boot block architecture provides flexible voltage solution different design needs various applications asymmetrically-blocked memory allows integration several memory components into single flash device boot block provides secure boot PROM parameter blocks emulate EEPROM functionality parameter store with proper software techniques main blocks provide code data storage with access times fast enough execute code place decreasing requirements
Applications
4-Mbit boot block flash memory family combines high-density low-power high-performance cost-effective flash memories with blocking hardware protection capabilities Their flexibility versatility reduce costs throughout product life cycle Flash memory ideal Just-In-Time production flow reducing system inventory costs eliminating component handling during production phase When your product end-user's hands updates feature enhancements become necessary flash memory reduces update costs allowing user-performed code changes instead costly product returns technician calls 4-Mbit boot block flash memory family provides full-function blocked flash memories suitable wide range applications These applications include extended BIOS ROM-able applications storage digital cellular phone program data storage telecommunication boot firmware printer firmware font storage various other embedded applications where program data storage required Reprogrammable systems such personal computers ideal applications 4-Mbit flash memory products Increasing software sophistication greatens probability that code update will required after shipped example emerging ``plug play'' standard desktop portable enables auto-configuration add-in cards However since ``plug play'' specification continues evolve flash BIOS provides cost-effective capability update existing addition parameter blocks ideal storing required auto-configuration parameters allowing integrate BIOS PROM parameter storage EEPROM into single component reducing parts costs while increasing functionality
Pinouts
Intel's SmartVoltage Boot Block architecture provides upgrade paths every package pinout 8-Mbit density 28F004B 40-lead TSOP pinout space-constrained designs shown Figure 28F400 44-lead PSOP pinout follows industry-standard EPROM pinout shown Figure designs that require operation have space concerns refer 48-lead pinout Figure Furthermore 28F400 56-lead TSOP pinout shown Figure provides density upgrades future higher density boot block memories Pinouts corresponding 2-Mbit 8-Mbit components also provided convenient reference 4-Mbit pinouts given chip illustration center with 2-Mbit 8-Mbit pinouts going outward from center
4-MBIT SmartVoltage BOOT BLOCK FAMIL
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Figure 28F400 Interface Intel386 Microprocessor
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Figure 28F004B Interface Intel80C188EB 8-Bit Embedded Microprocessor
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Figure 40-Lead TSOP Offers Smallest Form Factor Space-Constrained Applications
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NOTE Versions 8-Mbit device been changed Mbit) Designers planning upgrading 8-Mbit density from 4-Mbit density this package should design control functionality 4-Mbit level allow control after upgrading 8-Mbit density
Figure 44-Lead PSOP Offers Convenient Upgrade from JEDEC Standards
4-MBIT SmartVoltage BOOT BLOCK FAMIL
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Figure 48-Lead TSOP Offers Smallest Form Factor Operation
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Figure 56-Lead TSOP Offers Compatibility between Mbits
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Descriptions
Table 28F400 Descriptions Symbol -A18 Type INPUT Name Function ADDRESS INPUTS memory addresses Addresses internally latched during write cycle 28F400 only -A17 pins while 28F004B -A18 ADDRESS INPUT When signature mode accessed During this mode decodes between manufacturer device When BYTE logic only lower byte signatures read DQ15 don't care signature mode when BYTE DATA INPUTS OUTPUTS Inputs array data second cycle during Program command Inputs commands Command User Interface when active Data internally latched during write cycle Outputs array Intelligent Identifier Status Register data data pins float tri-state when chip de-selected outputs disabled DATA INPUTS OUTPUTS Inputs array data second cycle during Program command Data internally latched during write cycle Outputs array data data pins float tri-state when chip de-selected outputs disabled byte-wide mode (BYTE ``0'') bytewide mode DQ15 becomes lowest order address data output -DQ7 28F004B does include these -DQ15 pins CHIP ENABLE Activates device's control logic input buffers decoders sense amplifiers active high de-selects memory device reduces power consumption standby levels high CMOS high level standby current will increase current flow through input stages OUTPUT ENABLE Enables device's outputs through data buffers during read cycle active WRITE ENABLE Controls writes Command Register array blocks active Addresses data latched rising edge pulse RESET DEEP POWER-DOWN Uses three voltage levels (VIL VHH) control different functions reset deep power-down mode boot block unlocking backwards-compatible with products When logic device reset deep power-down mode which puts outputs High-Z resets Write State Machine draws minimum current When logic high device standard operation When transitions from logic-low logic-high device defaults read array mode When boot block unlocked programmed erased This overrides control from input
INPUT
-DQ7
INPUT OUTPUT
-DQ15
INPUT OUTPUT
INPUT
INPUT INPUT
INPUT
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table 28F400 Descriptions (Continued) Symbol Type INPUT Name Function WRITE PROTECT Provides method unlocking boot block system without supply When logic boot block locked preventing program erase operations boot block program erase operation attempted boot block when corresponding status (bit program erase) will Status Register indicate operation failed When erased logic high boot block unlocked programmed
NOTE This feature overridden boot block unlocked when This available 44-lead PSOP package Section details write protection BYTE INPUT BYTE ENABLE available 28F004B Controls whether device operates byte-wide mode (x8) word-wide mode (x16) BYTE must controlled CMOS levels meet CMOS current specification standby mode When BYTE logic byte-wide mode enabled where data read programmed -DQ7 DQ15 becomes lowest order address that decodes between upper lower byte -DQ14 tri-stated during bytewide mode When BYTE logic high word-wide mode enabled where data read programmed -DQ15 DEVICE POWER SUPPLY only) PROGRAM ERASE POWER SUPPLY erasing memory array blocks programming data each block voltage either must applied this When VPPLK blocks locked protected against Program Erase commands GROUND internal circuitry CONNECT driven left floating
4-MBIT SmartVoltage BOOT BLOCK FAMIL
PRODUCT DESCRIPTION Memory Blocking Organization
This product family features asymmetricallyblocked architecture providing system memory integration Each erase block erased independently others times commercial temperature times extended temperature block sizes have been chosen optimize their functionality common applications nonvolatile storage combination block sizes boot block architecture allow integration several memories into single chip address locations blocks memory maps Figures BOOT BLOCK boot block intended replace dedicated boot PROM microprocessor microcontrollerbased system 16-Kbyte bytes) boot block located either (denoted suffix) bottom suffix) address accommodate different microprocessor protocols boot code location This boot block features hardware controllable write-protection protect crucial microprocessor boot code from accidental modification protection boot block controlled using combination pins detailed Section
PARAMETER BLOCKS boot block architecture includes parameter blocks facilitate storage frequently updated small parameters that would normally require EEPROM using software techniques byterewrite functionality EEPROMs emulated These techniques detailed Intel's AP-604 ``Using Intel's Boot Block Flash Memory Parameter Blocks Replace EEPROM Each boot block component contains parameter blocks Kbytes bytes) each parameter blocks write-protectable MAIN BLOCKS After allocation address space boot parameter blocks remainder divided into main blocks data code storage Each 4-Mbit device contains 96-Kbyte byte) block three 128-Kbyte (131 byte) blocks memory maps each device more information
4-MBIT SmartVoltage BOOT BLOCK FAMIL
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NOTE Address operation least significant system address should connected Memory maps shown operation
Figure Word-Wide x16-Mode Memory Maps
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NOTE Address These memory maps apply 28F400 28F800 mode
Figure Byte-Wide x8-Mode Memory Maps
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PRODUCT FAMILY PRINCIPLES OPERATION
Flash memory combines EPROM functionality with in-circuit electrical write erase boot block flash family utilizes Command User Interface (CUI) automated algorithms simplify write erase operations allows 100% TTL-level control inputs fixed power supplies during erasure programming maximum EPROM compatibility When VPPLK device will only successfully execute following commands Read Array Read Status Register Clear Status Register intelligent identifier mode device provides standard EPROM read standby output disable operations Manufacturer identification device identification data accessed through through standard EPROM high voltage access (VID) PROM programming equipment same EPROM read standby output disable functions available when applied addition allows write erase device functions associated with altering memory contents Program Erase Intelligent Identifier Read Read Status accessed internal Write State Machine (WSM) completely automates program erase beginning operation signaled reporting status through Status Register handles interface data address latches well system status requests during operation
Operations
Flash memory reads erases writes in-system local cycles from flash memory conform standard microprocessor cycles These operations summarized Tables
Read Operations
READ ARRAY When transitions from (reset) device will read array mode will respond read control inputs address inputs without commands being written When device read array mode five control signals must controlled obtain data outputs
must logic high (VIH)
must logic (VIL) must logic (VIL) must logic high (VIH) BYTE must logic high logic
addition address desired location must applied address pins Refer Figures exact sequence timing these signals device read array mode would case after program erase operation Read Mode command (FFH) must written before reads take place During system design consideration should taken ensure address control inputs meet required input slew rates defined Figures
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Operations Word-Wide Mode (BYTE Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes
VIH)
VIL)
DQ0-15 DOUT High High High 0089 Table
Table Operations Byte-Wide Mode (BYTE Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write Notes
DQ0-7 DOUT High High High Table
DQ8-14 High High High High High High
High
NOTES Refer Characteristics control pins addresses VPPLK VPPH Characteristics VPPLK VPPH1 VPPH2 voltages Manufacturer device codes also accessed write sequence -A17 -A18 Table device Refer Table valid during write operation Command writes block erase word byte write only executed when VPPH1 VPPH2 write erase boot block hold Section must meet maximum deep power-down current specified
4-MBIT SmartVoltage BOOT BLOCK FAMIL
INTELLIGENT IDENTIFIERS read manufacturer device codes device must intelligent identifier read mode which reached using methods writing intelligent identifier command (90H) taking Once intelligent identifier read mode outputs manufacturer's identification code outputs device code byte-wide mode only lower byte above signatures read (DQ15 ``don't care'' this mode) Table product signatures return read array mode write Read Array command (FFH) Table Intelligent Identifier Table Device Product 28F400 28F004 0089 (Top Boot) 4470 (Bottom Boot) 4471
Write Operations
COMMAND USER INTERFACE (CUI) Command User Interface (CUI) interface between microprocessor internal chip controller Commands written using standard microprocessor write timings available commands Read Array Read Intelligent Identifier Read Status Register Clear Status Register Erase Program (summarized Tables three read modes read array intelligent identifier read status register read Program Erase commands informs Write State Machine (WSM) that write erase been requested During execution Program command will control programming sequences will only respond status reads During erase cycle will respond status reads erase suspend After completed task will Status ``1'' (ready) which indicates that respond full command Note that after returned control will stay current command state until receives another command Command Function Description Device operations selected writing specific commands into Tables define available commands
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Command Codes Descriptions Code Device Mode Invalid Reserved Read Array Program Erase Abort Decription Unassigned commands that should used Intel reserves right redefine these codes future functions Places device read array mode that array data will output data pins This command also used cancel erase program sequences after their set-up commands have been issued cancel after issuing Erase Set-Up command issue this command which will reset read array mode cancel program operation after issuing Program Set-Up command issue Read Array commands sequence reset read array mode program erase operation already been initated this command cancel that operation progress Sets into state such that next write will load Address Data registers After this command executed outputs default Status Register Read Array command sequence (FFH) required reset Read Array after Program Set-Up command second write after Program Set-Up command will latch addresses data initiating program algorithm device outputs Status Register data when enabled read array data issue Read Array command Alternate Prog Set-Up Erase Set-Up (See Program Set-Up) Prepares Erase Confirm command next command Erase Confirm command then will both Program Status Erase Status bits Status Register place device into read Status Register state wait another command previous command Erase Set-Up command then will latch address data begin erasing block indicated address pins During erase device will respond only Read Status Register Erase Suspend commands will output Status Register data when toggled Status Register data updated toggling either Valid only while erase operation progress will ignored other circumstance Issuing this command will begin suspend erase operation Status Register will indicate when device reaches erase suspend mode this mode will respond only Read Array Read Status Register Erase Resume commands will also Status ``1'' (ready) will continue idle SUSPEND state regardless state input control pins except which will immediately shut down remainder chip made active During suspend operation data address latches will remain closed address pads able drive address into read path Section Puts device into read Status Register mode that reading device outputs Status Register data regardless address presented device device automatically enters this mode after program erase completed This commands that executable while operating Section
Program Set-Up
Erase Resume Erase Confirm Erase Suspend
Read Status Register
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Command Codes Descriptions (Continued) Code Device Mode Clear Status Register Decription only Program Status Erase Status bits Status Register ``1'' cannot clear them Status Register operates this fashion reasons first give host flexibility read status bits time Second when programming string bytes single Status Register query after programming string more efficient since will return accumulated error status entire string Section Intelligent Identifier Puts device into intelligent identifier read mode that reading device will output manufacturer device codes manufacturer device other address inputs ignored) Section Table Command Definitions Command Read Array Intelligent Identifier Read Status Register Clear Status Register Word Byte Write Alternate Word Byte Write Block Erase Confirm Erase Suspend Resume
ADDRESS Block Address Identifier Address Write Address Don't Care
Note
First Cycle Oper Write Write Write Write Write Addr Data
Second Cycle Oper Addr Data
Read Read
Write Write Write Write
Write Write Write
DATA Status Register Data Identifier Data Write Data
NOTES operations defined Tables Identifier Address manufacturer code device code Data read from Status Register Intelligent Identifier Data Following Intelligent Identifier command read operations access manufacturer device codes Address within block being erased Address written Data written location Either commands valid When writing commands device upper data -DQ15 (28F400 only) which either minimize current draw
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Status Register Definition WSMS VPPS
WRITE STATE MACHINE STATUS Ready (WSMS) Busy ERASE-SUSPEND STATUS (ESS) Erase Suspended Erase Progress Completed ERASE STATUS (ES) Error Block Erasure Successful Block Erase PROGRAM STATUS (DWS) Error Byte Word Program Successful Byte Word Program STATUS (VPPS) Detect Operation Abort
NOTES Check Write State Machine first determine Word Byte program Block Erase completion before checking Program Erase Status bits When Erase Suspend issued halts execution sets both WSMS bits remains ``1'' until Erase Resume command issued When this applied number erase pulses block still unable verify successful block erasure When this attempted failed program byte word Status does provide continuous indication level interrogates level only after Byte Write Erase command sequences have been entered informs system been switched Status guaranteed report accurate feedback between VPPLK VPPH These bits reserved future should masked when polling Status Register Important contents Status Register latched falling edge whichever occurs last read cycle This prevents possible errors which might occur Status Register contents change while being read must toggled with each subsequent status read Status Register will indicate completion program erase operation When active register will indicate status will also hold bits indicating whether successful performing desired operation
2-SR RESERVED FUTURE ENHANCEMENTS STATUS REGISTER device Status Register indicates when program erase operation complete success failure that operation read Status Register write Read Status (70H) command This causes subsequent read operations output data from Status Register until another command written return reading from array issue Read Array (FFH) command Status Register bits output -DQ7 both byte-wide (x8) word-wide (x16) mode word-wide mode upper byte -DQ15 outputs during Read Status command byte-wide mode -DQ14 tri-stated DQ15 retains order address function
4-MBIT SmartVoltage BOOT BLOCK FAMILThe Status Register should cleared before attempting next operation instruction follow after programming completed however reads from Memory Array Intelligent Identifier cannot accomplished until given appropriate command ERASE MODE erase block write Erase Set-Up Erase Confirm commands along with addresses identifying block erased These addresses latched internally when Erase Confirm command issued Block erasure results bits within block being Only block erased time will execute sequence internally timed events Program bits within block Verify that bits within block sufficiently programmed Erase bits within block Verify that bits within block sufficiently erased While erase sequence executing Status Register When Status Register indicates that erasure complete check Erase Status verify that erase operation successful Erase operation unsuccessful Status Register will indicating Erase Failure within acceptable limits after Erase Confirm command issued will execute erase sequence instead Status Register ``1'' indicate Erase Failure ``1'' identify that supply voltage within acceptable limits Clear Status Register before attempting next operation instruction follow after erasure completed however reads from Memory Array Status Register Intelligent Identifier cannot accomplished until given Read Array command
Clearing Status Register sets status bits through clears bits cannot clear status bits through Bits through only cleared controlling through Clear Status Register (50H) command because these bits indicate various error conditions allowing system software control resetting these bits several operations performed (such cumulatively programming several bytes erasing multiple blocks sequence) before reading Status Register determine error occurred during that series Clear Status Register before beginning another command sequence Note again that Read Array command must issued before data read from memory intelligent identifier PROGRAM MODE Programming executed using two-write sequence Program Setup command written followed second write which specifies address data programmed will execute sequence internally timed events Program desired bits addressed memory word byte Verify that desired bits sufficiently programmed Programming memory results specific bits within byte word being changed user attempts program ``1''s there will change memory cell content error occurs Status Register indicates programming status while program sequence executing Status Register Status Register polled toggling either While programming only valid command Read Status Register When programming complete Program Status bits should checked programming operation unsuccessful Status Register ``1'' indicate Program Failure then within acceptable limits execute programming sequence
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Suspending Resuming Erase Since erase operation requires order seconds complete Erase Suspend command provided allow erase-sequence interruption order read data from another block memory Once erase sequence started writing Erase Suspend command requests that pause erase sequence predetermined point erase algorithm Status Register will indicate when erase operation been suspended this point Read Array command written order read data from blocks other than that which being suspended only other valid command this time Erase Resume command Read Status Register command During erase suspend mode chip into pseudo-standby mode taking which reduces active current draw resume erase operation enable chip taking then issuing Erase Resume command which continues erase sequence completion with standard erase operation Status Register must read cleared next instruction issued order continue
BOOT BLOCK LOCKING
When boot block locked program erase operation boot block will result error Status Register other blocks remain unlocked this condition programmed erased normally Note that this feature overridden boot block unlocked when BLOCK UNLOCKING
BOOT
methods used unlock boot block
both either these conditions boot block will unlocked programmed erased truth table Table clearly defines write protection methods Table Write Protection Truth Table SmartVoltage Boot Block Family
VPPLK VPPLK VPPLK VPPLK
Write Protection Provided Blocks Locked Blocks Locked (Reset) Blocks Unlocked Boot Block Locked Blocks Unlocked
Boot Block Locking
boot block family architecture features hardware-lockable boot block that kernel code system kept secure while parameter main blocks programmed erased independently necessary Only boot block locked independently from other blocks COMPLETE PROTECTION complete write protection blocks flash device programming voltage held When below VPPLK program erase operation will result error Status Register
4-MBIT SmartVoltage BOOT BLOCK FAMIL
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Figure Automated Word Byte Programming Flowchart
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Figure Automated Block Erase Flowchart
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Figure Erase Suspend Resume Flowchart
4-MBIT SmartVoltage BOOT BLOCK FAMILDuring erase program modes will abort either erase program operations memory contents longer valid data been corrupted function read mode above internal circuitry turned achieve power savings transitions turning power device will clear Status Register
Power Consumption
ACTIVE POWER With logic-low level logichigh level device placed active mode Refer Characteristics table current values AUTOMATIC POWER SAVINGS (APS) Automatic Power Savings (APS) provides low-power operation during active mode Power Reduction Control (PRC) circuitry allows device itself into current state when being accessed After data read from memory array logic controls device's power consumption entering mode where typical current less than device stays this static state with outputs valid until location read STANDBY POWER With logic-high level (VIH) read mode memory placed standby mode which disables much device's circuitry substantially reduces power consumption Outputs (DQ0 -DQ15 -DQ7) placed high-impedance state independent status signal When logic-high level during erase program operations device will continue perform operation consume corresponding active power until operation completed DEEP POWER-DOWN MODE SmartVoltage boot block family supports typical deep power-down mode which turns circuits save power This mode activated when logic-low (GND Note BYTE must CMOS levels meet ICCD specification During read modes going de-selects memory places output drivers high impedance state Recovery from deep power-down state requires minimum access time tPHQV (see Characteristics table)
Power-Up Down Operation
device protected against accidental block erasure programming during power transitions Power supply sequencing required since device indifferent which power supply powers-up first reset read mode after power-up system must drop present address ensure valid data outputs system designer must guard against spurious writes when voltages above VLKO active Since both must command write driving either signal will inhibit writes device architecture provides additional protection since alteration memory contents only occur after successful completion two-step command sequences device also disabled until brought regardless state control inputs holding device reset connected system PowerGood) during power-up down invalid conditions during power-up masked providing another level memory protection CONNECTED SYSTEM RESET
during system reset important with automated write erase devices because system expects read from flash memory when comes reset reset occurs without flash memory reset proper initialization would occur because flash memory providing status information instead array data Intel's Flash memories allow proper initialization following system reset connecting same RESET signal that resets system
4-MBIT SmartVoltage BOOT BLOCK FAMILTransient current magnitudes depend device outputs' capacitive inductive loading Two-line control proper decoupling capacitor selection will suppress these transient voltage peaks Each flash device should have ceramic capacitor connected between each between These high- frequency inherently low-inductance capacitors should placed close possible package leads TRACE PRINTED CIRCUIT BOARDS Designing in-system writes flash memory requires special consideration power supply trace printed circuit board designer supplies flash memory cells current programming erasing should similar trace widths layout considerations given power supply trace Adequate supply traces decoupling capacitors placed adjacent component will decrease spikes overshoots
TRANSITIONS
latches commands issued system software altered transitions actions default state upon powerup after exit from deep power-down mode after transitions above VLKO (Lockout voltage) read array mode After word byte write block erase operation complete even after transitions down VPPLK must reset read array mode Read Array command accesses flash memory desired Please refer AP-617 ``Additional Flash Data Protection Using circuit-level discription implement protection discussed Section
Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods System designers should consider three supply current issues Standby current levels (ICCS) Active current levels (ICCR) Transient peaks produced falling rising edges
NOTE Table headings Sections BV-60 BV-80 BV-120 TBV-80 TBE-120) refer specific products listed below Section more information product naming line items Abbreviation BV-60 BV-80 BV-120 TBV-80 TBE-120 Applicable Product Names E28F004BV-T60 E28F004BV-B60 PA28F400BV-T60 PA28F400BV-B60 E28F400CV-T60 E28F400CV-B60 E28F400BV-T60 E28F400BV-B60 E28F004BV-T80 E28F004BV-B80 PA28F400BV-T80 PA28F400BV-B80 E28F400CV-T80 E28F400CV-B80 E28F400BV-T80 E28F400BV-B80 E28F004BV-T120 E28F004BV-B120 PA28F400BV-T120 PA28F400BV-B120 TE28F004BV-T80 TE28F004BV-B80 TB28F400BV-T80 TB28F400BV-B80 TE28F400CV-T80 TE28F400CV-B80 TE28F400BV-T80 TE28F400BV-B80 TE28F004BE-T120 TE28F004BE-B120 TE28F400CE-T120 TE28F400CE-B120
4-MBIT SmartVoltage BOOT BLOCK FAMIL
ABSOLUTE MAXIMUM RATINGS
Commercial Operating Temperature During Read During Block Erase Word Byte Write Temperature Bias
NOTICE This data sheet contains preliminary information products production specifications subject change without notice Verify with your local Intel Sales office that have latest data sheet before finalizing design
Extended Operating Temperature During Read During Block Erase Word Byte Write Temperature Under Bias
WARNING Stressing device beyond ``Absolute Maximum Ratings'' cause permanent damage These stress ratings only Operation beyond ``Operating Conditions'' recommended extended exposure beyond ``Operating Conditions'' affect device reliability
NOTES
Operating temperature commercial product defined this specification Minimum voltage input output pins During transitions this level undershoot periods Maximum voltage input output pins which during transitions overshoot periods Maximum voltage overshoot periods Maximum voltage overshoot periods Output shorted more than second more than output shorted time
Storage Temperature Voltage (except 0V(2) with Respect Voltage 5V(2 with Respect Program Voltage with Respect during Block Erase 0V(2 Word Byte Write Supply Voltage 0V(2) with Respect Output Short Circuit Current
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COMMERCIAL OPERATING CONDITIONS
Table Commercial Temperature Operating Conditions Symbol Parameter Operating Temperature Supply Voltage Supply Voltage (10%) Supply Voltage (5%) Notes
Units Volts Volts Volts
NOTES specifications apply product versions their standard test configuration specifications apply version high-speed test configuration
Applying Voltages
When applying voltage device delay required before initiating device operation depending ramp rate ramps slower than then delay required ramps faster than then delay required before initiating device operation recommended during power-up protect against spurious write signals when between VLKO VCCMIN Ramp Rate
Required Timing delay required delay time required before device operation initiated including read operations command writes program operations erase operations This delay measured beginning from time reaches VCCMIN operation operation)
NOTES These requirements must strictly followed guarantee other read write specifications switch between operation system should first transition from existing voltage range then voltage time supply drops below VCCMIN chip reset aborting operations pending progress These guidelines must followed transition from
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Characteristics
Table Characteristics (Commercial) Prod Parameter Note ICCS Input Load Current Output Leakage Current Standby Current BV-60 BV-80 BV-120
Unit
Test Conditions
BYTE
ICCD Deep Power-Down Current Read Current Word Byte
CMOS INPUTS (5V) IOUT Inputs INPUTS (5V) IOUT Inputs VPPH1 Word Write Progress VPPH2 12V) Word Write Progress VPPH1 Block Erase Progress VPPH2 12V) Block Erase Progress
ICCR
ICCW
Write Current Word Byte
ICCE
Erase Current
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Table Characteristics (Commercial) (Continued) Prod Parameter Note ICCES IPPS IPPD IPPR IPPW Erase Suspend Current Standby Current Deep Power-Down Current Read Current Word Byte Current
BV-60 BV-80 BV-120
Unit
Test Conditions
Block Erase Suspend VPPH2
VPPH2 VPPH1 Word Write Progress VPPH2 12V) Word Write Progress
IPPE
Erase Current
VPPH1 Block Erase Progress VPPH2 12V) Block Erase Progress
IPPES
Erase Suspend Current Boot Block Unlock Current Intelligent Identifier Current
VPPH Block Erase Suspend Progress
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Table Characteristics (Commercial) (Continued) Prod Parameter Note VOH1 VOH2 Intelligent Identifier Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage (TTL) Output High Voltage (CMOS) VPPLK Lock-Out Voltage
BV-60 BV-80 BV-120
Unit
Test Conditions
Total Write Protect Boot Block Unlock
VPPH1 (Prog Erase Operations) VPPH2 (Prog Erase Operations) VLKO Erase Write Lock Voltage Unlock Voltage
Table Capacitance MHz) Symbol COUT Parameter Input Capacitance Output Capacitance Note Unit Conditions VOUT
NOTES currents unless otherwise noted Typical values These currents valid product versions (packages speeds) ICCES specified with device deselected device read while erase suspend mode current draw ICCES ICCR Block erases word byte writes inhibited when VPPLK guaranteed range between VPPH1 VPPLK Sampled 100% tested Automatic Power Savings (APS) reduces ICCR less than typical static operation CMOS Inputs either Inputs either 28F004B address follows COUT capacitance numbers parts VLKO both operations
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NOTE test inputs driven logic ``1'' logic Input timing begins output timing ends Input rise fall times (10% 90%)
Figure Inputs Measurement Points
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NOTE test inputs driven VTTL) logic ``1'' VTTL) logic Input timing begins VTTL) VTTL) Output timing ends Input rise fall times (10% 90%)
Figure Inputs Measurement Points Test Configuration Component Values Test Configuration Standard Test Standard Test High-Speed Test
NOTE includes capacitance
(pF)
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NOTE table component values
Figure Test Configuration
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Characteristics
Table Characteristics Read Only Operations (Commercial) Prod Parameter Load Note tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output High Output Output High 3V(5) BV-60 5%(6) 10%(7) Unit
Output Hold from Address Change Whichever Occurs First BYTE High High
tELFL tELFH tAVFL tFLQV tFHQV tFLQZ
Address BYTE BYTE BYTE
Output Delay Output High
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Table Characteristics Read Only Operations (Commercial) (Continued) Parameter Load BV-80 3V(5) 10%(7) BV-120 3V(5) 10%(7) Unit
Notes tAVAV Read Cycle Time tAVQV Address Output Delay tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ Output Delay Output Delay Output Delay Output Output High Output Output High
Output Hold from Address Change Whichever Occurs First High High
tELFL BYTE tELFH tAVFL Address BYTE tFLQV BYTE tFHQV
Output Delay
tFLQZ BYTE Output High
NOTES Input Output Reference Waveform timing measurements delayed after falling edge without impact Sampled 100% tested tFLQV BYTE switching valid output delay will equal tAVQV measured from time DQ15 becomes valid Test Configurations (Figure Standard Test component values Test Configurations (Figure High-Speed Test component values Test Configurations (Figure Standard Test component values
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Figure Waveforms Read Operations
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Figure BYTE
Timing Diagram Read Operations
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Table Characteristics Controlled Write Operations (Commercial) Prod Parameter Load Note tAVAV tPHWL tELWL Write Cycle Time Setup Setup Going Going 3V(9) High BV-60 5%(10) 10%(10) Unit
tPHHWH Boot Block Lock Setup Going High tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQWL tQVPH tPHBR Setup Going High Going
Address Setup High Data Setup Pulse Width
Going High
Data Hold Time from
Address Hold Time from High Hold Time from Pulse Width High High
Duration Word Byte Program Duration Erase (Boot) Duration Erase (Parameter) Duration Erase (Main) Hold from Valid Hold from Valid Boot-Block Lock Delay
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Table Characteristics Controlled Write Operations (Commercial) (Continued) BV-80 Parameter Load Notes tAVAV tPHWL tELWL Write Cycle Time Setup Going Setup Going 3V(9) 10%(11) BV-120 3V(9) 10%(11) Unit
tPHHWH Boot Block Lock Setup Going High tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL Setup Going High Address Setup Going High Data Setup Going High Pulse Width
Data Hold Time from High Address Hold Time from High Hold Time from High Pulse Width High
tWHQV1 Word Byte Program Time tWHQV2 Erase Duration (Boot) tWHQV3 Erase Duration (Param) tWHQV4 Erase Duration (Main) tQWL tQVPH tPHBR Hold from Valid Hold from Valid Boot-Block Lock Delay
4-MBIT SmartVoltage BOOT BLOCK FAMILNOTES Read timing characteristics during write erase operations same during read-only operations Refer characteristics during read mode on-chip completely automates program erase operations program erase algorithms controlled internally which includes verify margining operations Refer command definition table valid (Table Refer command definition table valid (Table Program erase durations measured valid data (successful operation boot block program erase should held should held until operation completes successfully Time tPHBR required successful locking boot block Sampled 100% tested Test Configurations (Figure Standard Test component values Test Configurations (Figure High-Speed Test component values Test Configurations (Figure Standard Test component values
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Figure Waveforms Write Erase Operations Controlled Writes)
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Table Characteristics Controlled Write Operations (Commercial) Prod Parameter Load Note tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQWL tQVPH tPHBR Write Cycle Time High Recovery Going Setup Going 3V(9) High High BV-60 5%(10) 10%(11) Unit
Boot Block Lock Setup Going High Setup Going High Going
Address Setup High Data Setup Pulse Width
Going High
Data Hold Time from
Address Hold Time from High Hold Time from Pulse Width High
Duration Word Byte Programming Operation Erase Duration (Boot) Erase Duration (Param) Erase Duration(Main) Hold from Valid Hold from Valid Boot-Block Lock Delay
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Table Characteristics Controlled Write Operations (Commercial) (Continued) BV-80 Parameter Load Notes tAVAV tPHEL tWLEL Write Cycle Time High Recovery Going 3V(9) 10%(11) BV-120 3V(9) 10%(11) Unit
Setup Going
tPHHEH Boot Block Lock Setup Going High tVPEH tAVEH tDVEH tELEH tEHDX tEHAX Setup High Going
Address Setup Going High Data Setup Going High Pulse Width
Data Hold Time from High Address Hold Time from High
tEHWH Hold Time from High tEHEL Pulse Width High
tEHQV1 Duration Word Byte Programming Operation tEHQV2 Erase Duration (Boot) tEHQV3 Erase Duration (Param) tEHQV4 Erase Duration(Main) tQWL tQVPH tPHBR Hold from Valid Hold from Valid Boot-Block Lock Delay
NOTES Controlled Write Operations notes through Chip-Enable controlled writes write operations driven valid combination systems where defines write pulse-width (within longer timing waveform) set-up hold inactive times should measured relative waveform
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Figure Alternate Waveforms Write Erase Operations Controlled Writes)
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Table Erase Program Timings (Commercial Parameter Boot Parameter Block Erase Time Main Block Erase Time Main Block Write Time (Byte Mode) Main Block Write Time (Word Mode) Byte Write Time Word Write Time Unit
NOTES numbers sampled 100% tested erase times specified under worst case conditions erase times tested same value independent Note typical conditions Typical conditions with center specifed voltage range Production programming using typically results reduction programming time Contact your Intel representative information regarding maximum byte word write specifications
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EXTENDED OPERATING CONDITIONS
Table Extended Temperature Operating Conditions Symbol Parameter Operating Temperature Supply Voltage Supply Voltage Supply Voltage (10%) Notes
Units Volts Volts Volts
NOTES specifications valid both voltage ranges Characteristics tables voltage range-specific specifications specifications apply versions their standard test configuration
Applying Voltages
When applying voltage device delay required before initiating device operation depending ramp rate ramps slower than then delay required ramps faster than then delay required before initiating device operation recommended during power-up protect against spurious write signals when between VLKO VCCMIN Ramp Rate
Required Timing delay required delay time required before device operation initiated including read operations command writes program operations erase operations This delay measured beginning from time reaches VCCMIN operation operation operation)
NOTES These requirements must strictly followed guarantee other read write specifications switch between operation system should first transition from existing voltage range then voltage time supply drops below VCCMIN chip reset aborting operations pending progress These guidelines must followed transition from
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Characteristics
Table Characteristics Extended Temperature Operation Prod Parameter Notes Input Load Current Output Leakage Current Standby Current TBE-120
TBV-80
TBV-80 TBE-120
Unit
Test Conditions
VCCMax CMOS Levels Levels BYTE CMOS INPUTS (5V) IOUT Inputs INPUTS (5V) IOUT Inputs
ICCS
ICCD
Deep Power-Down Current Read Current Word Byte
ICCR
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Table Characteristics Extended Temperature Operation (Continued) Prod Parameter Notes ICCW Write Current Word Byte Erase Current TBE-120 ICCES Erase Suspend Current Standby Current Deep Power-Down Current Read Current Write Current Word Byte TBV-80 TBV-80 TBE-120 VPPH1 Word Write Progress VPPH2 12V) Word Write Progress VPPH1 Erase Progress VPPH2 12V) Erase Progress Block Erase Suspend VPPH1 VPPH2 Unit Test Conditions
ICCE
IPPS
IPPD
IPPR IPPW
VPPH2 VPPH1 Word Write Progress VPPH2 12V) Word Write Progress
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Characteristics Extended Temperature Operation (Continued) Prod Parameter Notes IPPE Erase Current TBE-120 IPPES Erase Suspend Current Boot Block Unlock Current Intelligent Identifier Current TBV-80 TBV-80 TBE-120 VPPH1 Block Erase Progress VPPH2 12V) Block Erase Progress VPPH Block Erase Suspend Progress Unit Test Conditions
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Characteristics Extended Temperature Operation (Continued) Prod Parameter Notes Intelligent Identifier Voltage Input Voltage Input High Voltage Output Voltage TBE-120 TBV-90 TBV-90 TBE-120 Unit Test Conditions
(5V) Complete Write Protection
VOH1 VOH2
Output High Voltage (TTL) Output High Voltage High Voltage (CMOS)
VPPLK Lock-Out Voltage VPPH1 during VPPH2 Prog Erase Operations VLKO Erase Write Lock Voltage Unlock Voltage
Boot Block Write Erase
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Table Capacitance MHz) Symbol COUT Parameter Input Capacitance Output Capacitance Note Unit Conditions VOUT
NOTES currents unless otherwise noted Typical values These currents valid product versions (packages speeds) ICCES specified with device de-selected device read while erase suspend current draw ICCES ICCR Block erases word byte writes inhibited when VPPLK guaranteed range between VPPH1 VPPLK Sampled 100% tested Automatic Power Savings (APS) reduces ICCR less than typical static operation CMOS Inputs either Inputs either 28F004B address follows COUT capacitance numbers parts VLKO operations
4-MBIT SmartVoltage BOOT BLOCK FAMIL
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NOTE test inputs driven logic ``1'' logic Input timing begins output timing ends Input rise fall times (10% 90%)
Figure Input Range Measurement Points
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NOTE test inputs driven logic ``1'' logic Input timing begins output timing ends Input rise fall times (10% 90%)
Figure Input Range Measurement Points
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NOTE test inputs driven VTTL) logic ``1'' VTTL) logic Input timing begins VTTL) VTTL) Output timing ends Input rise fall times (10% 90%)
Figure Input Range Measurement Points Test Configuration Component Values Test Configuration Standard Test Standard Test
NOTE includes capacitance
(pF)
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NOTE table component values
Figure Test Configuration
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Characteristics
Table Characteristics Read Only Operations(1) (Extended Temperature) Prod Parameter Load Notes tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output High Output Output High TBE-120 6V(5) TBV-80 3V(5) TBV-80 TBE-120 10%(6) Unit
Output Hold from Address Change Whichever Occurs First BYTE High High
tELFL tELFH tAVFL tFLQV tFHQV tFLQZ
Address BYTE BYTE BYTE
Output Delay Output High
NOTES Input Output Reference Waveform timing measurements delayed after falling edge without impact Sampled 100% tested tFLQV BYTE switching valid output delay will equal tAVQV measured from time DQ15 becomes valid Test Configurations (Figure Standard Test component values Test Configurations (Figure Standard Test component values
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Table Characteristics -Controlled Write Operations(1) (Extended Temperature) Prod Parameter Load Notes tAVAV tPHWL tELWL Write Cycle Time High Recovery Going Setup Going TBE-120 6V(9) High TBV-80 3V(9) TBV-80 TBE-120 10%(10) Unit
tPHHWH Boot Block Lock Setup Going High tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQWL tQVPH tPHBR Setup Going High Going
Address Setup High Data Setup Pulse Width
Going High
Data Hold Time from
Address Hold Time from High Hold Time from Pulse Width High High
Word Byte Program Time Erase Duration (Boot) Erase Duration (Param) Erase Duration (Main) Hold from Valid Hold from Valid Boot-Block Lock Delay
4-MBIT SmartVoltage BOOT BLOCK FAMILNOTES Read timing characteristics during write erase operations same during read-only operations Refer Characteristics during read mode on-chip completely automates program erase operations program erase algorithms controlled internally which includes verify margining operations Refer command definition table valid (Table Refer command definition table valid (Table Program erase durations measured valid data (successful operation boot block program erase should held should held until operation completes successfully Time tPHBR required successful locking boot block Sampled 100% tested Test Configurations (Figure Standard Test component values Test Configurations (Figure Standard Test component values
4-MBIT SmartVoltage BOOT BLOCK FAMIL
Table Characteristics Controlled Write Operations (Extended Temperature) Prod Parameter Load Notes tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQWL tQVPH tPHBR Write Cycle Time High Recovery Going Setup Going TBE-120 6V(9) High TBV-80 3V(9) TBV-80 TBE-120 10%(10) Unit
Boot Block Lock Setup Going High Setup Going High Going
Address Setup High Data Setup Pulse Width
Going High
Data Hold Time from
Address Hold Time from High Hold Time from Pulse Width High High
Word Byte Program Time Erase Duration (Boot) Erase Duration (Param) Erase Duration (Main) Hold from Valid Hold from Valid Boot-Block Lock Delay
NOTES Controlled Write Operations notes through Chip-Enable controlled writes write operations driven valid combination systems where defines write pulse-width (within longer timing waveform) set-up hold inactive times should measured relative waveform
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Table Erase Program Timings (Extended Parameter Boot Parameter Block Erase Time Main Block Erase Time Main Block Write Time (Byte Mode) Main Block Write Time (Word Mode) Byte Write Time Word Write Time 7V-3 Unit
NOTES numbers sampled 100% tested erase times specified under worst case conditions erase times tested same value independent Note typical conditions Typical conditions with center specifed voltage range Production programming using typically results reduction programming time Contact your Intel representative information regarding maximum byte word write specifications
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ADDITIONAL INFORMATION Ordering Information
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VALID COMBINATIONS 40-Lead TSOP Commercial E28F004BVT60 E28F004BVB60 E28F004BVT80 E28F004BVB80 E28F004BVT120 E28F004BVB120 Extended TE28F004BVT80 TE28F004BVB80 TE28F004BET120 TE28F004BEB120
44-Lead PSOP PA28F400BVT60 PA28F400BVB60 PA28F400BVT80 PA28F400BVB80 PA28F400BVT120 PA28F400BVB120 TB28F400BVT80 TB28F400BVB80
48-Lead TSOP E28F400CVT60 E28F400CVB60 E28F400CVT80 E28F400CVB80
56-Lead TSOP E28F400BVT60 E28F400BVB60 E28F400BVT80 E28F400BVB80
TE28F400CVT80 TE28F400CVB80 TE28F400CET120 TE28F400CEB120
TE27F400BVT80 TE27F400BVB80
Table Summary Line Items Name 28F004BV 28F400BV 28F400CV 28F004BE 28F400CE 40-Ld 44-Ld 48-Ld 56-Ld TSOP PSOP TSOP TSOP
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References
Order Number 290531 290539 290448 290449 290450 290451 292148 292172 292130 292154 Document 2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 28F002 200BX-T 2-Mbit Boot Block Flash Memory Datasheet 28F002 200BL-T 2-Mbit Power Boot Block Flash Memory Datasheet 28F004 400BL-T 4-Mbit Power Boot Block Flash Memory Datasheet 28F004 400BX-T 4-Mbit Boot Block Flash Memory Datasheet AP-604 ``Using Intel's Boot Block Flash Memory Parameter Blocks Replace EEPROM'' AP-617 ``Additional Flash Data Protection Using
AB-57 ``Boot Block Architecture Safe Firmware Updates'' AB-60 8-Mbit SmartVoltage Boot Block Flash Memory Family''
Revision History
Number -001 -002 Initial release datasheet Status changed from Product Preview Preliminary 28F400CV references information added throughout specs added throughout following sections have been changed rewritten 3321 Note added Figure clarify 28F008B pinout 28F008SA Sentence about program erase timeout deleted from Section Erroneous arrows leading error states deleted from flowcharts Figs Sections changed ``Applying Voltages These sections completely changed clarify ramp requirements IPPD Commercial spec changed from Capacitance tables added after Commercial Extended Characteristics tables Test slew rate notes added Figs Test configuration drawings (Fig consolidated into with component values table (Component values also rounded tELFL tELFH tAVFL changed from BV-60 Commercial TBV-80 Extended BV-80 BV-120 Commercial tWHAX tEHAX changed from tPHWL changed from 1000 BV-80 BV-120 Commercial tPHEL changed from 1000 BV-60 BV-80 BV-120 Commercial 28F400BE removed from Table Applying voltages (Sections rewritten clarity Minor cosmetic changes edits Description
-003

Intel SmartVoltage Technology Program Erase Read Operation Increased P

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